1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This defines functionality used to emit comments about X86 instructions to
11 // an output stream for -fverbose-asm.
13 //===----------------------------------------------------------------------===//
15 #include "X86InstComments.h"
16 #include "MCTargetDesc/X86MCTargetDesc.h"
17 #include "Utils/X86ShuffleDecode.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/CodeGen/MachineValueType.h"
20 #include "llvm/Support/raw_ostream.h"
24 static unsigned getVectorRegSize(unsigned RegNo) {
25 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
27 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
29 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
31 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
34 llvm_unreachable("Unknown vector reg!");
38 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
39 unsigned OperandIndex) {
40 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
41 return MVT::getVectorVT(ScalarVT,
42 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
45 /// \brief Extracts the src/dst types for a given zero extension instruction.
46 /// \note While the number of elements in DstVT type correct, the
47 /// number in the SrcVT type is expanded to fill the src xmm register and the
48 /// upper elements may not be included in the dst xmm/ymm register.
49 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
50 switch (MI->getOpcode()) {
52 llvm_unreachable("Unknown zero extension instruction");
56 case X86::VPMOVZXBWrm:
57 case X86::VPMOVZXBWrr:
61 case X86::VPMOVZXBWYrm:
62 case X86::VPMOVZXBWYrr:
68 case X86::VPMOVZXBDrm:
69 case X86::VPMOVZXBDrr:
73 case X86::VPMOVZXBDYrm:
74 case X86::VPMOVZXBDYrr:
80 case X86::VPMOVZXBQrm:
81 case X86::VPMOVZXBQrr:
85 case X86::VPMOVZXBQYrm:
86 case X86::VPMOVZXBQYrr:
93 case X86::VPMOVZXWDrm:
94 case X86::VPMOVZXWDrr:
98 case X86::VPMOVZXWDYrm:
99 case X86::VPMOVZXWDYrr:
103 case X86::PMOVZXWQrm:
104 case X86::PMOVZXWQrr:
105 case X86::VPMOVZXWQrm:
106 case X86::VPMOVZXWQrr:
110 case X86::VPMOVZXWQYrm:
111 case X86::VPMOVZXWQYrr:
115 // i32 zero extension
116 case X86::PMOVZXDQrm:
117 case X86::PMOVZXDQrr:
118 case X86::VPMOVZXDQrm:
119 case X86::VPMOVZXDQrr:
123 case X86::VPMOVZXDQYrm:
124 case X86::VPMOVZXDQYrr:
131 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
132 case X86::V##Inst##Suffix##src: \
133 case X86::V##Inst##Suffix##src##k: \
134 case X86::V##Inst##Suffix##src##kz:
136 #define CASE_SSE_INS_COMMON(Inst, src) \
139 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
140 case X86::V##Inst##Suffix##src:
142 #define CASE_MOVDUP(Inst, src) \
143 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
144 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
145 CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
146 CASE_AVX_INS_COMMON(Inst, , r##src) \
147 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
148 CASE_SSE_INS_COMMON(Inst, r##src) \
150 #define CASE_VSHUF(Inst, src) \
151 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
152 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
153 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
154 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) \
156 /// \brief Extracts the types and if it has memory operand for a given
157 /// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
158 static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
160 switch (MI->getOpcode()) {
162 llvm_unreachable("Unknown VSHUF64x2 family instructions.");
165 HasMemOp = true; // FALL THROUGH.
167 VT = getRegOperandVectorVT(MI, MVT::i64, 0);
170 HasMemOp = true; // FALL THROUGH.
172 VT = getRegOperandVectorVT(MI, MVT::i32, 0);
177 //===----------------------------------------------------------------------===//
178 // Top Level Entrypoint
179 //===----------------------------------------------------------------------===//
181 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
182 /// newline terminated strings to the specified string if desired. This
183 /// information is shown in disassembly dumps when verbose assembly is enabled.
184 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
185 const char *(*getRegName)(unsigned)) {
186 // If this is a shuffle operation, the switch should fill in this state.
187 SmallVector<int, 8> ShuffleMask;
188 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
190 switch (MI->getOpcode()) {
192 // Not an instruction for which we can decode comments.
195 case X86::BLENDPDrri:
196 case X86::VBLENDPDrri:
197 case X86::VBLENDPDYrri:
198 Src2Name = getRegName(MI->getOperand(2).getReg());
200 case X86::BLENDPDrmi:
201 case X86::VBLENDPDrmi:
202 case X86::VBLENDPDYrmi:
203 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
204 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
205 MI->getOperand(MI->getNumOperands() - 1).getImm(),
207 Src1Name = getRegName(MI->getOperand(1).getReg());
208 DestName = getRegName(MI->getOperand(0).getReg());
211 case X86::BLENDPSrri:
212 case X86::VBLENDPSrri:
213 case X86::VBLENDPSYrri:
214 Src2Name = getRegName(MI->getOperand(2).getReg());
216 case X86::BLENDPSrmi:
217 case X86::VBLENDPSrmi:
218 case X86::VBLENDPSYrmi:
219 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
220 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
221 MI->getOperand(MI->getNumOperands() - 1).getImm(),
223 Src1Name = getRegName(MI->getOperand(1).getReg());
224 DestName = getRegName(MI->getOperand(0).getReg());
227 case X86::PBLENDWrri:
228 case X86::VPBLENDWrri:
229 case X86::VPBLENDWYrri:
230 Src2Name = getRegName(MI->getOperand(2).getReg());
232 case X86::PBLENDWrmi:
233 case X86::VPBLENDWrmi:
234 case X86::VPBLENDWYrmi:
235 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
236 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
237 MI->getOperand(MI->getNumOperands() - 1).getImm(),
239 Src1Name = getRegName(MI->getOperand(1).getReg());
240 DestName = getRegName(MI->getOperand(0).getReg());
243 case X86::VPBLENDDrri:
244 case X86::VPBLENDDYrri:
245 Src2Name = getRegName(MI->getOperand(2).getReg());
247 case X86::VPBLENDDrmi:
248 case X86::VPBLENDDYrmi:
249 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
250 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
251 MI->getOperand(MI->getNumOperands() - 1).getImm(),
253 Src1Name = getRegName(MI->getOperand(1).getReg());
254 DestName = getRegName(MI->getOperand(0).getReg());
257 case X86::INSERTPSrr:
258 case X86::VINSERTPSrr:
259 Src2Name = getRegName(MI->getOperand(2).getReg());
261 case X86::INSERTPSrm:
262 case X86::VINSERTPSrm:
263 DestName = getRegName(MI->getOperand(0).getReg());
264 Src1Name = getRegName(MI->getOperand(1).getReg());
265 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
266 DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
271 case X86::VMOVLHPSrr:
272 Src2Name = getRegName(MI->getOperand(2).getReg());
273 Src1Name = getRegName(MI->getOperand(1).getReg());
274 DestName = getRegName(MI->getOperand(0).getReg());
275 DecodeMOVLHPSMask(2, ShuffleMask);
279 case X86::VMOVHLPSrr:
280 Src2Name = getRegName(MI->getOperand(2).getReg());
281 Src1Name = getRegName(MI->getOperand(1).getReg());
282 DestName = getRegName(MI->getOperand(0).getReg());
283 DecodeMOVHLPSMask(2, ShuffleMask);
286 CASE_MOVDUP(MOVSLDUP, r)
287 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
289 CASE_MOVDUP(MOVSLDUP, m) {
290 MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
291 DestName = getRegName(MI->getOperand(0).getReg());
292 DecodeMOVSLDUPMask(VT, ShuffleMask);
296 CASE_MOVDUP(MOVSHDUP, r)
297 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
299 CASE_MOVDUP(MOVSHDUP, m) {
300 MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
301 DestName = getRegName(MI->getOperand(0).getReg());
302 DecodeMOVSHDUPMask(VT, ShuffleMask);
306 case X86::VMOVDDUPYrr:
307 Src1Name = getRegName(MI->getOperand(1).getReg());
309 case X86::VMOVDDUPYrm:
310 DestName = getRegName(MI->getOperand(0).getReg());
311 DecodeMOVDDUPMask(MVT::v4f64, ShuffleMask);
315 case X86::VMOVDDUPrr:
316 Src1Name = getRegName(MI->getOperand(1).getReg());
319 case X86::VMOVDDUPrm:
320 DestName = getRegName(MI->getOperand(0).getReg());
321 DecodeMOVDDUPMask(MVT::v2f64, ShuffleMask);
326 case X86::VPSLLDQYri:
327 Src1Name = getRegName(MI->getOperand(1).getReg());
328 DestName = getRegName(MI->getOperand(0).getReg());
329 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
330 DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
331 MI->getOperand(MI->getNumOperands() - 1).getImm(),
337 case X86::VPSRLDQYri:
338 Src1Name = getRegName(MI->getOperand(1).getReg());
339 DestName = getRegName(MI->getOperand(0).getReg());
340 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
341 DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
342 MI->getOperand(MI->getNumOperands() - 1).getImm(),
346 case X86::PALIGNR128rr:
347 case X86::VPALIGNR128rr:
348 case X86::VPALIGNR256rr:
349 Src1Name = getRegName(MI->getOperand(2).getReg());
351 case X86::PALIGNR128rm:
352 case X86::VPALIGNR128rm:
353 case X86::VPALIGNR256rm:
354 Src2Name = getRegName(MI->getOperand(1).getReg());
355 DestName = getRegName(MI->getOperand(0).getReg());
356 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
357 DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
358 MI->getOperand(MI->getNumOperands() - 1).getImm(),
364 case X86::VPSHUFDYri:
365 Src1Name = getRegName(MI->getOperand(1).getReg());
369 case X86::VPSHUFDYmi:
370 DestName = getRegName(MI->getOperand(0).getReg());
371 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
372 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
373 MI->getOperand(MI->getNumOperands() - 1).getImm(),
378 case X86::VPSHUFHWri:
379 case X86::VPSHUFHWYri:
380 Src1Name = getRegName(MI->getOperand(1).getReg());
383 case X86::VPSHUFHWmi:
384 case X86::VPSHUFHWYmi:
385 DestName = getRegName(MI->getOperand(0).getReg());
386 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
387 DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
388 MI->getOperand(MI->getNumOperands() - 1).getImm(),
393 case X86::VPSHUFLWri:
394 case X86::VPSHUFLWYri:
395 Src1Name = getRegName(MI->getOperand(1).getReg());
398 case X86::VPSHUFLWmi:
399 case X86::VPSHUFLWYmi:
400 DestName = getRegName(MI->getOperand(0).getReg());
401 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
402 DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
403 MI->getOperand(MI->getNumOperands() - 1).getImm(),
407 case X86::MMX_PSHUFWri:
408 Src1Name = getRegName(MI->getOperand(1).getReg());
410 case X86::MMX_PSHUFWmi:
411 DestName = getRegName(MI->getOperand(0).getReg());
412 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
413 DecodePSHUFMask(MVT::v4i16,
414 MI->getOperand(MI->getNumOperands() - 1).getImm(),
419 Src1Name = getRegName(MI->getOperand(1).getReg());
422 DestName = getRegName(MI->getOperand(0).getReg());
423 DecodePSWAPMask(MVT::v2i32, ShuffleMask);
426 case X86::MMX_PUNPCKHBWirr:
427 case X86::PUNPCKHBWrr:
428 case X86::VPUNPCKHBWrr:
429 case X86::VPUNPCKHBWYrr:
430 Src2Name = getRegName(MI->getOperand(2).getReg());
432 case X86::MMX_PUNPCKHBWirm:
433 case X86::PUNPCKHBWrm:
434 case X86::VPUNPCKHBWrm:
435 case X86::VPUNPCKHBWYrm:
436 Src1Name = getRegName(MI->getOperand(1).getReg());
437 DestName = getRegName(MI->getOperand(0).getReg());
438 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
441 case X86::MMX_PUNPCKHWDirr:
442 case X86::PUNPCKHWDrr:
443 case X86::VPUNPCKHWDrr:
444 case X86::VPUNPCKHWDYrr:
445 Src2Name = getRegName(MI->getOperand(2).getReg());
447 case X86::MMX_PUNPCKHWDirm:
448 case X86::PUNPCKHWDrm:
449 case X86::VPUNPCKHWDrm:
450 case X86::VPUNPCKHWDYrm:
451 Src1Name = getRegName(MI->getOperand(1).getReg());
452 DestName = getRegName(MI->getOperand(0).getReg());
453 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
456 case X86::MMX_PUNPCKHDQirr:
457 case X86::PUNPCKHDQrr:
458 case X86::VPUNPCKHDQrr:
459 case X86::VPUNPCKHDQYrr:
460 case X86::VPUNPCKHDQZrr:
461 Src2Name = getRegName(MI->getOperand(2).getReg());
463 case X86::MMX_PUNPCKHDQirm:
464 case X86::PUNPCKHDQrm:
465 case X86::VPUNPCKHDQrm:
466 case X86::VPUNPCKHDQYrm:
467 case X86::VPUNPCKHDQZrm:
468 Src1Name = getRegName(MI->getOperand(1).getReg());
469 DestName = getRegName(MI->getOperand(0).getReg());
470 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
473 case X86::PUNPCKHQDQrr:
474 case X86::VPUNPCKHQDQrr:
475 case X86::VPUNPCKHQDQYrr:
476 case X86::VPUNPCKHQDQZrr:
477 Src2Name = getRegName(MI->getOperand(2).getReg());
479 case X86::PUNPCKHQDQrm:
480 case X86::VPUNPCKHQDQrm:
481 case X86::VPUNPCKHQDQYrm:
482 case X86::VPUNPCKHQDQZrm:
483 Src1Name = getRegName(MI->getOperand(1).getReg());
484 DestName = getRegName(MI->getOperand(0).getReg());
485 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
488 case X86::MMX_PUNPCKLBWirr:
489 case X86::PUNPCKLBWrr:
490 case X86::VPUNPCKLBWrr:
491 case X86::VPUNPCKLBWYrr:
492 Src2Name = getRegName(MI->getOperand(2).getReg());
494 case X86::MMX_PUNPCKLBWirm:
495 case X86::PUNPCKLBWrm:
496 case X86::VPUNPCKLBWrm:
497 case X86::VPUNPCKLBWYrm:
498 Src1Name = getRegName(MI->getOperand(1).getReg());
499 DestName = getRegName(MI->getOperand(0).getReg());
500 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
503 case X86::MMX_PUNPCKLWDirr:
504 case X86::PUNPCKLWDrr:
505 case X86::VPUNPCKLWDrr:
506 case X86::VPUNPCKLWDYrr:
507 Src2Name = getRegName(MI->getOperand(2).getReg());
509 case X86::MMX_PUNPCKLWDirm:
510 case X86::PUNPCKLWDrm:
511 case X86::VPUNPCKLWDrm:
512 case X86::VPUNPCKLWDYrm:
513 Src1Name = getRegName(MI->getOperand(1).getReg());
514 DestName = getRegName(MI->getOperand(0).getReg());
515 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
518 case X86::MMX_PUNPCKLDQirr:
519 case X86::PUNPCKLDQrr:
520 case X86::VPUNPCKLDQrr:
521 case X86::VPUNPCKLDQYrr:
522 case X86::VPUNPCKLDQZrr:
523 Src2Name = getRegName(MI->getOperand(2).getReg());
525 case X86::MMX_PUNPCKLDQirm:
526 case X86::PUNPCKLDQrm:
527 case X86::VPUNPCKLDQrm:
528 case X86::VPUNPCKLDQYrm:
529 case X86::VPUNPCKLDQZrm:
530 Src1Name = getRegName(MI->getOperand(1).getReg());
531 DestName = getRegName(MI->getOperand(0).getReg());
532 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
535 case X86::PUNPCKLQDQrr:
536 case X86::VPUNPCKLQDQrr:
537 case X86::VPUNPCKLQDQYrr:
538 case X86::VPUNPCKLQDQZrr:
539 Src2Name = getRegName(MI->getOperand(2).getReg());
541 case X86::PUNPCKLQDQrm:
542 case X86::VPUNPCKLQDQrm:
543 case X86::VPUNPCKLQDQYrm:
544 case X86::VPUNPCKLQDQZrm:
545 Src1Name = getRegName(MI->getOperand(1).getReg());
546 DestName = getRegName(MI->getOperand(0).getReg());
547 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
551 case X86::VSHUFPDrri:
552 case X86::VSHUFPDYrri:
553 Src2Name = getRegName(MI->getOperand(2).getReg());
556 case X86::VSHUFPDrmi:
557 case X86::VSHUFPDYrmi:
558 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
559 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
560 MI->getOperand(MI->getNumOperands() - 1).getImm(),
562 Src1Name = getRegName(MI->getOperand(1).getReg());
563 DestName = getRegName(MI->getOperand(0).getReg());
567 case X86::VSHUFPSrri:
568 case X86::VSHUFPSYrri:
569 Src2Name = getRegName(MI->getOperand(2).getReg());
572 case X86::VSHUFPSrmi:
573 case X86::VSHUFPSYrmi:
574 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
575 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
576 MI->getOperand(MI->getNumOperands() - 1).getImm(),
578 Src1Name = getRegName(MI->getOperand(1).getReg());
579 DestName = getRegName(MI->getOperand(0).getReg());
585 CASE_VSHUF(32X4, m) {
588 unsigned NumOp = MI->getNumOperands();
589 getVSHUF64x2FamilyInfo(MI, VT, HasMemOp);
590 decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(),
592 DestName = getRegName(MI->getOperand(0).getReg());
594 assert((NumOp >= 8) && "Expected at least 8 operands!");
595 Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg());
597 assert((NumOp >= 4) && "Expected at least 4 operands!");
598 Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg());
599 Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg());
604 case X86::UNPCKLPDrr:
605 case X86::VUNPCKLPDrr:
606 case X86::VUNPCKLPDYrr:
607 case X86::VUNPCKLPDZrr:
608 Src2Name = getRegName(MI->getOperand(2).getReg());
610 case X86::UNPCKLPDrm:
611 case X86::VUNPCKLPDrm:
612 case X86::VUNPCKLPDYrm:
613 case X86::VUNPCKLPDZrm:
614 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
615 Src1Name = getRegName(MI->getOperand(1).getReg());
616 DestName = getRegName(MI->getOperand(0).getReg());
619 case X86::UNPCKLPSrr:
620 case X86::VUNPCKLPSrr:
621 case X86::VUNPCKLPSYrr:
622 case X86::VUNPCKLPSZrr:
623 Src2Name = getRegName(MI->getOperand(2).getReg());
625 case X86::UNPCKLPSrm:
626 case X86::VUNPCKLPSrm:
627 case X86::VUNPCKLPSYrm:
628 case X86::VUNPCKLPSZrm:
629 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
630 Src1Name = getRegName(MI->getOperand(1).getReg());
631 DestName = getRegName(MI->getOperand(0).getReg());
634 case X86::UNPCKHPDrr:
635 case X86::VUNPCKHPDrr:
636 case X86::VUNPCKHPDYrr:
637 case X86::VUNPCKHPDZrr:
638 Src2Name = getRegName(MI->getOperand(2).getReg());
640 case X86::UNPCKHPDrm:
641 case X86::VUNPCKHPDrm:
642 case X86::VUNPCKHPDYrm:
643 case X86::VUNPCKHPDZrm:
644 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
645 Src1Name = getRegName(MI->getOperand(1).getReg());
646 DestName = getRegName(MI->getOperand(0).getReg());
649 case X86::UNPCKHPSrr:
650 case X86::VUNPCKHPSrr:
651 case X86::VUNPCKHPSYrr:
652 case X86::VUNPCKHPSZrr:
653 Src2Name = getRegName(MI->getOperand(2).getReg());
655 case X86::UNPCKHPSrm:
656 case X86::VUNPCKHPSrm:
657 case X86::VUNPCKHPSYrm:
658 case X86::VUNPCKHPSZrm:
659 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
660 Src1Name = getRegName(MI->getOperand(1).getReg());
661 DestName = getRegName(MI->getOperand(0).getReg());
664 case X86::VPERMILPSri:
665 case X86::VPERMILPSYri:
666 Src1Name = getRegName(MI->getOperand(1).getReg());
668 case X86::VPERMILPSmi:
669 case X86::VPERMILPSYmi:
670 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
671 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
672 MI->getOperand(MI->getNumOperands() - 1).getImm(),
674 DestName = getRegName(MI->getOperand(0).getReg());
677 case X86::VPERMILPDri:
678 case X86::VPERMILPDYri:
679 Src1Name = getRegName(MI->getOperand(1).getReg());
681 case X86::VPERMILPDmi:
682 case X86::VPERMILPDYmi:
683 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
684 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
685 MI->getOperand(MI->getNumOperands() - 1).getImm(),
687 DestName = getRegName(MI->getOperand(0).getReg());
690 case X86::VPERM2F128rr:
691 case X86::VPERM2I128rr:
692 Src2Name = getRegName(MI->getOperand(2).getReg());
694 case X86::VPERM2F128rm:
695 case X86::VPERM2I128rm:
696 // For instruction comments purpose, assume the 256-bit vector is v4i64.
697 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
698 DecodeVPERM2X128Mask(MVT::v4i64,
699 MI->getOperand(MI->getNumOperands() - 1).getImm(),
701 Src1Name = getRegName(MI->getOperand(1).getReg());
702 DestName = getRegName(MI->getOperand(0).getReg());
706 case X86::VPERMPDYri:
707 Src1Name = getRegName(MI->getOperand(1).getReg());
710 case X86::VPERMPDYmi:
711 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
712 DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
714 DestName = getRegName(MI->getOperand(0).getReg());
719 Src2Name = getRegName(MI->getOperand(2).getReg());
720 Src1Name = getRegName(MI->getOperand(1).getReg());
724 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
725 DestName = getRegName(MI->getOperand(0).getReg());
729 Src2Name = getRegName(MI->getOperand(2).getReg());
730 Src1Name = getRegName(MI->getOperand(1).getReg());
734 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
735 DestName = getRegName(MI->getOperand(0).getReg());
738 case X86::MOVPQI2QIrr:
739 case X86::MOVZPQILo2PQIrr:
740 case X86::VMOVPQI2QIrr:
741 case X86::VMOVZPQILo2PQIrr:
742 Src1Name = getRegName(MI->getOperand(1).getReg());
744 case X86::MOVQI2PQIrm:
745 case X86::MOVZQI2PQIrm:
746 case X86::MOVZPQILo2PQIrm:
747 case X86::VMOVQI2PQIrm:
748 case X86::VMOVZQI2PQIrm:
749 case X86::VMOVZPQILo2PQIrm:
750 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
751 DestName = getRegName(MI->getOperand(0).getReg());
754 case X86::MOVDI2PDIrm:
755 case X86::VMOVDI2PDIrm:
756 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
757 DestName = getRegName(MI->getOperand(0).getReg());
761 if (MI->getOperand(2).isImm() &&
762 MI->getOperand(3).isImm())
763 DecodeEXTRQIMask(MI->getOperand(2).getImm(),
764 MI->getOperand(3).getImm(),
767 DestName = getRegName(MI->getOperand(0).getReg());
768 Src1Name = getRegName(MI->getOperand(1).getReg());
772 if (MI->getOperand(3).isImm() &&
773 MI->getOperand(4).isImm())
774 DecodeINSERTQIMask(MI->getOperand(3).getImm(),
775 MI->getOperand(4).getImm(),
778 DestName = getRegName(MI->getOperand(0).getReg());
779 Src1Name = getRegName(MI->getOperand(1).getReg());
780 Src2Name = getRegName(MI->getOperand(2).getReg());
783 case X86::PMOVZXBWrr:
784 case X86::PMOVZXBDrr:
785 case X86::PMOVZXBQrr:
786 case X86::PMOVZXWDrr:
787 case X86::PMOVZXWQrr:
788 case X86::PMOVZXDQrr:
789 case X86::VPMOVZXBWrr:
790 case X86::VPMOVZXBDrr:
791 case X86::VPMOVZXBQrr:
792 case X86::VPMOVZXWDrr:
793 case X86::VPMOVZXWQrr:
794 case X86::VPMOVZXDQrr:
795 case X86::VPMOVZXBWYrr:
796 case X86::VPMOVZXBDYrr:
797 case X86::VPMOVZXBQYrr:
798 case X86::VPMOVZXWDYrr:
799 case X86::VPMOVZXWQYrr:
800 case X86::VPMOVZXDQYrr:
801 Src1Name = getRegName(MI->getOperand(1).getReg());
803 case X86::PMOVZXBWrm:
804 case X86::PMOVZXBDrm:
805 case X86::PMOVZXBQrm:
806 case X86::PMOVZXWDrm:
807 case X86::PMOVZXWQrm:
808 case X86::PMOVZXDQrm:
809 case X86::VPMOVZXBWrm:
810 case X86::VPMOVZXBDrm:
811 case X86::VPMOVZXBQrm:
812 case X86::VPMOVZXWDrm:
813 case X86::VPMOVZXWQrm:
814 case X86::VPMOVZXDQrm:
815 case X86::VPMOVZXBWYrm:
816 case X86::VPMOVZXBDYrm:
817 case X86::VPMOVZXBQYrm:
818 case X86::VPMOVZXWDYrm:
819 case X86::VPMOVZXWQYrm:
820 case X86::VPMOVZXDQYrm: {
822 getZeroExtensionTypes(MI, SrcVT, DstVT);
823 DecodeZeroExtendMask(SrcVT, DstVT, ShuffleMask);
824 DestName = getRegName(MI->getOperand(0).getReg());
828 // The only comments we decode are shuffles, so give up if we were unable to
829 // decode a shuffle mask.
830 if (ShuffleMask.empty())
833 if (!DestName) DestName = Src1Name;
834 OS << (DestName ? DestName : "mem") << " = ";
836 // If the two sources are the same, canonicalize the input elements to be
837 // from the first src so that we get larger element spans.
838 if (Src1Name == Src2Name) {
839 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
840 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
841 ShuffleMask[i] >= (int)e) // From second mask.
846 // The shuffle mask specifies which elements of the src1/src2 fill in the
847 // destination, with a few sentinel values. Loop through and print them
849 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
852 if (ShuffleMask[i] == SM_SentinelZero) {
857 // Otherwise, it must come from src1 or src2. Print the span of elements
858 // that comes from this src.
859 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
860 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
861 OS << (SrcName ? SrcName : "mem") << '[';
863 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
864 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
869 if (ShuffleMask[i] == SM_SentinelUndef)
872 OS << ShuffleMask[i] % ShuffleMask.size();
876 --i; // For loop increments element #.
881 // We successfully added a comment to this instruction.