1 //===-- X86DisassemblerDecoder.c - Disassembler decoder -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains the implementation of the instruction decoder.
12 // Documentation for the disassembler can be found in X86Disassembler.h.
14 //===----------------------------------------------------------------------===//
16 #include <stdarg.h> /* for va_*() */
17 #include <stdio.h> /* for vsnprintf() */
18 #include <stdlib.h> /* for exit() */
19 #include <string.h> /* for memset() */
21 #include "X86DisassemblerDecoder.h"
23 using namespace llvm::X86Disassembler;
25 #include "X86GenDisassemblerTables.inc"
31 #define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0)
33 #define debug(s) do { } while (0)
38 * contextForAttrs - Client for the instruction context table. Takes a set of
39 * attributes and returns the appropriate decode context.
41 * @param attrMask - Attributes, from the enumeration attributeBits.
42 * @return - The InstructionContext to use when looking up an
43 * an instruction with these attributes.
45 static InstructionContext contextForAttrs(uint16_t attrMask) {
46 return static_cast<InstructionContext>(CONTEXTS_SYM[attrMask]);
50 * modRMRequired - Reads the appropriate instruction table to determine whether
51 * the ModR/M byte is required to decode a particular instruction.
53 * @param type - The opcode type (i.e., how many bytes it has).
54 * @param insnContext - The context for the instruction, as returned by
56 * @param opcode - The last byte of the instruction's opcode, not counting
57 * ModR/M extensions and escapes.
58 * @return - TRUE if the ModR/M byte is required, FALSE otherwise.
60 static int modRMRequired(OpcodeType type,
61 InstructionContext insnContext,
63 const struct ContextDecision* decision = 0;
67 decision = &ONEBYTE_SYM;
70 decision = &TWOBYTE_SYM;
73 decision = &THREEBYTE38_SYM;
76 decision = &THREEBYTE3A_SYM;
79 decision = &XOP8_MAP_SYM;
82 decision = &XOP9_MAP_SYM;
85 decision = &XOPA_MAP_SYM;
89 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
90 modrm_type != MODRM_ONEENTRY;
94 * decode - Reads the appropriate instruction table to obtain the unique ID of
97 * @param type - See modRMRequired().
98 * @param insnContext - See modRMRequired().
99 * @param opcode - See modRMRequired().
100 * @param modRM - The ModR/M byte if required, or any value if not.
101 * @return - The UID of the instruction, or 0 on failure.
103 static InstrUID decode(OpcodeType type,
104 InstructionContext insnContext,
107 const struct ModRMDecision* dec = 0;
111 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
114 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
117 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
120 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
123 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
126 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
129 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
133 switch (dec->modrm_type) {
135 debug("Corrupt table! Unknown modrm_type");
138 return modRMTable[dec->instructionIDs];
140 if (modFromModRM(modRM) == 0x3)
141 return modRMTable[dec->instructionIDs+1];
142 return modRMTable[dec->instructionIDs];
144 if (modFromModRM(modRM) == 0x3)
145 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
146 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
147 case MODRM_SPLITMISC:
148 if (modFromModRM(modRM) == 0x3)
149 return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
150 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
152 return modRMTable[dec->instructionIDs+modRM];
157 * specifierForUID - Given a UID, returns the name and operand specification for
160 * @param uid - The unique ID for the instruction. This should be returned by
161 * decode(); specifierForUID will not check bounds.
162 * @return - A pointer to the specification for that instruction.
164 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
165 return &INSTRUCTIONS_SYM[uid];
169 * consumeByte - Uses the reader function provided by the user to consume one
170 * byte from the instruction's memory and advance the cursor.
172 * @param insn - The instruction with the reader function to use. The cursor
173 * for this instruction is advanced.
174 * @param byte - A pointer to a pre-allocated memory buffer to be populated
175 * with the data read.
176 * @return - 0 if the read was successful; nonzero otherwise.
178 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
179 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
182 ++(insn->readerCursor);
188 * lookAtByte - Like consumeByte, but does not advance the cursor.
190 * @param insn - See consumeByte().
191 * @param byte - See consumeByte().
192 * @return - See consumeByte().
194 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
195 return insn->reader(insn->readerArg, byte, insn->readerCursor);
198 static void unconsumeByte(struct InternalInstruction* insn) {
199 insn->readerCursor--;
202 #define CONSUME_FUNC(name, type) \
203 static int name(struct InternalInstruction* insn, type* ptr) { \
206 for (offset = 0; offset < sizeof(type); ++offset) { \
208 int ret = insn->reader(insn->readerArg, \
210 insn->readerCursor + offset); \
213 combined = combined | ((uint64_t)byte << (offset * 8)); \
216 insn->readerCursor += sizeof(type); \
221 * consume* - Use the reader function provided by the user to consume data
222 * values of various sizes from the instruction's memory and advance the
223 * cursor appropriately. These readers perform endian conversion.
225 * @param insn - See consumeByte().
226 * @param ptr - A pointer to a pre-allocated memory of appropriate size to
227 * be populated with the data read.
228 * @return - See consumeByte().
230 CONSUME_FUNC(consumeInt8, int8_t)
231 CONSUME_FUNC(consumeInt16, int16_t)
232 CONSUME_FUNC(consumeInt32, int32_t)
233 CONSUME_FUNC(consumeUInt16, uint16_t)
234 CONSUME_FUNC(consumeUInt32, uint32_t)
235 CONSUME_FUNC(consumeUInt64, uint64_t)
238 * dbgprintf - Uses the logging function provided by the user to log a single
239 * message, typically without a carriage-return.
241 * @param insn - The instruction containing the logging function.
242 * @param format - See printf().
243 * @param ... - See printf().
245 static void dbgprintf(struct InternalInstruction* insn,
254 va_start(ap, format);
255 (void)vsnprintf(buffer, sizeof(buffer), format, ap);
258 insn->dlog(insn->dlogArg, buffer);
264 * setPrefixPresent - Marks that a particular prefix is present at a particular
267 * @param insn - The instruction to be marked as having the prefix.
268 * @param prefix - The prefix that is present.
269 * @param location - The location where the prefix is located (in the address
270 * space of the instruction's reader).
272 static void setPrefixPresent(struct InternalInstruction* insn,
276 insn->prefixPresent[prefix] = 1;
277 insn->prefixLocations[prefix] = location;
281 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is
282 * present at a given location.
284 * @param insn - The instruction to be queried.
285 * @param prefix - The prefix.
286 * @param location - The location to query.
287 * @return - Whether the prefix is at that location.
289 static BOOL isPrefixAtLocation(struct InternalInstruction* insn,
293 if (insn->prefixPresent[prefix] == 1 &&
294 insn->prefixLocations[prefix] == location)
301 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
302 * instruction as having them. Also sets the instruction's default operand,
303 * address, and other relevant data sizes to report operands correctly.
305 * @param insn - The instruction whose prefixes are to be read.
306 * @return - 0 if the instruction could be read until the end of the prefix
307 * bytes, and no prefixes conflicted; nonzero otherwise.
309 static int readPrefixes(struct InternalInstruction* insn) {
310 BOOL isPrefix = TRUE;
311 BOOL prefixGroups[4] = { FALSE };
312 uint64_t prefixLocation;
316 BOOL hasAdSize = FALSE;
317 BOOL hasOpSize = FALSE;
319 dbgprintf(insn, "readPrefixes()");
322 prefixLocation = insn->readerCursor;
324 /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
325 if (consumeByte(insn, &byte))
329 * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
330 * break and let it be disassembled as a normal "instruction".
332 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0)
335 if (insn->readerCursor - 1 == insn->startLocation
336 && (byte == 0xf2 || byte == 0xf3)
337 && !lookAtByte(insn, &nextByte))
340 * If the byte is 0xf2 or 0xf3, and any of the following conditions are
342 * - it is followed by a LOCK (0xf0) prefix
343 * - it is followed by an xchg instruction
344 * then it should be disassembled as a xacquire/xrelease not repne/rep.
346 if ((byte == 0xf2 || byte == 0xf3) &&
347 ((nextByte == 0xf0) |
348 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90)))
349 insn->xAcquireRelease = TRUE;
351 * Also if the byte is 0xf3, and the following condition is met:
352 * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
353 * "mov mem, imm" (opcode 0xc6/0xc7) instructions.
354 * then it should be disassembled as an xrelease not rep.
357 (nextByte == 0x88 || nextByte == 0x89 ||
358 nextByte == 0xc6 || nextByte == 0xc7))
359 insn->xAcquireRelease = TRUE;
360 if (insn->mode == MODE_64BIT && (nextByte & 0xf0) == 0x40) {
361 if (consumeByte(insn, &nextByte))
363 if (lookAtByte(insn, &nextByte))
367 if (nextByte != 0x0f && nextByte != 0x90)
372 case 0xf0: /* LOCK */
373 case 0xf2: /* REPNE/REPNZ */
374 case 0xf3: /* REP or REPE/REPZ */
376 dbgprintf(insn, "Redundant Group 1 prefix");
377 prefixGroups[0] = TRUE;
378 setPrefixPresent(insn, byte, prefixLocation);
380 case 0x2e: /* CS segment override -OR- Branch not taken */
381 case 0x36: /* SS segment override -OR- Branch taken */
382 case 0x3e: /* DS segment override */
383 case 0x26: /* ES segment override */
384 case 0x64: /* FS segment override */
385 case 0x65: /* GS segment override */
388 insn->segmentOverride = SEG_OVERRIDE_CS;
391 insn->segmentOverride = SEG_OVERRIDE_SS;
394 insn->segmentOverride = SEG_OVERRIDE_DS;
397 insn->segmentOverride = SEG_OVERRIDE_ES;
400 insn->segmentOverride = SEG_OVERRIDE_FS;
403 insn->segmentOverride = SEG_OVERRIDE_GS;
406 debug("Unhandled override");
410 dbgprintf(insn, "Redundant Group 2 prefix");
411 prefixGroups[1] = TRUE;
412 setPrefixPresent(insn, byte, prefixLocation);
414 case 0x66: /* Operand-size override */
416 dbgprintf(insn, "Redundant Group 3 prefix");
417 prefixGroups[2] = TRUE;
419 setPrefixPresent(insn, byte, prefixLocation);
421 case 0x67: /* Address-size override */
423 dbgprintf(insn, "Redundant Group 4 prefix");
424 prefixGroups[3] = TRUE;
426 setPrefixPresent(insn, byte, prefixLocation);
428 default: /* Not a prefix byte */
434 dbgprintf(insn, "Found prefix 0x%hhx", byte);
437 insn->vectorExtensionType = TYPE_NO_VEX_XOP;
440 uint8_t byte1, byte2;
442 if (consumeByte(insn, &byte1)) {
443 dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
447 if (lookAtByte(insn, &byte2)) {
448 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
452 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) &&
453 ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) {
454 insn->vectorExtensionType = TYPE_EVEX;
457 unconsumeByte(insn); /* unconsume byte1 */
458 unconsumeByte(insn); /* unconsume byte */
459 insn->necessaryPrefixLocation = insn->readerCursor - 2;
462 if (insn->vectorExtensionType == TYPE_EVEX) {
463 insn->vectorExtensionPrefix[0] = byte;
464 insn->vectorExtensionPrefix[1] = byte1;
465 if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) {
466 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
469 if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) {
470 dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
474 /* We simulate the REX prefix for simplicity's sake */
475 if (insn->mode == MODE_64BIT) {
476 insn->rexPrefix = 0x40
477 | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3)
478 | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2)
479 | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1)
480 | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
483 dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
484 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
485 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]);
488 else if (byte == 0xc4) {
491 if (lookAtByte(insn, &byte1)) {
492 dbgprintf(insn, "Couldn't read second byte of VEX");
496 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
497 insn->vectorExtensionType = TYPE_VEX_3B;
498 insn->necessaryPrefixLocation = insn->readerCursor - 1;
502 insn->necessaryPrefixLocation = insn->readerCursor - 1;
505 if (insn->vectorExtensionType == TYPE_VEX_3B) {
506 insn->vectorExtensionPrefix[0] = byte;
507 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
508 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
510 /* We simulate the REX prefix for simplicity's sake */
512 if (insn->mode == MODE_64BIT) {
513 insn->rexPrefix = 0x40
514 | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3)
515 | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2)
516 | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1)
517 | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
520 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
521 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
522 insn->vectorExtensionPrefix[2]);
525 else if (byte == 0xc5) {
528 if (lookAtByte(insn, &byte1)) {
529 dbgprintf(insn, "Couldn't read second byte of VEX");
533 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
534 insn->vectorExtensionType = TYPE_VEX_2B;
540 if (insn->vectorExtensionType == TYPE_VEX_2B) {
541 insn->vectorExtensionPrefix[0] = byte;
542 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
544 if (insn->mode == MODE_64BIT) {
545 insn->rexPrefix = 0x40
546 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
549 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1]))
558 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx",
559 insn->vectorExtensionPrefix[0],
560 insn->vectorExtensionPrefix[1]);
563 else if (byte == 0x8f) {
566 if (lookAtByte(insn, &byte1)) {
567 dbgprintf(insn, "Couldn't read second byte of XOP");
571 if ((byte1 & 0x38) != 0x0) { /* 0 in these 3 bits is a POP instruction. */
572 insn->vectorExtensionType = TYPE_XOP;
573 insn->necessaryPrefixLocation = insn->readerCursor - 1;
577 insn->necessaryPrefixLocation = insn->readerCursor - 1;
580 if (insn->vectorExtensionType == TYPE_XOP) {
581 insn->vectorExtensionPrefix[0] = byte;
582 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
583 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
585 /* We simulate the REX prefix for simplicity's sake */
587 if (insn->mode == MODE_64BIT) {
588 insn->rexPrefix = 0x40
589 | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3)
590 | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2)
591 | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1)
592 | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
595 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2]))
604 dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
605 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
606 insn->vectorExtensionPrefix[2]);
610 if (insn->mode == MODE_64BIT) {
611 if ((byte & 0xf0) == 0x40) {
614 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
615 dbgprintf(insn, "Redundant REX prefix");
619 insn->rexPrefix = byte;
620 insn->necessaryPrefixLocation = insn->readerCursor - 2;
622 dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
625 insn->necessaryPrefixLocation = insn->readerCursor - 1;
629 insn->necessaryPrefixLocation = insn->readerCursor - 1;
633 if (insn->mode == MODE_16BIT) {
634 insn->registerSize = (hasOpSize ? 4 : 2);
635 insn->addressSize = (hasAdSize ? 4 : 2);
636 insn->displacementSize = (hasAdSize ? 4 : 2);
637 insn->immediateSize = (hasOpSize ? 4 : 2);
638 } else if (insn->mode == MODE_32BIT) {
639 insn->registerSize = (hasOpSize ? 2 : 4);
640 insn->addressSize = (hasAdSize ? 2 : 4);
641 insn->displacementSize = (hasAdSize ? 2 : 4);
642 insn->immediateSize = (hasOpSize ? 2 : 4);
643 } else if (insn->mode == MODE_64BIT) {
644 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
645 insn->registerSize = 8;
646 insn->addressSize = (hasAdSize ? 4 : 8);
647 insn->displacementSize = 4;
648 insn->immediateSize = 4;
649 } else if (insn->rexPrefix) {
650 insn->registerSize = (hasOpSize ? 2 : 4);
651 insn->addressSize = (hasAdSize ? 4 : 8);
652 insn->displacementSize = (hasOpSize ? 2 : 4);
653 insn->immediateSize = (hasOpSize ? 2 : 4);
655 insn->registerSize = (hasOpSize ? 2 : 4);
656 insn->addressSize = (hasAdSize ? 4 : 8);
657 insn->displacementSize = (hasOpSize ? 2 : 4);
658 insn->immediateSize = (hasOpSize ? 2 : 4);
666 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
667 * extended or escape opcodes).
669 * @param insn - The instruction whose opcode is to be read.
670 * @return - 0 if the opcode could be read successfully; nonzero otherwise.
672 static int readOpcode(struct InternalInstruction* insn) {
673 /* Determine the length of the primary opcode */
677 dbgprintf(insn, "readOpcode()");
679 insn->opcodeType = ONEBYTE;
681 if (insn->vectorExtensionType == TYPE_EVEX)
683 switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
685 dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)",
686 mmFromEVEX2of4(insn->vectorExtensionPrefix[1]));
689 insn->opcodeType = TWOBYTE;
690 return consumeByte(insn, &insn->opcode);
692 insn->opcodeType = THREEBYTE_38;
693 return consumeByte(insn, &insn->opcode);
695 insn->opcodeType = THREEBYTE_3A;
696 return consumeByte(insn, &insn->opcode);
699 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
700 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
702 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
703 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
706 insn->opcodeType = TWOBYTE;
707 return consumeByte(insn, &insn->opcode);
709 insn->opcodeType = THREEBYTE_38;
710 return consumeByte(insn, &insn->opcode);
712 insn->opcodeType = THREEBYTE_3A;
713 return consumeByte(insn, &insn->opcode);
716 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
717 insn->opcodeType = TWOBYTE;
718 return consumeByte(insn, &insn->opcode);
720 else if (insn->vectorExtensionType == TYPE_XOP) {
721 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
723 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
724 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
726 case XOP_MAP_SELECT_8:
727 insn->opcodeType = XOP8_MAP;
728 return consumeByte(insn, &insn->opcode);
729 case XOP_MAP_SELECT_9:
730 insn->opcodeType = XOP9_MAP;
731 return consumeByte(insn, &insn->opcode);
732 case XOP_MAP_SELECT_A:
733 insn->opcodeType = XOPA_MAP;
734 return consumeByte(insn, &insn->opcode);
738 if (consumeByte(insn, ¤t))
741 if (current == 0x0f) {
742 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
744 if (consumeByte(insn, ¤t))
747 if (current == 0x38) {
748 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
750 if (consumeByte(insn, ¤t))
753 insn->opcodeType = THREEBYTE_38;
754 } else if (current == 0x3a) {
755 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
757 if (consumeByte(insn, ¤t))
760 insn->opcodeType = THREEBYTE_3A;
762 dbgprintf(insn, "Didn't find a three-byte escape prefix");
764 insn->opcodeType = TWOBYTE;
769 * At this point we have consumed the full opcode.
770 * Anything we consume from here on must be unconsumed.
773 insn->opcode = current;
778 static int readModRM(struct InternalInstruction* insn);
781 * getIDWithAttrMask - Determines the ID of an instruction, consuming
782 * the ModR/M byte as appropriate for extended and escape opcodes,
783 * and using a supplied attribute mask.
785 * @param instructionID - A pointer whose target is filled in with the ID of the
787 * @param insn - The instruction whose ID is to be determined.
788 * @param attrMask - The attribute mask to search.
789 * @return - 0 if the ModR/M could be read when needed or was not
790 * needed; nonzero otherwise.
792 static int getIDWithAttrMask(uint16_t* instructionID,
793 struct InternalInstruction* insn,
795 BOOL hasModRMExtension;
797 InstructionContext instructionClass = contextForAttrs(attrMask);
799 hasModRMExtension = modRMRequired(insn->opcodeType,
803 if (hasModRMExtension) {
807 *instructionID = decode(insn->opcodeType,
812 *instructionID = decode(insn->opcodeType,
822 * is16BitEquivalent - Determines whether two instruction names refer to
823 * equivalent instructions but one is 16-bit whereas the other is not.
825 * @param orig - The instruction that is not 16-bit
826 * @param equiv - The instruction that is 16-bit
828 static BOOL is16BitEquivalent(const char* orig, const char* equiv) {
832 if (orig[i] == '\0' && equiv[i] == '\0')
834 if (orig[i] == '\0' || equiv[i] == '\0')
836 if (orig[i] != equiv[i]) {
837 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
839 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
841 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
849 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
850 * appropriate for extended and escape opcodes. Determines the attributes and
851 * context for the instruction before doing so.
853 * @param insn - The instruction whose ID is to be determined.
854 * @return - 0 if the ModR/M could be read when needed or was not needed;
857 static int getID(struct InternalInstruction* insn, const void *miiArg) {
859 uint16_t instructionID;
861 dbgprintf(insn, "getID()");
863 attrMask = ATTR_NONE;
865 if (insn->mode == MODE_64BIT)
866 attrMask |= ATTR_64BIT;
868 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
869 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
871 if (insn->vectorExtensionType == TYPE_EVEX) {
872 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
874 attrMask |= ATTR_OPSIZE;
884 if (zFromEVEX4of4(insn->vectorExtensionPrefix[3]))
885 attrMask |= ATTR_EVEXKZ;
886 if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
887 attrMask |= ATTR_EVEXB;
888 if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
889 attrMask |= ATTR_EVEXK;
890 if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
891 attrMask |= ATTR_EVEXL;
892 if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
893 attrMask |= ATTR_EVEXL2;
895 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
896 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
898 attrMask |= ATTR_OPSIZE;
908 if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
909 attrMask |= ATTR_VEXL;
911 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
912 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
914 attrMask |= ATTR_OPSIZE;
924 if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
925 attrMask |= ATTR_VEXL;
927 else if (insn->vectorExtensionType == TYPE_XOP) {
928 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
930 attrMask |= ATTR_OPSIZE;
940 if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
941 attrMask |= ATTR_VEXL;
948 if (insn->mode != MODE_16BIT && isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation))
949 attrMask |= ATTR_OPSIZE;
950 else if (isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation))
951 attrMask |= ATTR_ADSIZE;
952 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation))
954 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
958 if (insn->rexPrefix & 0x08)
959 attrMask |= ATTR_REXW;
961 if (getIDWithAttrMask(&instructionID, insn, attrMask))
965 * JCXZ/JECXZ need special handling for 16-bit mode because the meaning
966 * of the AdSize prefix is inverted w.r.t. 32-bit mode.
968 if (insn->mode == MODE_16BIT && insn->opcode == 0xE3) {
969 const struct InstructionSpecifier *spec;
970 spec = specifierForUID(instructionID);
973 * Check for Ii8PCRel instructions. We could alternatively do a
974 * string-compare on the names, but this is probably cheaper.
976 if (x86OperandSets[spec->operands][0].type == TYPE_REL8) {
977 attrMask ^= ATTR_ADSIZE;
978 if (getIDWithAttrMask(&instructionID, insn, attrMask))
983 /* The following clauses compensate for limitations of the tables. */
985 if ((insn->mode == MODE_16BIT || insn->prefixPresent[0x66]) &&
986 !(attrMask & ATTR_OPSIZE)) {
988 * The instruction tables make no distinction between instructions that
989 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
990 * particular spot (i.e., many MMX operations). In general we're
991 * conservative, but in the specific case where OpSize is present but not
992 * in the right place we check if there's a 16-bit operation.
995 const struct InstructionSpecifier *spec;
996 uint16_t instructionIDWithOpsize;
997 const char *specName, *specWithOpSizeName;
999 spec = specifierForUID(instructionID);
1001 if (getIDWithAttrMask(&instructionIDWithOpsize,
1003 attrMask | ATTR_OPSIZE)) {
1005 * ModRM required with OpSize but not present; give up and return version
1006 * without OpSize set
1009 insn->instructionID = instructionID;
1014 specName = GetInstrName(instructionID, miiArg);
1015 specWithOpSizeName = GetInstrName(instructionIDWithOpsize, miiArg);
1017 if (is16BitEquivalent(specName, specWithOpSizeName) &&
1018 (insn->mode == MODE_16BIT) ^ insn->prefixPresent[0x66]) {
1019 insn->instructionID = instructionIDWithOpsize;
1020 insn->spec = specifierForUID(instructionIDWithOpsize);
1022 insn->instructionID = instructionID;
1028 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1029 insn->rexPrefix & 0x01) {
1031 * NOOP shouldn't decode as NOOP if REX.b is set. Instead
1032 * it should decode as XCHG %r8, %eax.
1035 const struct InstructionSpecifier *spec;
1036 uint16_t instructionIDWithNewOpcode;
1037 const struct InstructionSpecifier *specWithNewOpcode;
1039 spec = specifierForUID(instructionID);
1041 /* Borrow opcode from one of the other XCHGar opcodes */
1042 insn->opcode = 0x91;
1044 if (getIDWithAttrMask(&instructionIDWithNewOpcode,
1047 insn->opcode = 0x90;
1049 insn->instructionID = instructionID;
1054 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
1057 insn->opcode = 0x90;
1059 insn->instructionID = instructionIDWithNewOpcode;
1060 insn->spec = specWithNewOpcode;
1065 insn->instructionID = instructionID;
1066 insn->spec = specifierForUID(insn->instructionID);
1072 * readSIB - Consumes the SIB byte to determine addressing information for an
1075 * @param insn - The instruction whose SIB byte is to be read.
1076 * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
1078 static int readSIB(struct InternalInstruction* insn) {
1079 SIBIndex sibIndexBase = SIB_INDEX_NONE;
1080 SIBBase sibBaseBase = SIB_BASE_NONE;
1081 uint8_t index, base;
1083 dbgprintf(insn, "readSIB()");
1085 if (insn->consumedSIB)
1088 insn->consumedSIB = TRUE;
1090 switch (insn->addressSize) {
1092 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
1095 sibIndexBase = SIB_INDEX_EAX;
1096 sibBaseBase = SIB_BASE_EAX;
1099 sibIndexBase = SIB_INDEX_RAX;
1100 sibBaseBase = SIB_BASE_RAX;
1104 if (consumeByte(insn, &insn->sib))
1107 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
1108 if (insn->vectorExtensionType == TYPE_EVEX)
1109 index |= v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4;
1113 insn->sibIndex = SIB_INDEX_NONE;
1116 insn->sibIndex = (SIBIndex)(sibIndexBase + index);
1117 if (insn->sibIndex == SIB_INDEX_sib ||
1118 insn->sibIndex == SIB_INDEX_sib64)
1119 insn->sibIndex = SIB_INDEX_NONE;
1123 switch (scaleFromSIB(insn->sib)) {
1138 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1143 switch (modFromModRM(insn->modRM)) {
1145 insn->eaDisplacement = EA_DISP_32;
1146 insn->sibBase = SIB_BASE_NONE;
1149 insn->eaDisplacement = EA_DISP_8;
1150 insn->sibBase = (SIBBase)(sibBaseBase + base);
1153 insn->eaDisplacement = EA_DISP_32;
1154 insn->sibBase = (SIBBase)(sibBaseBase + base);
1157 debug("Cannot have Mod = 0b11 and a SIB byte");
1162 insn->sibBase = (SIBBase)(sibBaseBase + base);
1170 * readDisplacement - Consumes the displacement of an instruction.
1172 * @param insn - The instruction whose displacement is to be read.
1173 * @return - 0 if the displacement byte was successfully read; nonzero
1176 static int readDisplacement(struct InternalInstruction* insn) {
1181 dbgprintf(insn, "readDisplacement()");
1183 if (insn->consumedDisplacement)
1186 insn->consumedDisplacement = TRUE;
1187 insn->displacementOffset = insn->readerCursor - insn->startLocation;
1189 switch (insn->eaDisplacement) {
1191 insn->consumedDisplacement = FALSE;
1194 if (consumeInt8(insn, &d8))
1196 insn->displacement = d8;
1199 if (consumeInt16(insn, &d16))
1201 insn->displacement = d16;
1204 if (consumeInt32(insn, &d32))
1206 insn->displacement = d32;
1210 insn->consumedDisplacement = TRUE;
1215 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1216 * displacement) for an instruction and interprets it.
1218 * @param insn - The instruction whose addressing information is to be read.
1219 * @return - 0 if the information was successfully read; nonzero otherwise.
1221 static int readModRM(struct InternalInstruction* insn) {
1222 uint8_t mod, rm, reg;
1224 dbgprintf(insn, "readModRM()");
1226 if (insn->consumedModRM)
1229 if (consumeByte(insn, &insn->modRM))
1231 insn->consumedModRM = TRUE;
1233 mod = modFromModRM(insn->modRM);
1234 rm = rmFromModRM(insn->modRM);
1235 reg = regFromModRM(insn->modRM);
1238 * This goes by insn->registerSize to pick the correct register, which messes
1239 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1242 switch (insn->registerSize) {
1244 insn->regBase = MODRM_REG_AX;
1245 insn->eaRegBase = EA_REG_AX;
1248 insn->regBase = MODRM_REG_EAX;
1249 insn->eaRegBase = EA_REG_EAX;
1252 insn->regBase = MODRM_REG_RAX;
1253 insn->eaRegBase = EA_REG_RAX;
1257 reg |= rFromREX(insn->rexPrefix) << 3;
1258 rm |= bFromREX(insn->rexPrefix) << 3;
1259 if (insn->vectorExtensionType == TYPE_EVEX) {
1260 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1261 rm |= xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1264 insn->reg = (Reg)(insn->regBase + reg);
1266 switch (insn->addressSize) {
1268 insn->eaBaseBase = EA_BASE_BX_SI;
1273 insn->eaBase = EA_BASE_NONE;
1274 insn->eaDisplacement = EA_DISP_16;
1275 if (readDisplacement(insn))
1278 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1279 insn->eaDisplacement = EA_DISP_NONE;
1283 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1284 insn->eaDisplacement = EA_DISP_8;
1285 insn->displacementSize = 1;
1286 if (readDisplacement(insn))
1290 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1291 insn->eaDisplacement = EA_DISP_16;
1292 if (readDisplacement(insn))
1296 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1297 if (readDisplacement(insn))
1304 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1308 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1312 case 0xc: /* in case REXW.b is set */
1313 insn->eaBase = (insn->addressSize == 4 ?
1314 EA_BASE_sib : EA_BASE_sib64);
1315 if (readSIB(insn) || readDisplacement(insn))
1319 insn->eaBase = EA_BASE_NONE;
1320 insn->eaDisplacement = EA_DISP_32;
1321 if (readDisplacement(insn))
1325 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1330 insn->displacementSize = 1;
1333 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1337 case 0xc: /* in case REXW.b is set */
1338 insn->eaBase = EA_BASE_sib;
1339 if (readSIB(insn) || readDisplacement(insn))
1343 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1344 if (readDisplacement(insn))
1350 insn->eaDisplacement = EA_DISP_NONE;
1351 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1355 } /* switch (insn->addressSize) */
1360 #define GENERIC_FIXUP_FUNC(name, base, prefix) \
1361 static uint8_t name(struct InternalInstruction *insn, \
1368 debug("Unhandled register type"); \
1372 return base + index; \
1374 if (insn->rexPrefix && \
1375 index >= 4 && index <= 7) { \
1376 return prefix##_SPL + (index - 4); \
1378 return prefix##_AL + index; \
1381 return prefix##_AX + index; \
1383 return prefix##_EAX + index; \
1385 return prefix##_RAX + index; \
1387 return prefix##_ZMM0 + index; \
1389 return prefix##_YMM0 + index; \
1394 return prefix##_XMM0 + index; \
1398 return prefix##_K0 + index; \
1404 return prefix##_MM0 + index; \
1405 case TYPE_SEGMENTREG: \
1408 return prefix##_ES + index; \
1409 case TYPE_DEBUGREG: \
1412 return prefix##_DR0 + index; \
1413 case TYPE_CONTROLREG: \
1416 return prefix##_CR0 + index; \
1421 * fixup*Value - Consults an operand type to determine the meaning of the
1422 * reg or R/M field. If the operand is an XMM operand, for example, an
1423 * operand would be XMM0 instead of AX, which readModRM() would otherwise
1424 * misinterpret it as.
1426 * @param insn - The instruction containing the operand.
1427 * @param type - The operand type.
1428 * @param index - The existing value of the field as reported by readModRM().
1429 * @param valid - The address of a uint8_t. The target is set to 1 if the
1430 * field is valid for the register class; 0 if not.
1431 * @return - The proper value.
1433 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
1434 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
1437 * fixupReg - Consults an operand specifier to determine which of the
1438 * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1440 * @param insn - See fixup*Value().
1441 * @param op - The operand specifier.
1442 * @return - 0 if fixup was successful; -1 if the register returned was
1443 * invalid for its class.
1445 static int fixupReg(struct InternalInstruction *insn,
1446 const struct OperandSpecifier *op) {
1449 dbgprintf(insn, "fixupReg()");
1451 switch ((OperandEncoding)op->encoding) {
1453 debug("Expected a REG or R/M encoding in fixupReg");
1456 insn->vvvv = (Reg)fixupRegValue(insn,
1457 (OperandType)op->type,
1464 insn->reg = (Reg)fixupRegValue(insn,
1465 (OperandType)op->type,
1466 insn->reg - insn->regBase,
1472 if (insn->eaBase >= insn->eaRegBase) {
1473 insn->eaBase = (EABase)fixupRMValue(insn,
1474 (OperandType)op->type,
1475 insn->eaBase - insn->eaRegBase,
1487 * readOpcodeRegister - Reads an operand from the opcode field of an
1488 * instruction and interprets it appropriately given the operand width.
1489 * Handles AddRegFrm instructions.
1491 * @param insn - the instruction whose opcode field is to be read.
1492 * @param size - The width (in bytes) of the register being specified.
1493 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1495 * @return - 0 on success; nonzero otherwise.
1497 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1498 dbgprintf(insn, "readOpcodeRegister()");
1501 size = insn->registerSize;
1505 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1506 | (insn->opcode & 7)));
1507 if (insn->rexPrefix &&
1508 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1509 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1510 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1511 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1516 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1517 + ((bFromREX(insn->rexPrefix) << 3)
1518 | (insn->opcode & 7)));
1521 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1522 + ((bFromREX(insn->rexPrefix) << 3)
1523 | (insn->opcode & 7)));
1526 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1527 + ((bFromREX(insn->rexPrefix) << 3)
1528 | (insn->opcode & 7)));
1536 * readImmediate - Consumes an immediate operand from an instruction, given the
1537 * desired operand size.
1539 * @param insn - The instruction whose operand is to be read.
1540 * @param size - The width (in bytes) of the operand.
1541 * @return - 0 if the immediate was successfully consumed; nonzero
1544 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1550 dbgprintf(insn, "readImmediate()");
1552 if (insn->numImmediatesConsumed == 2) {
1553 debug("Already consumed two immediates");
1558 size = insn->immediateSize;
1560 insn->immediateSize = size;
1561 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1565 if (consumeByte(insn, &imm8))
1567 insn->immediates[insn->numImmediatesConsumed] = imm8;
1570 if (consumeUInt16(insn, &imm16))
1572 insn->immediates[insn->numImmediatesConsumed] = imm16;
1575 if (consumeUInt32(insn, &imm32))
1577 insn->immediates[insn->numImmediatesConsumed] = imm32;
1580 if (consumeUInt64(insn, &imm64))
1582 insn->immediates[insn->numImmediatesConsumed] = imm64;
1586 insn->numImmediatesConsumed++;
1592 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1594 * @param insn - The instruction whose operand is to be read.
1595 * @return - 0 if the vvvv was successfully consumed; nonzero
1598 static int readVVVV(struct InternalInstruction* insn) {
1599 dbgprintf(insn, "readVVVV()");
1602 if (insn->vectorExtensionType == TYPE_EVEX)
1603 vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]);
1604 else if (insn->vectorExtensionType == TYPE_VEX_3B)
1605 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1606 else if (insn->vectorExtensionType == TYPE_VEX_2B)
1607 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1608 else if (insn->vectorExtensionType == TYPE_XOP)
1609 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1613 if (insn->mode != MODE_64BIT)
1616 insn->vvvv = static_cast<Reg>(vvvv);
1621 * readMaskRegister - Reads an mask register from the opcode field of an
1624 * @param insn - The instruction whose opcode field is to be read.
1625 * @return - 0 on success; nonzero otherwise.
1627 static int readMaskRegister(struct InternalInstruction* insn) {
1628 dbgprintf(insn, "readMaskRegister()");
1630 if (insn->vectorExtensionType != TYPE_EVEX)
1634 static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
1639 * readOperands - Consults the specifier for an instruction and consumes all
1640 * operands for that instruction, interpreting them as it goes.
1642 * @param insn - The instruction whose operands are to be read and interpreted.
1643 * @return - 0 if all operands could be read; nonzero otherwise.
1645 static int readOperands(struct InternalInstruction* insn) {
1647 int hasVVVV, needVVVV;
1650 dbgprintf(insn, "readOperands()");
1652 /* If non-zero vvvv specified, need to make sure one of the operands
1654 hasVVVV = !readVVVV(insn);
1655 needVVVV = hasVVVV && (insn->vvvv != 0);
1657 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
1658 switch (x86OperandSets[insn->spec->operands][index].encoding) {
1665 if (readModRM(insn))
1667 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1676 dbgprintf(insn, "We currently don't hande code-offset encodings");
1680 /* Saw a register immediate so don't read again and instead split the
1681 previous immediate. FIXME: This is a hack. */
1682 insn->immediates[insn->numImmediatesConsumed] =
1683 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1684 ++insn->numImmediatesConsumed;
1687 if (readImmediate(insn, 1))
1689 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
1690 insn->immediates[insn->numImmediatesConsumed - 1] > 7)
1692 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 &&
1693 insn->immediates[insn->numImmediatesConsumed - 1] > 31)
1695 if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 ||
1696 x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256)
1700 if (readImmediate(insn, 2))
1704 if (readImmediate(insn, 4))
1708 if (readImmediate(insn, 8))
1712 if (readImmediate(insn, insn->immediateSize))
1716 if (readImmediate(insn, insn->addressSize))
1720 if (readOpcodeRegister(insn, 1))
1724 if (readOpcodeRegister(insn, 2))
1728 if (readOpcodeRegister(insn, 4))
1732 if (readOpcodeRegister(insn, 8))
1736 if (readOpcodeRegister(insn, 0))
1742 needVVVV = 0; /* Mark that we have found a VVVV operand. */
1745 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1748 case ENCODING_WRITEMASK:
1749 if (readMaskRegister(insn))
1755 dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1760 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1761 if (needVVVV) return -1;
1767 * decodeInstruction - Reads and interprets a full instruction provided by the
1770 * @param insn - A pointer to the instruction to be populated. Must be
1772 * @param reader - The function to be used to read the instruction's bytes.
1773 * @param readerArg - A generic argument to be passed to the reader to store
1774 * any internal state.
1775 * @param logger - If non-NULL, the function to be used to write log messages
1777 * @param loggerArg - A generic argument to be passed to the logger to store
1778 * any internal state.
1779 * @param startLoc - The address (in the reader's address space) of the first
1780 * byte in the instruction.
1781 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1782 * decode the instruction in.
1783 * @return - 0 if the instruction's memory could be read; nonzero if
1786 int llvm::X86Disassembler::decodeInstruction(
1787 struct InternalInstruction *insn, byteReader_t reader,
1788 const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg,
1789 uint64_t startLoc, DisassemblerMode mode) {
1790 memset(insn, 0, sizeof(struct InternalInstruction));
1792 insn->reader = reader;
1793 insn->readerArg = readerArg;
1794 insn->dlog = logger;
1795 insn->dlogArg = loggerArg;
1796 insn->startLocation = startLoc;
1797 insn->readerCursor = startLoc;
1799 insn->numImmediatesConsumed = 0;
1801 if (readPrefixes(insn) ||
1803 getID(insn, miiArg) ||
1804 insn->instructionID == 0 ||
1808 insn->operands = &x86OperandSets[insn->spec->operands][0];
1810 insn->length = insn->readerCursor - insn->startLocation;
1812 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1813 startLoc, insn->readerCursor, insn->length);
1815 if (insn->length > 15)
1816 dbgprintf(insn, "Instruction exceeds 15-byte limit");