1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "llvm/ADT/APFloat.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallString.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/ADT/Twine.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MCTargetAsmParser.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
37 static const char OpPrecedence[] = {
48 class X86AsmParser : public MCTargetAsmParser {
51 ParseInstructionInfo *InstInfo;
53 SMLoc consumeToken() {
54 SMLoc Result = Parser.getTok().getLoc();
59 enum InfixCalculatorTok {
70 class InfixCalculator {
71 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
72 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
73 SmallVector<ICToken, 4> PostfixStack;
76 int64_t popOperand() {
77 assert (!PostfixStack.empty() && "Poped an empty stack!");
78 ICToken Op = PostfixStack.pop_back_val();
79 assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
80 && "Expected and immediate or register!");
83 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
84 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
85 "Unexpected operand!");
86 PostfixStack.push_back(std::make_pair(Op, Val));
89 void popOperator() { InfixOperatorStack.pop_back(); }
90 void pushOperator(InfixCalculatorTok Op) {
91 // Push the new operator if the stack is empty.
92 if (InfixOperatorStack.empty()) {
93 InfixOperatorStack.push_back(Op);
97 // Push the new operator if it has a higher precedence than the operator
98 // on the top of the stack or the operator on the top of the stack is a
100 unsigned Idx = InfixOperatorStack.size() - 1;
101 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
102 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
103 InfixOperatorStack.push_back(Op);
107 // The operator on the top of the stack has higher precedence than the
109 unsigned ParenCount = 0;
111 // Nothing to process.
112 if (InfixOperatorStack.empty())
115 Idx = InfixOperatorStack.size() - 1;
116 StackOp = InfixOperatorStack[Idx];
117 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
120 // If we have an even parentheses count and we see a left parentheses,
121 // then stop processing.
122 if (!ParenCount && StackOp == IC_LPAREN)
125 if (StackOp == IC_RPAREN) {
127 InfixOperatorStack.pop_back();
128 } else if (StackOp == IC_LPAREN) {
130 InfixOperatorStack.pop_back();
132 InfixOperatorStack.pop_back();
133 PostfixStack.push_back(std::make_pair(StackOp, 0));
136 // Push the new operator.
137 InfixOperatorStack.push_back(Op);
140 // Push any remaining operators onto the postfix stack.
141 while (!InfixOperatorStack.empty()) {
142 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
143 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
144 PostfixStack.push_back(std::make_pair(StackOp, 0));
147 if (PostfixStack.empty())
150 SmallVector<ICToken, 16> OperandStack;
151 for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
152 ICToken Op = PostfixStack[i];
153 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
154 OperandStack.push_back(Op);
156 assert (OperandStack.size() > 1 && "Too few operands.");
158 ICToken Op2 = OperandStack.pop_back_val();
159 ICToken Op1 = OperandStack.pop_back_val();
162 report_fatal_error("Unexpected operator!");
165 Val = Op1.second + Op2.second;
166 OperandStack.push_back(std::make_pair(IC_IMM, Val));
169 Val = Op1.second - Op2.second;
170 OperandStack.push_back(std::make_pair(IC_IMM, Val));
173 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
174 "Multiply operation with an immediate and a register!");
175 Val = Op1.second * Op2.second;
176 OperandStack.push_back(std::make_pair(IC_IMM, Val));
179 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
180 "Divide operation with an immediate and a register!");
181 assert (Op2.second != 0 && "Division by zero!");
182 Val = Op1.second / Op2.second;
183 OperandStack.push_back(std::make_pair(IC_IMM, Val));
188 assert (OperandStack.size() == 1 && "Expected a single result.");
189 return OperandStack.pop_back_val().second;
193 enum IntelExprState {
208 class IntelExprStateMachine {
209 IntelExprState State, PrevState;
210 unsigned BaseReg, IndexReg, TmpReg, Scale;
214 bool StopOnLBrac, AddImmPrefix;
216 InlineAsmIdentifierInfo Info;
218 IntelExprStateMachine(int64_t imm, bool stoponlbrac, bool addimmprefix) :
219 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
220 Scale(1), Imm(imm), Sym(0), StopOnLBrac(stoponlbrac),
221 AddImmPrefix(addimmprefix) { Info.clear(); }
223 unsigned getBaseReg() { return BaseReg; }
224 unsigned getIndexReg() { return IndexReg; }
225 unsigned getScale() { return Scale; }
226 const MCExpr *getSym() { return Sym; }
227 StringRef getSymName() { return SymName; }
228 int64_t getImm() { return Imm + IC.execute(); }
229 bool isValidEndState() {
230 return State == IES_RBRAC || State == IES_INTEGER;
232 bool getStopOnLBrac() { return StopOnLBrac; }
233 bool getAddImmPrefix() { return AddImmPrefix; }
234 bool hadError() { return State == IES_ERROR; }
236 InlineAsmIdentifierInfo &getIdentifierInfo() {
241 IntelExprState CurrState = State;
250 IC.pushOperator(IC_PLUS);
251 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
252 // If we already have a BaseReg, then assume this is the IndexReg with
257 assert (!IndexReg && "BaseReg/IndexReg already set!");
264 PrevState = CurrState;
267 IntelExprState CurrState = State;
282 // Only push the minus operator if it is not a unary operator.
283 if (!(CurrState == IES_PLUS || CurrState == IES_MINUS ||
284 CurrState == IES_MULTIPLY || CurrState == IES_DIVIDE ||
285 CurrState == IES_LPAREN || CurrState == IES_LBRAC))
286 IC.pushOperator(IC_MINUS);
287 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
288 // If we already have a BaseReg, then assume this is the IndexReg with
293 assert (!IndexReg && "BaseReg/IndexReg already set!");
300 PrevState = CurrState;
302 void onRegister(unsigned Reg) {
303 IntelExprState CurrState = State;
310 State = IES_REGISTER;
312 IC.pushOperand(IC_REGISTER);
315 // Index Register - Scale * Register
316 if (PrevState == IES_INTEGER) {
317 assert (!IndexReg && "IndexReg already set!");
318 State = IES_REGISTER;
320 // Get the scale and replace the 'Scale * Register' with '0'.
321 Scale = IC.popOperand();
322 IC.pushOperand(IC_IMM);
329 PrevState = CurrState;
331 void onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName) {
341 SymName = SymRefName;
342 IC.pushOperand(IC_IMM);
346 void onInteger(int64_t TmpInt) {
347 IntelExprState CurrState = State;
358 if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
359 // Index Register - Register * Scale
360 assert (!IndexReg && "IndexReg already set!");
363 // Get the scale and replace the 'Register * Scale' with '0'.
365 } else if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
366 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
367 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
368 CurrState == IES_MINUS) {
369 // Unary minus. No need to pop the minus operand because it was never
371 IC.pushOperand(IC_IMM, -TmpInt); // Push -Imm.
373 IC.pushOperand(IC_IMM, TmpInt);
377 PrevState = CurrState;
388 State = IES_MULTIPLY;
389 IC.pushOperator(IC_MULTIPLY);
402 IC.pushOperator(IC_DIVIDE);
414 IC.pushOperator(IC_PLUS);
419 IntelExprState CurrState = State;
428 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
429 // If we already have a BaseReg, then assume this is the IndexReg with
434 assert (!IndexReg && "BaseReg/IndexReg already set!");
441 PrevState = CurrState;
444 IntelExprState CurrState = State;
454 // FIXME: We don't handle this type of unary minus, yet.
455 if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
456 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
457 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
458 CurrState == IES_MINUS) {
463 IC.pushOperator(IC_LPAREN);
466 PrevState = CurrState;
478 IC.pushOperator(IC_RPAREN);
484 MCAsmParser &getParser() const { return Parser; }
486 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
488 bool Error(SMLoc L, const Twine &Msg,
489 ArrayRef<SMRange> Ranges = None,
490 bool MatchingInlineAsm = false) {
491 if (MatchingInlineAsm) return true;
492 return Parser.Error(L, Msg, Ranges);
495 X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
500 X86Operand *ParseOperand();
501 X86Operand *ParseATTOperand();
502 X86Operand *ParseIntelOperand();
503 X86Operand *ParseIntelOffsetOfOperator();
504 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp);
505 X86Operand *ParseIntelOperator(unsigned OpKind);
506 X86Operand *ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
507 X86Operand *ParseIntelMemOperand(int64_t ImmDisp, SMLoc StartLoc,
509 bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
510 X86Operand *ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
511 int64_t ImmDisp, unsigned Size);
512 bool ParseIntelIdentifier(const MCExpr *&Val, StringRef &Identifier,
513 InlineAsmIdentifierInfo &Info,
514 bool IsUnevaluatedOperand, SMLoc &End);
516 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
518 X86Operand *CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
519 unsigned BaseReg, unsigned IndexReg,
520 unsigned Scale, SMLoc Start, SMLoc End,
521 unsigned Size, StringRef Identifier,
522 InlineAsmIdentifierInfo &Info);
524 bool ParseDirectiveWord(unsigned Size, SMLoc L);
525 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
527 bool processInstruction(MCInst &Inst,
528 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
530 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
531 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
532 MCStreamer &Out, unsigned &ErrorInfo,
533 bool MatchingInlineAsm);
535 /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
536 /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
537 bool isSrcOp(X86Operand &Op);
539 /// isDstOp - Returns true if operand is either (%rdi) or %es:(%rdi)
540 /// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
541 bool isDstOp(X86Operand &Op);
543 bool is64BitMode() const {
544 // FIXME: Can tablegen auto-generate this?
545 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
548 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
549 setAvailableFeatures(FB);
552 bool isParsingIntelSyntax() {
553 return getParser().getAssemblerDialect();
556 /// @name Auto-generated Matcher Functions
559 #define GET_ASSEMBLER_HEADER
560 #include "X86GenAsmMatcher.inc"
565 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
566 const MCInstrInfo &MII)
567 : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
569 // Initialize the set of available features.
570 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
572 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
574 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
576 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
578 virtual bool ParseDirective(AsmToken DirectiveID);
580 } // end anonymous namespace
582 /// @name Auto-generated Match Functions
585 static unsigned MatchRegisterName(StringRef Name);
589 static bool isImmSExti16i8Value(uint64_t Value) {
590 return (( Value <= 0x000000000000007FULL)||
591 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
592 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
595 static bool isImmSExti32i8Value(uint64_t Value) {
596 return (( Value <= 0x000000000000007FULL)||
597 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
598 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
601 static bool isImmZExtu32u8Value(uint64_t Value) {
602 return (Value <= 0x00000000000000FFULL);
605 static bool isImmSExti64i8Value(uint64_t Value) {
606 return (( Value <= 0x000000000000007FULL)||
607 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
610 static bool isImmSExti64i32Value(uint64_t Value) {
611 return (( Value <= 0x000000007FFFFFFFULL)||
612 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
616 /// X86Operand - Instances of this class represent a parsed X86 machine
618 struct X86Operand : public MCParsedAsmOperand {
626 SMLoc StartLoc, EndLoc;
661 X86Operand(KindTy K, SMLoc Start, SMLoc End)
662 : Kind(K), StartLoc(Start), EndLoc(End) {}
664 StringRef getSymName() { return SymName; }
665 void *getOpDecl() { return OpDecl; }
667 /// getStartLoc - Get the location of the first token of this operand.
668 SMLoc getStartLoc() const { return StartLoc; }
669 /// getEndLoc - Get the location of the last token of this operand.
670 SMLoc getEndLoc() const { return EndLoc; }
671 /// getLocRange - Get the range between the first and last token of this
673 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
674 /// getOffsetOfLoc - Get the location of the offset operator.
675 SMLoc getOffsetOfLoc() const { return OffsetOfLoc; }
677 virtual void print(raw_ostream &OS) const {}
679 StringRef getToken() const {
680 assert(Kind == Token && "Invalid access!");
681 return StringRef(Tok.Data, Tok.Length);
683 void setTokenValue(StringRef Value) {
684 assert(Kind == Token && "Invalid access!");
685 Tok.Data = Value.data();
686 Tok.Length = Value.size();
689 unsigned getReg() const {
690 assert(Kind == Register && "Invalid access!");
694 const MCExpr *getImm() const {
695 assert(Kind == Immediate && "Invalid access!");
699 const MCExpr *getMemDisp() const {
700 assert(Kind == Memory && "Invalid access!");
703 unsigned getMemSegReg() const {
704 assert(Kind == Memory && "Invalid access!");
707 unsigned getMemBaseReg() const {
708 assert(Kind == Memory && "Invalid access!");
711 unsigned getMemIndexReg() const {
712 assert(Kind == Memory && "Invalid access!");
715 unsigned getMemScale() const {
716 assert(Kind == Memory && "Invalid access!");
720 bool isToken() const {return Kind == Token; }
722 bool isImm() const { return Kind == Immediate; }
724 bool isImmSExti16i8() const {
728 // If this isn't a constant expr, just assume it fits and let relaxation
730 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
734 // Otherwise, check the value is in a range that makes sense for this
736 return isImmSExti16i8Value(CE->getValue());
738 bool isImmSExti32i8() const {
742 // If this isn't a constant expr, just assume it fits and let relaxation
744 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748 // Otherwise, check the value is in a range that makes sense for this
750 return isImmSExti32i8Value(CE->getValue());
752 bool isImmZExtu32u8() const {
756 // If this isn't a constant expr, just assume it fits and let relaxation
758 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762 // Otherwise, check the value is in a range that makes sense for this
764 return isImmZExtu32u8Value(CE->getValue());
766 bool isImmSExti64i8() const {
770 // If this isn't a constant expr, just assume it fits and let relaxation
772 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
776 // Otherwise, check the value is in a range that makes sense for this
778 return isImmSExti64i8Value(CE->getValue());
780 bool isImmSExti64i32() const {
784 // If this isn't a constant expr, just assume it fits and let relaxation
786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790 // Otherwise, check the value is in a range that makes sense for this
792 return isImmSExti64i32Value(CE->getValue());
795 bool isOffsetOf() const {
796 return OffsetOfLoc.getPointer();
799 bool needAddressOf() const {
803 bool isMem() const { return Kind == Memory; }
804 bool isMem8() const {
805 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
807 bool isMem16() const {
808 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
810 bool isMem32() const {
811 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
813 bool isMem64() const {
814 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
816 bool isMem80() const {
817 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
819 bool isMem128() const {
820 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
822 bool isMem256() const {
823 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
825 bool isMem512() const {
826 return Kind == Memory && (!Mem.Size || Mem.Size == 512);
829 bool isMemVX32() const {
830 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
831 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
833 bool isMemVY32() const {
834 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
835 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
837 bool isMemVX64() const {
838 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
839 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
841 bool isMemVY64() const {
842 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
843 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
845 bool isMemVZ32() const {
846 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
847 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
849 bool isMemVZ64() const {
850 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
851 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
854 bool isAbsMem() const {
855 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
856 !getMemIndexReg() && getMemScale() == 1;
859 bool isMemOffs8() const {
860 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
861 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 8);
863 bool isMemOffs16() const {
864 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
865 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 16);
867 bool isMemOffs32() const {
868 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
869 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 32);
871 bool isMemOffs64() const {
872 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
873 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 64);
876 bool isReg() const { return Kind == Register; }
878 bool isGR32orGR64() const {
879 return Kind == Register &&
880 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
881 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
884 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
885 // Add as immediates when possible.
886 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
887 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
889 Inst.addOperand(MCOperand::CreateExpr(Expr));
892 void addRegOperands(MCInst &Inst, unsigned N) const {
893 assert(N == 1 && "Invalid number of operands!");
894 Inst.addOperand(MCOperand::CreateReg(getReg()));
897 static unsigned getGR32FromGR64(unsigned RegNo) {
899 default: llvm_unreachable("Unexpected register");
900 case X86::RAX: return X86::EAX;
901 case X86::RCX: return X86::ECX;
902 case X86::RDX: return X86::EDX;
903 case X86::RBX: return X86::EBX;
904 case X86::RBP: return X86::EBP;
905 case X86::RSP: return X86::ESP;
906 case X86::RSI: return X86::ESI;
907 case X86::RDI: return X86::EDI;
908 case X86::R8: return X86::R8D;
909 case X86::R9: return X86::R9D;
910 case X86::R10: return X86::R10D;
911 case X86::R11: return X86::R11D;
912 case X86::R12: return X86::R12D;
913 case X86::R13: return X86::R13D;
914 case X86::R14: return X86::R14D;
915 case X86::R15: return X86::R15D;
916 case X86::RIP: return X86::EIP;
920 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
921 assert(N == 1 && "Invalid number of operands!");
922 unsigned RegNo = getReg();
923 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
924 RegNo = getGR32FromGR64(RegNo);
925 Inst.addOperand(MCOperand::CreateReg(RegNo));
928 void addImmOperands(MCInst &Inst, unsigned N) const {
929 assert(N == 1 && "Invalid number of operands!");
930 addExpr(Inst, getImm());
933 void addMemOperands(MCInst &Inst, unsigned N) const {
934 assert((N == 5) && "Invalid number of operands!");
935 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
936 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
937 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
938 addExpr(Inst, getMemDisp());
939 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
942 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
943 assert((N == 1) && "Invalid number of operands!");
944 // Add as immediates when possible.
945 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
946 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
948 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
951 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
952 assert((N == 1) && "Invalid number of operands!");
953 // Add as immediates when possible.
954 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
955 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
957 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
960 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
961 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
962 X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
963 Res->Tok.Data = Str.data();
964 Res->Tok.Length = Str.size();
968 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
969 bool AddressOf = false,
970 SMLoc OffsetOfLoc = SMLoc(),
971 StringRef SymName = StringRef(),
973 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
974 Res->Reg.RegNo = RegNo;
975 Res->AddressOf = AddressOf;
976 Res->OffsetOfLoc = OffsetOfLoc;
977 Res->SymName = SymName;
978 Res->OpDecl = OpDecl;
982 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
983 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
988 /// Create an absolute memory operand.
989 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
990 unsigned Size = 0, StringRef SymName = StringRef(),
992 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
994 Res->Mem.Disp = Disp;
995 Res->Mem.BaseReg = 0;
996 Res->Mem.IndexReg = 0;
998 Res->Mem.Size = Size;
999 Res->SymName = SymName;
1000 Res->OpDecl = OpDecl;
1001 Res->AddressOf = false;
1005 /// Create a generalized memory operand.
1006 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
1007 unsigned BaseReg, unsigned IndexReg,
1008 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
1010 StringRef SymName = StringRef(),
1012 // We should never just have a displacement, that should be parsed as an
1013 // absolute memory operand.
1014 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
1016 // The scale should always be one of {1,2,4,8}.
1017 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
1019 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
1020 Res->Mem.SegReg = SegReg;
1021 Res->Mem.Disp = Disp;
1022 Res->Mem.BaseReg = BaseReg;
1023 Res->Mem.IndexReg = IndexReg;
1024 Res->Mem.Scale = Scale;
1025 Res->Mem.Size = Size;
1026 Res->SymName = SymName;
1027 Res->OpDecl = OpDecl;
1028 Res->AddressOf = false;
1033 } // end anonymous namespace.
1035 bool X86AsmParser::isSrcOp(X86Operand &Op) {
1036 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;
1038 return (Op.isMem() &&
1039 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
1040 isa<MCConstantExpr>(Op.Mem.Disp) &&
1041 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1042 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
1045 bool X86AsmParser::isDstOp(X86Operand &Op) {
1046 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
1048 return Op.isMem() &&
1049 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&
1050 isa<MCConstantExpr>(Op.Mem.Disp) &&
1051 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1052 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
1055 bool X86AsmParser::ParseRegister(unsigned &RegNo,
1056 SMLoc &StartLoc, SMLoc &EndLoc) {
1058 const AsmToken &PercentTok = Parser.getTok();
1059 StartLoc = PercentTok.getLoc();
1061 // If we encounter a %, ignore it. This code handles registers with and
1062 // without the prefix, unprefixed registers can occur in cfi directives.
1063 if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
1064 Parser.Lex(); // Eat percent token.
1066 const AsmToken &Tok = Parser.getTok();
1067 EndLoc = Tok.getEndLoc();
1069 if (Tok.isNot(AsmToken::Identifier)) {
1070 if (isParsingIntelSyntax()) return true;
1071 return Error(StartLoc, "invalid register name",
1072 SMRange(StartLoc, EndLoc));
1075 RegNo = MatchRegisterName(Tok.getString());
1077 // If the match failed, try the register name as lowercase.
1079 RegNo = MatchRegisterName(Tok.getString().lower());
1081 if (!is64BitMode()) {
1082 // FIXME: This should be done using Requires<In32BitMode> and
1083 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1085 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
1087 if (RegNo == X86::RIZ ||
1088 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1089 X86II::isX86_64NonExtLowByteReg(RegNo) ||
1090 X86II::isX86_64ExtendedReg(RegNo))
1091 return Error(StartLoc, "register %"
1092 + Tok.getString() + " is only available in 64-bit mode",
1093 SMRange(StartLoc, EndLoc));
1096 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1097 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
1099 Parser.Lex(); // Eat 'st'
1101 // Check to see if we have '(4)' after %st.
1102 if (getLexer().isNot(AsmToken::LParen))
1107 const AsmToken &IntTok = Parser.getTok();
1108 if (IntTok.isNot(AsmToken::Integer))
1109 return Error(IntTok.getLoc(), "expected stack index");
1110 switch (IntTok.getIntVal()) {
1111 case 0: RegNo = X86::ST0; break;
1112 case 1: RegNo = X86::ST1; break;
1113 case 2: RegNo = X86::ST2; break;
1114 case 3: RegNo = X86::ST3; break;
1115 case 4: RegNo = X86::ST4; break;
1116 case 5: RegNo = X86::ST5; break;
1117 case 6: RegNo = X86::ST6; break;
1118 case 7: RegNo = X86::ST7; break;
1119 default: return Error(IntTok.getLoc(), "invalid stack index");
1122 if (getParser().Lex().isNot(AsmToken::RParen))
1123 return Error(Parser.getTok().getLoc(), "expected ')'");
1125 EndLoc = Parser.getTok().getEndLoc();
1126 Parser.Lex(); // Eat ')'
1130 EndLoc = Parser.getTok().getEndLoc();
1132 // If this is "db[0-7]", match it as an alias
1134 if (RegNo == 0 && Tok.getString().size() == 3 &&
1135 Tok.getString().startswith("db")) {
1136 switch (Tok.getString()[2]) {
1137 case '0': RegNo = X86::DR0; break;
1138 case '1': RegNo = X86::DR1; break;
1139 case '2': RegNo = X86::DR2; break;
1140 case '3': RegNo = X86::DR3; break;
1141 case '4': RegNo = X86::DR4; break;
1142 case '5': RegNo = X86::DR5; break;
1143 case '6': RegNo = X86::DR6; break;
1144 case '7': RegNo = X86::DR7; break;
1148 EndLoc = Parser.getTok().getEndLoc();
1149 Parser.Lex(); // Eat it.
1155 if (isParsingIntelSyntax()) return true;
1156 return Error(StartLoc, "invalid register name",
1157 SMRange(StartLoc, EndLoc));
1160 Parser.Lex(); // Eat identifier token.
1164 X86Operand *X86AsmParser::ParseOperand() {
1165 if (isParsingIntelSyntax())
1166 return ParseIntelOperand();
1167 return ParseATTOperand();
1170 /// getIntelMemOperandSize - Return intel memory operand size.
1171 static unsigned getIntelMemOperandSize(StringRef OpStr) {
1172 unsigned Size = StringSwitch<unsigned>(OpStr)
1173 .Cases("BYTE", "byte", 8)
1174 .Cases("WORD", "word", 16)
1175 .Cases("DWORD", "dword", 32)
1176 .Cases("QWORD", "qword", 64)
1177 .Cases("XWORD", "xword", 80)
1178 .Cases("XMMWORD", "xmmword", 128)
1179 .Cases("YMMWORD", "ymmword", 256)
1185 X86AsmParser::CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
1186 unsigned BaseReg, unsigned IndexReg,
1187 unsigned Scale, SMLoc Start, SMLoc End,
1188 unsigned Size, StringRef Identifier,
1189 InlineAsmIdentifierInfo &Info){
1190 if (isa<MCSymbolRefExpr>(Disp)) {
1191 // If this is not a VarDecl then assume it is a FuncDecl or some other label
1192 // reference. We need an 'r' constraint here, so we need to create register
1193 // operand to ensure proper matching. Just pick a GPR based on the size of
1195 if (!Info.IsVarDecl) {
1196 unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
1197 return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true,
1198 SMLoc(), Identifier, Info.OpDecl);
1201 Size = Info.Type * 8; // Size is in terms of bits in this context.
1203 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_SizeDirective, Start,
1208 // When parsing inline assembly we set the base register to a non-zero value
1209 // if we don't know the actual value at this time. This is necessary to
1210 // get the matching correct in some cases.
1211 BaseReg = BaseReg ? BaseReg : 1;
1212 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1213 End, Size, Identifier, Info.OpDecl);
1217 RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> *AsmRewrites,
1218 StringRef SymName, int64_t ImmDisp,
1219 int64_t FinalImmDisp, SMLoc &BracLoc,
1220 SMLoc &StartInBrac, SMLoc &End) {
1221 // Remove the '[' and ']' from the IR string.
1222 AsmRewrites->push_back(AsmRewrite(AOK_Skip, BracLoc, 1));
1223 AsmRewrites->push_back(AsmRewrite(AOK_Skip, End, 1));
1225 // If ImmDisp is non-zero, then we parsed a displacement before the
1226 // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
1227 // If ImmDisp doesn't match the displacement computed by the state machine
1228 // then we have an additional displacement in the bracketed expression.
1229 if (ImmDisp != FinalImmDisp) {
1231 // We have an immediate displacement before the bracketed expression.
1232 // Adjust this to match the final immediate displacement.
1234 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1235 E = AsmRewrites->end(); I != E; ++I) {
1236 if ((*I).Loc.getPointer() > BracLoc.getPointer())
1238 if ((*I).Kind == AOK_ImmPrefix || (*I).Kind == AOK_Imm) {
1239 assert (!Found && "ImmDisp already rewritten.");
1240 (*I).Kind = AOK_Imm;
1241 (*I).Len = BracLoc.getPointer() - (*I).Loc.getPointer();
1242 (*I).Val = FinalImmDisp;
1247 assert (Found && "Unable to rewrite ImmDisp.");
1250 // We have a symbolic and an immediate displacement, but no displacement
1251 // before the bracketed expression. Put the immediate displacement
1252 // before the bracketed expression.
1253 AsmRewrites->push_back(AsmRewrite(AOK_Imm, BracLoc, 0, FinalImmDisp));
1256 // Remove all the ImmPrefix rewrites within the brackets.
1257 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1258 E = AsmRewrites->end(); I != E; ++I) {
1259 if ((*I).Loc.getPointer() < StartInBrac.getPointer())
1261 if ((*I).Kind == AOK_ImmPrefix)
1262 (*I).Kind = AOK_Delete;
1264 const char *SymLocPtr = SymName.data();
1265 // Skip everything before the symbol.
1266 if (unsigned Len = SymLocPtr - StartInBrac.getPointer()) {
1267 assert(Len > 0 && "Expected a non-negative length.");
1268 AsmRewrites->push_back(AsmRewrite(AOK_Skip, StartInBrac, Len));
1270 // Skip everything after the symbol.
1271 if (unsigned Len = End.getPointer() - (SymLocPtr + SymName.size())) {
1272 SMLoc Loc = SMLoc::getFromPointer(SymLocPtr + SymName.size());
1273 assert(Len > 0 && "Expected a non-negative length.");
1274 AsmRewrites->push_back(AsmRewrite(AOK_Skip, Loc, Len));
1278 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1279 const AsmToken &Tok = Parser.getTok();
1283 bool UpdateLocLex = true;
1285 // The period in the dot operator (e.g., [ebx].foo.bar) is parsed as an
1286 // identifier. Don't try an parse it as a register.
1287 if (Tok.getString().startswith("."))
1290 // If we're parsing an immediate expression, we don't expect a '['.
1291 if (SM.getStopOnLBrac() && getLexer().getKind() == AsmToken::LBrac)
1294 switch (getLexer().getKind()) {
1296 if (SM.isValidEndState()) {
1300 return Error(Tok.getLoc(), "unknown token in expression");
1302 case AsmToken::EndOfStatement: {
1306 case AsmToken::Identifier: {
1307 // This could be a register or a symbolic displacement.
1310 SMLoc IdentLoc = Tok.getLoc();
1311 StringRef Identifier = Tok.getString();
1312 if(!ParseRegister(TmpReg, IdentLoc, End)) {
1313 SM.onRegister(TmpReg);
1314 UpdateLocLex = false;
1317 if (!isParsingInlineAsm()) {
1318 if (getParser().parsePrimaryExpr(Val, End))
1319 return Error(Tok.getLoc(), "Unexpected identifier!");
1321 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1322 if (ParseIntelIdentifier(Val, Identifier, Info,
1323 /*Unevaluated=*/false, End))
1326 SM.onIdentifierExpr(Val, Identifier);
1327 UpdateLocLex = false;
1330 return Error(Tok.getLoc(), "Unexpected identifier!");
1332 case AsmToken::Integer:
1333 if (isParsingInlineAsm() && SM.getAddImmPrefix())
1334 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
1336 SM.onInteger(Tok.getIntVal());
1338 case AsmToken::Plus: SM.onPlus(); break;
1339 case AsmToken::Minus: SM.onMinus(); break;
1340 case AsmToken::Star: SM.onStar(); break;
1341 case AsmToken::Slash: SM.onDivide(); break;
1342 case AsmToken::LBrac: SM.onLBrac(); break;
1343 case AsmToken::RBrac: SM.onRBrac(); break;
1344 case AsmToken::LParen: SM.onLParen(); break;
1345 case AsmToken::RParen: SM.onRParen(); break;
1348 return Error(Tok.getLoc(), "unknown token in expression");
1350 if (!Done && UpdateLocLex)
1351 End = consumeToken();
1356 X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
1359 const AsmToken &Tok = Parser.getTok();
1360 SMLoc BracLoc = Tok.getLoc(), End = Tok.getEndLoc();
1361 if (getLexer().isNot(AsmToken::LBrac))
1362 return ErrorOperand(BracLoc, "Expected '[' token!");
1363 Parser.Lex(); // Eat '['
1365 SMLoc StartInBrac = Tok.getLoc();
1366 // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
1367 // may have already parsed an immediate displacement before the bracketed
1369 IntelExprStateMachine SM(ImmDisp, /*StopOnLBrac=*/false, /*AddImmPrefix=*/true);
1370 if (ParseIntelExpression(SM, End))
1374 if (const MCExpr *Sym = SM.getSym()) {
1375 // A symbolic displacement.
1377 if (isParsingInlineAsm())
1378 RewriteIntelBracExpression(InstInfo->AsmRewrites, SM.getSymName(),
1379 ImmDisp, SM.getImm(), BracLoc, StartInBrac,
1382 // An immediate displacement only.
1383 Disp = MCConstantExpr::Create(SM.getImm(), getContext());
1386 // Parse the dot operator (e.g., [ebx].foo.bar).
1387 if (Tok.getString().startswith(".")) {
1388 const MCExpr *NewDisp;
1389 if (ParseIntelDotOperator(Disp, NewDisp))
1392 End = Tok.getEndLoc();
1393 Parser.Lex(); // Eat the field.
1397 int BaseReg = SM.getBaseReg();
1398 int IndexReg = SM.getIndexReg();
1399 int Scale = SM.getScale();
1400 if (!isParsingInlineAsm()) {
1402 if (!BaseReg && !IndexReg) {
1404 return X86Operand::CreateMem(Disp, Start, End, Size);
1406 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, Size);
1408 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1412 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1413 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1414 End, Size, SM.getSymName(), Info);
1417 // Inline assembly may use variable names with namespace alias qualifiers.
1418 bool X86AsmParser::ParseIntelIdentifier(const MCExpr *&Val,
1419 StringRef &Identifier,
1420 InlineAsmIdentifierInfo &Info,
1421 bool IsUnevaluatedOperand, SMLoc &End) {
1422 assert (isParsingInlineAsm() && "Expected to be parsing inline assembly.");
1425 StringRef LineBuf(Identifier.data());
1426 SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
1428 const AsmToken &Tok = Parser.getTok();
1430 // Advance the token stream until the end of the current token is
1431 // after the end of what the frontend claimed.
1432 const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
1434 End = Tok.getEndLoc();
1437 assert(End.getPointer() <= EndPtr && "frontend claimed part of a token?");
1438 if (End.getPointer() == EndPtr) break;
1441 // Create the symbol reference.
1442 Identifier = LineBuf;
1443 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
1444 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1445 Val = MCSymbolRefExpr::Create(Sym, Variant, getParser().getContext());
1449 /// \brief Parse intel style segment override.
1450 X86Operand *X86AsmParser::ParseIntelSegmentOverride(unsigned SegReg,
1453 assert(SegReg != 0 && "Tried to parse a segment override without a segment!");
1454 const AsmToken &Tok = Parser.getTok(); // Eat colon.
1455 if (Tok.isNot(AsmToken::Colon))
1456 return ErrorOperand(Tok.getLoc(), "Expected ':' token!");
1457 Parser.Lex(); // Eat ':'
1459 int64_t ImmDisp = 0;
1460 if (getLexer().is(AsmToken::Integer)) {
1461 ImmDisp = Tok.getIntVal();
1462 AsmToken ImmDispToken = Parser.Lex(); // Eat the integer.
1464 if (isParsingInlineAsm())
1465 InstInfo->AsmRewrites->push_back(
1466 AsmRewrite(AOK_ImmPrefix, ImmDispToken.getLoc()));
1468 if (getLexer().isNot(AsmToken::LBrac)) {
1469 // An immediate following a 'segment register', 'colon' token sequence can
1470 // be followed by a bracketed expression. If it isn't we know we have our
1471 // final segment override.
1472 const MCExpr *Disp = MCConstantExpr::Create(ImmDisp, getContext());
1473 return X86Operand::CreateMem(SegReg, Disp, /*BaseReg=*/0, /*IndexReg=*/0,
1474 /*Scale=*/1, Start, ImmDispToken.getEndLoc(),
1479 if (getLexer().is(AsmToken::LBrac))
1480 return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
1484 if (!isParsingInlineAsm()) {
1485 if (getParser().parsePrimaryExpr(Val, End))
1486 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1488 return X86Operand::CreateMem(Val, Start, End, Size);
1491 InlineAsmIdentifierInfo Info;
1492 StringRef Identifier = Tok.getString();
1493 if (ParseIntelIdentifier(Val, Identifier, Info,
1494 /*Unevaluated=*/false, End))
1496 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1497 /*Scale=*/1, Start, End, Size, Identifier, Info);
1500 /// ParseIntelMemOperand - Parse intel style memory operand.
1501 X86Operand *X86AsmParser::ParseIntelMemOperand(int64_t ImmDisp, SMLoc Start,
1503 const AsmToken &Tok = Parser.getTok();
1506 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1507 if (getLexer().is(AsmToken::LBrac))
1508 return ParseIntelBracExpression(/*SegReg=*/0, Start, ImmDisp, Size);
1511 if (!isParsingInlineAsm()) {
1512 if (getParser().parsePrimaryExpr(Val, End))
1513 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1515 return X86Operand::CreateMem(Val, Start, End, Size);
1518 InlineAsmIdentifierInfo Info;
1519 StringRef Identifier = Tok.getString();
1520 if (ParseIntelIdentifier(Val, Identifier, Info,
1521 /*Unevaluated=*/false, End))
1523 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1524 /*Scale=*/1, Start, End, Size, Identifier, Info);
1527 /// Parse the '.' operator.
1528 bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
1529 const MCExpr *&NewDisp) {
1530 const AsmToken &Tok = Parser.getTok();
1531 int64_t OrigDispVal, DotDispVal;
1533 // FIXME: Handle non-constant expressions.
1534 if (const MCConstantExpr *OrigDisp = dyn_cast<MCConstantExpr>(Disp))
1535 OrigDispVal = OrigDisp->getValue();
1537 return Error(Tok.getLoc(), "Non-constant offsets are not supported!");
1540 StringRef DotDispStr = Tok.getString().drop_front(1);
1542 // .Imm gets lexed as a real.
1543 if (Tok.is(AsmToken::Real)) {
1545 DotDispStr.getAsInteger(10, DotDisp);
1546 DotDispVal = DotDisp.getZExtValue();
1547 } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1549 std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1550 if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1552 return Error(Tok.getLoc(), "Unable to lookup field reference!");
1553 DotDispVal = DotDisp;
1555 return Error(Tok.getLoc(), "Unexpected token type!");
1557 if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1558 SMLoc Loc = SMLoc::getFromPointer(DotDispStr.data());
1559 unsigned Len = DotDispStr.size();
1560 unsigned Val = OrigDispVal + DotDispVal;
1561 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_DotOperator, Loc, Len,
1565 NewDisp = MCConstantExpr::Create(OrigDispVal + DotDispVal, getContext());
1569 /// Parse the 'offset' operator. This operator is used to specify the
1570 /// location rather then the content of a variable.
1571 X86Operand *X86AsmParser::ParseIntelOffsetOfOperator() {
1572 const AsmToken &Tok = Parser.getTok();
1573 SMLoc OffsetOfLoc = Tok.getLoc();
1574 Parser.Lex(); // Eat offset.
1577 InlineAsmIdentifierInfo Info;
1578 SMLoc Start = Tok.getLoc(), End;
1579 StringRef Identifier = Tok.getString();
1580 if (ParseIntelIdentifier(Val, Identifier, Info,
1581 /*Unevaluated=*/false, End))
1584 // Don't emit the offset operator.
1585 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, OffsetOfLoc, 7));
1587 // The offset operator will have an 'r' constraint, thus we need to create
1588 // register operand to ensure proper matching. Just pick a GPR based on
1589 // the size of a pointer.
1590 unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
1591 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1592 OffsetOfLoc, Identifier, Info.OpDecl);
1595 enum IntelOperatorKind {
1601 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1602 /// returns the number of elements in an array. It returns the value 1 for
1603 /// non-array variables. The SIZE operator returns the size of a C or C++
1604 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1605 /// TYPE operator returns the size of a C or C++ type or variable. If the
1606 /// variable is an array, TYPE returns the size of a single element.
1607 X86Operand *X86AsmParser::ParseIntelOperator(unsigned OpKind) {
1608 const AsmToken &Tok = Parser.getTok();
1609 SMLoc TypeLoc = Tok.getLoc();
1610 Parser.Lex(); // Eat operator.
1612 const MCExpr *Val = 0;
1613 InlineAsmIdentifierInfo Info;
1614 SMLoc Start = Tok.getLoc(), End;
1615 StringRef Identifier = Tok.getString();
1616 if (ParseIntelIdentifier(Val, Identifier, Info,
1617 /*Unevaluated=*/true, End))
1621 return ErrorOperand(Start, "unable to lookup expression");
1625 default: llvm_unreachable("Unexpected operand kind!");
1626 case IOK_LENGTH: CVal = Info.Length; break;
1627 case IOK_SIZE: CVal = Info.Size; break;
1628 case IOK_TYPE: CVal = Info.Type; break;
1631 // Rewrite the type operator and the C or C++ type or variable in terms of an
1632 // immediate. E.g. TYPE foo -> $$4
1633 unsigned Len = End.getPointer() - TypeLoc.getPointer();
1634 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, TypeLoc, Len, CVal));
1636 const MCExpr *Imm = MCConstantExpr::Create(CVal, getContext());
1637 return X86Operand::CreateImm(Imm, Start, End);
1640 X86Operand *X86AsmParser::ParseIntelOperand() {
1641 const AsmToken &Tok = Parser.getTok();
1644 // Offset, length, type and size operators.
1645 if (isParsingInlineAsm()) {
1646 StringRef AsmTokStr = Tok.getString();
1647 if (AsmTokStr == "offset" || AsmTokStr == "OFFSET")
1648 return ParseIntelOffsetOfOperator();
1649 if (AsmTokStr == "length" || AsmTokStr == "LENGTH")
1650 return ParseIntelOperator(IOK_LENGTH);
1651 if (AsmTokStr == "size" || AsmTokStr == "SIZE")
1652 return ParseIntelOperator(IOK_SIZE);
1653 if (AsmTokStr == "type" || AsmTokStr == "TYPE")
1654 return ParseIntelOperator(IOK_TYPE);
1657 unsigned Size = getIntelMemOperandSize(Tok.getString());
1659 Parser.Lex(); // Eat operand size (e.g., byte, word).
1660 if (Tok.getString() != "PTR" && Tok.getString() != "ptr")
1661 return ErrorOperand(Start, "Expected 'PTR' or 'ptr' token!");
1662 Parser.Lex(); // Eat ptr.
1664 Start = Tok.getLoc();
1667 if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Minus) ||
1668 getLexer().is(AsmToken::LParen)) {
1669 AsmToken StartTok = Tok;
1670 IntelExprStateMachine SM(/*Imm=*/0, /*StopOnLBrac=*/true,
1671 /*AddImmPrefix=*/false);
1672 if (ParseIntelExpression(SM, End))
1675 int64_t Imm = SM.getImm();
1676 if (isParsingInlineAsm()) {
1677 unsigned Len = Tok.getLoc().getPointer() - Start.getPointer();
1678 if (StartTok.getString().size() == Len)
1679 // Just add a prefix if this wasn't a complex immediate expression.
1680 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix, Start));
1682 // Otherwise, rewrite the complex expression as a single immediate.
1683 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, Start, Len, Imm));
1686 if (getLexer().isNot(AsmToken::LBrac)) {
1687 const MCExpr *ImmExpr = MCConstantExpr::Create(Imm, getContext());
1688 return X86Operand::CreateImm(ImmExpr, Start, End);
1691 // Only positive immediates are valid.
1693 return ErrorOperand(Start, "expected a positive immediate displacement "
1694 "before bracketed expr.");
1696 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1697 return ParseIntelMemOperand(Imm, Start, Size);
1702 if (!ParseRegister(RegNo, Start, End)) {
1703 // If this is a segment register followed by a ':', then this is the start
1704 // of a segment override, otherwise this is a normal register reference.
1705 if (getLexer().isNot(AsmToken::Colon))
1706 return X86Operand::CreateReg(RegNo, Start, End);
1708 return ParseIntelSegmentOverride(/*SegReg=*/RegNo, Start, Size);
1712 return ParseIntelMemOperand(/*Disp=*/0, Start, Size);
1715 X86Operand *X86AsmParser::ParseATTOperand() {
1716 switch (getLexer().getKind()) {
1718 // Parse a memory operand with no segment register.
1719 return ParseMemOperand(0, Parser.getTok().getLoc());
1720 case AsmToken::Percent: {
1721 // Read the register.
1724 if (ParseRegister(RegNo, Start, End)) return 0;
1725 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
1726 Error(Start, "%eiz and %riz can only be used as index registers",
1727 SMRange(Start, End));
1731 // If this is a segment register followed by a ':', then this is the start
1732 // of a memory reference, otherwise this is a normal register reference.
1733 if (getLexer().isNot(AsmToken::Colon))
1734 return X86Operand::CreateReg(RegNo, Start, End);
1736 getParser().Lex(); // Eat the colon.
1737 return ParseMemOperand(RegNo, Start);
1739 case AsmToken::Dollar: {
1740 // $42 -> immediate.
1741 SMLoc Start = Parser.getTok().getLoc(), End;
1744 if (getParser().parseExpression(Val, End))
1746 return X86Operand::CreateImm(Val, Start, End);
1751 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1752 /// has already been parsed if present.
1753 X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
1755 // We have to disambiguate a parenthesized expression "(4+5)" from the start
1756 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
1757 // only way to do this without lookahead is to eat the '(' and see what is
1759 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
1760 if (getLexer().isNot(AsmToken::LParen)) {
1762 if (getParser().parseExpression(Disp, ExprEnd)) return 0;
1764 // After parsing the base expression we could either have a parenthesized
1765 // memory address or not. If not, return now. If so, eat the (.
1766 if (getLexer().isNot(AsmToken::LParen)) {
1767 // Unless we have a segment register, treat this as an immediate.
1769 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
1770 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1776 // Okay, we have a '('. We don't know if this is an expression or not, but
1777 // so we have to eat the ( to see beyond it.
1778 SMLoc LParenLoc = Parser.getTok().getLoc();
1779 Parser.Lex(); // Eat the '('.
1781 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
1782 // Nothing to do here, fall into the code below with the '(' part of the
1783 // memory operand consumed.
1787 // It must be an parenthesized expression, parse it now.
1788 if (getParser().parseParenExpression(Disp, ExprEnd))
1791 // After parsing the base expression we could either have a parenthesized
1792 // memory address or not. If not, return now. If so, eat the (.
1793 if (getLexer().isNot(AsmToken::LParen)) {
1794 // Unless we have a segment register, treat this as an immediate.
1796 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
1797 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1805 // If we reached here, then we just ate the ( of the memory operand. Process
1806 // the rest of the memory operand.
1807 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1810 if (getLexer().is(AsmToken::Percent)) {
1811 SMLoc StartLoc, EndLoc;
1812 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
1813 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
1814 Error(StartLoc, "eiz and riz can only be used as index registers",
1815 SMRange(StartLoc, EndLoc));
1820 if (getLexer().is(AsmToken::Comma)) {
1821 Parser.Lex(); // Eat the comma.
1822 IndexLoc = Parser.getTok().getLoc();
1824 // Following the comma we should have either an index register, or a scale
1825 // value. We don't support the later form, but we want to parse it
1828 // Not that even though it would be completely consistent to support syntax
1829 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
1830 if (getLexer().is(AsmToken::Percent)) {
1832 if (ParseRegister(IndexReg, L, L)) return 0;
1834 if (getLexer().isNot(AsmToken::RParen)) {
1835 // Parse the scale amount:
1836 // ::= ',' [scale-expression]
1837 if (getLexer().isNot(AsmToken::Comma)) {
1838 Error(Parser.getTok().getLoc(),
1839 "expected comma in scale expression");
1842 Parser.Lex(); // Eat the comma.
1844 if (getLexer().isNot(AsmToken::RParen)) {
1845 SMLoc Loc = Parser.getTok().getLoc();
1848 if (getParser().parseAbsoluteExpression(ScaleVal)){
1849 Error(Loc, "expected scale expression");
1853 // Validate the scale amount.
1854 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
1855 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
1858 Scale = (unsigned)ScaleVal;
1861 } else if (getLexer().isNot(AsmToken::RParen)) {
1862 // A scale amount without an index is ignored.
1864 SMLoc Loc = Parser.getTok().getLoc();
1867 if (getParser().parseAbsoluteExpression(Value))
1871 Warning(Loc, "scale factor without index register is ignored");
1876 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
1877 if (getLexer().isNot(AsmToken::RParen)) {
1878 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
1881 SMLoc MemEnd = Parser.getTok().getEndLoc();
1882 Parser.Lex(); // Eat the ')'.
1884 // If we have both a base register and an index register make sure they are
1885 // both 64-bit or 32-bit registers.
1886 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1887 if (BaseReg != 0 && IndexReg != 0) {
1888 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1889 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1890 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
1891 IndexReg != X86::RIZ) {
1892 Error(IndexLoc, "index register is 32-bit, but base register is 64-bit");
1895 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1896 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1897 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
1898 IndexReg != X86::EIZ){
1899 Error(IndexLoc, "index register is 64-bit, but base register is 32-bit");
1904 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
1909 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1910 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1912 StringRef PatchedName = Name;
1914 // FIXME: Hack to recognize setneb as setne.
1915 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
1916 PatchedName != "setb" && PatchedName != "setnb")
1917 PatchedName = PatchedName.substr(0, Name.size()-1);
1919 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
1920 const MCExpr *ExtraImmOp = 0;
1921 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
1922 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
1923 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
1924 bool IsVCMP = PatchedName[0] == 'v';
1925 unsigned SSECCIdx = IsVCMP ? 4 : 3;
1926 unsigned SSEComparisonCode = StringSwitch<unsigned>(
1927 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
1931 .Case("unord", 0x03)
1936 /* AVX only from here */
1937 .Case("eq_uq", 0x08)
1940 .Case("false", 0x0B)
1941 .Case("neq_oq", 0x0C)
1945 .Case("eq_os", 0x10)
1946 .Case("lt_oq", 0x11)
1947 .Case("le_oq", 0x12)
1948 .Case("unord_s", 0x13)
1949 .Case("neq_us", 0x14)
1950 .Case("nlt_uq", 0x15)
1951 .Case("nle_uq", 0x16)
1952 .Case("ord_s", 0x17)
1953 .Case("eq_us", 0x18)
1954 .Case("nge_uq", 0x19)
1955 .Case("ngt_uq", 0x1A)
1956 .Case("false_os", 0x1B)
1957 .Case("neq_os", 0x1C)
1958 .Case("ge_oq", 0x1D)
1959 .Case("gt_oq", 0x1E)
1960 .Case("true_us", 0x1F)
1962 if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
1963 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
1964 getParser().getContext());
1965 if (PatchedName.endswith("ss")) {
1966 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
1967 } else if (PatchedName.endswith("sd")) {
1968 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
1969 } else if (PatchedName.endswith("ps")) {
1970 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
1972 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
1973 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
1978 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
1980 if (ExtraImmOp && !isParsingIntelSyntax())
1981 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1983 // Determine whether this is an instruction prefix.
1985 Name == "lock" || Name == "rep" ||
1986 Name == "repe" || Name == "repz" ||
1987 Name == "repne" || Name == "repnz" ||
1988 Name == "rex64" || Name == "data16";
1991 // This does the actual operand parsing. Don't parse any more if we have a
1992 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
1993 // just want to parse the "lock" as the first instruction and the "incl" as
1995 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
1997 // Parse '*' modifier.
1998 if (getLexer().is(AsmToken::Star))
1999 Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2001 // Read the first operand.
2002 if (X86Operand *Op = ParseOperand())
2003 Operands.push_back(Op);
2005 Parser.eatToEndOfStatement();
2009 while (getLexer().is(AsmToken::Comma)) {
2010 Parser.Lex(); // Eat the comma.
2012 // Parse and remember the operand.
2013 if (X86Operand *Op = ParseOperand())
2014 Operands.push_back(Op);
2016 Parser.eatToEndOfStatement();
2021 if (STI.getFeatureBits() & X86::FeatureAVX512) {
2022 // Parse mask register {%k1}
2023 if (getLexer().is(AsmToken::LCurly)) {
2024 Operands.push_back(X86Operand::CreateToken("{", consumeToken()));
2025 if (X86Operand *Op = ParseOperand()) {
2026 Operands.push_back(Op);
2027 if (!getLexer().is(AsmToken::RCurly)) {
2028 SMLoc Loc = getLexer().getLoc();
2029 Parser.eatToEndOfStatement();
2030 return Error(Loc, "Expected } at this point");
2032 Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2034 Parser.eatToEndOfStatement();
2038 // Parse "zeroing non-masked" semantic {z}
2039 if (getLexer().is(AsmToken::LCurly)) {
2040 Operands.push_back(X86Operand::CreateToken("{z}", consumeToken()));
2041 if (!getLexer().is(AsmToken::Identifier) || getLexer().getTok().getIdentifier() != "z") {
2042 SMLoc Loc = getLexer().getLoc();
2043 Parser.eatToEndOfStatement();
2044 return Error(Loc, "Expected z at this point");
2046 Parser.Lex(); // Eat the z
2047 if (!getLexer().is(AsmToken::RCurly)) {
2048 SMLoc Loc = getLexer().getLoc();
2049 Parser.eatToEndOfStatement();
2050 return Error(Loc, "Expected } at this point");
2052 Parser.Lex(); // Eat the }
2056 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2057 SMLoc Loc = getLexer().getLoc();
2058 Parser.eatToEndOfStatement();
2059 return Error(Loc, "unexpected token in argument list");
2063 if (getLexer().is(AsmToken::EndOfStatement))
2064 Parser.Lex(); // Consume the EndOfStatement
2065 else if (isPrefix && getLexer().is(AsmToken::Slash))
2066 Parser.Lex(); // Consume the prefix separator Slash
2068 if (ExtraImmOp && isParsingIntelSyntax())
2069 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
2071 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
2072 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2073 // documented form in various unofficial manuals, so a lot of code uses it.
2074 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
2075 Operands.size() == 3) {
2076 X86Operand &Op = *(X86Operand*)Operands.back();
2077 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2078 isa<MCConstantExpr>(Op.Mem.Disp) &&
2079 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2080 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2081 SMLoc Loc = Op.getEndLoc();
2082 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2086 // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
2087 if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
2088 Operands.size() == 3) {
2089 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2090 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2091 isa<MCConstantExpr>(Op.Mem.Disp) &&
2092 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2093 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2094 SMLoc Loc = Op.getEndLoc();
2095 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2099 // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
2100 if (Name.startswith("ins") && Operands.size() == 3 &&
2101 (Name == "insb" || Name == "insw" || Name == "insl")) {
2102 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2103 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2104 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
2105 Operands.pop_back();
2106 Operands.pop_back();
2112 // Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
2113 if (Name.startswith("outs") && Operands.size() == 3 &&
2114 (Name == "outsb" || Name == "outsw" || Name == "outsl")) {
2115 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2116 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2117 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
2118 Operands.pop_back();
2119 Operands.pop_back();
2125 // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
2126 if (Name.startswith("movs") && Operands.size() == 3 &&
2127 (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
2128 (is64BitMode() && Name == "movsq"))) {
2129 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2130 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2131 if (isSrcOp(Op) && isDstOp(Op2)) {
2132 Operands.pop_back();
2133 Operands.pop_back();
2138 // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
2139 if (Name.startswith("lods") && Operands.size() == 3 &&
2140 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
2141 Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) {
2142 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2143 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
2144 if (isSrcOp(*Op1) && Op2->isReg()) {
2146 unsigned reg = Op2->getReg();
2147 bool isLods = Name == "lods";
2148 if (reg == X86::AL && (isLods || Name == "lodsb"))
2150 else if (reg == X86::AX && (isLods || Name == "lodsw"))
2152 else if (reg == X86::EAX && (isLods || Name == "lodsl"))
2154 else if (reg == X86::RAX && (isLods || Name == "lodsq"))
2159 Operands.pop_back();
2160 Operands.pop_back();
2164 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
2168 // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
2169 if (Name.startswith("stos") && Operands.size() == 3 &&
2170 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
2171 Name == "stosl" || (is64BitMode() && Name == "stosq"))) {
2172 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2173 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
2174 if (isDstOp(*Op2) && Op1->isReg()) {
2176 unsigned reg = Op1->getReg();
2177 bool isStos = Name == "stos";
2178 if (reg == X86::AL && (isStos || Name == "stosb"))
2180 else if (reg == X86::AX && (isStos || Name == "stosw"))
2182 else if (reg == X86::EAX && (isStos || Name == "stosl"))
2184 else if (reg == X86::RAX && (isStos || Name == "stosq"))
2189 Operands.pop_back();
2190 Operands.pop_back();
2194 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
2199 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
2201 if ((Name.startswith("shr") || Name.startswith("sar") ||
2202 Name.startswith("shl") || Name.startswith("sal") ||
2203 Name.startswith("rcl") || Name.startswith("rcr") ||
2204 Name.startswith("rol") || Name.startswith("ror")) &&
2205 Operands.size() == 3) {
2206 if (isParsingIntelSyntax()) {
2208 X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
2209 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2210 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2212 Operands.pop_back();
2215 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2216 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2217 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2219 Operands.erase(Operands.begin() + 1);
2224 // Transforms "int $3" into "int3" as a size optimization. We can't write an
2225 // instalias with an immediate operand yet.
2226 if (Name == "int" && Operands.size() == 2) {
2227 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2228 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2229 cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
2231 Operands.erase(Operands.begin() + 1);
2232 static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
2239 static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
2242 TmpInst.setOpcode(Opcode);
2244 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2245 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2246 TmpInst.addOperand(Inst.getOperand(0));
2251 static bool convert16i16to16ri8(MCInst &Inst, unsigned Opcode,
2252 bool isCmp = false) {
2253 if (!Inst.getOperand(0).isImm() ||
2254 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
2257 return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
2260 static bool convert32i32to32ri8(MCInst &Inst, unsigned Opcode,
2261 bool isCmp = false) {
2262 if (!Inst.getOperand(0).isImm() ||
2263 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
2266 return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
2269 static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
2270 bool isCmp = false) {
2271 if (!Inst.getOperand(0).isImm() ||
2272 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
2275 return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
2279 processInstruction(MCInst &Inst,
2280 const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
2281 switch (Inst.getOpcode()) {
2282 default: return false;
2283 case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
2284 case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
2285 case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
2286 case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
2287 case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
2288 case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
2289 case X86::OR16i16: return convert16i16to16ri8(Inst, X86::OR16ri8);
2290 case X86::OR32i32: return convert32i32to32ri8(Inst, X86::OR32ri8);
2291 case X86::OR64i32: return convert64i32to64ri8(Inst, X86::OR64ri8);
2292 case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
2293 case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
2294 case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
2295 case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
2296 case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
2297 case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
2298 case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
2299 case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
2300 case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
2301 case X86::ADC16i16: return convert16i16to16ri8(Inst, X86::ADC16ri8);
2302 case X86::ADC32i32: return convert32i32to32ri8(Inst, X86::ADC32ri8);
2303 case X86::ADC64i32: return convert64i32to64ri8(Inst, X86::ADC64ri8);
2304 case X86::SBB16i16: return convert16i16to16ri8(Inst, X86::SBB16ri8);
2305 case X86::SBB32i32: return convert32i32to32ri8(Inst, X86::SBB32ri8);
2306 case X86::SBB64i32: return convert64i32to64ri8(Inst, X86::SBB64ri8);
2307 case X86::VMOVAPDrr:
2308 case X86::VMOVAPDYrr:
2309 case X86::VMOVAPSrr:
2310 case X86::VMOVAPSYrr:
2311 case X86::VMOVDQArr:
2312 case X86::VMOVDQAYrr:
2313 case X86::VMOVDQUrr:
2314 case X86::VMOVDQUYrr:
2315 case X86::VMOVUPDrr:
2316 case X86::VMOVUPDYrr:
2317 case X86::VMOVUPSrr:
2318 case X86::VMOVUPSYrr: {
2319 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2320 !X86II::isX86_64ExtendedReg(Inst.getOperand(1).getReg()))
2324 switch (Inst.getOpcode()) {
2325 default: llvm_unreachable("Invalid opcode");
2326 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2327 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2328 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2329 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2330 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2331 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2332 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2333 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2334 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
2335 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
2336 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
2337 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
2339 Inst.setOpcode(NewOpc);
2343 case X86::VMOVSSrr: {
2344 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2345 !X86II::isX86_64ExtendedReg(Inst.getOperand(2).getReg()))
2348 switch (Inst.getOpcode()) {
2349 default: llvm_unreachable("Invalid opcode");
2350 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
2351 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
2353 Inst.setOpcode(NewOpc);
2359 static const char *getSubtargetFeatureName(unsigned Val);
2361 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2362 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2363 MCStreamer &Out, unsigned &ErrorInfo,
2364 bool MatchingInlineAsm) {
2365 assert(!Operands.empty() && "Unexpect empty operand list!");
2366 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
2367 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
2368 ArrayRef<SMRange> EmptyRanges = None;
2370 // First, handle aliases that expand to multiple instructions.
2371 // FIXME: This should be replaced with a real .td file alias mechanism.
2372 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2374 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
2375 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
2376 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
2377 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
2379 Inst.setOpcode(X86::WAIT);
2381 if (!MatchingInlineAsm)
2382 Out.EmitInstruction(Inst);
2385 StringSwitch<const char*>(Op->getToken())
2386 .Case("finit", "fninit")
2387 .Case("fsave", "fnsave")
2388 .Case("fstcw", "fnstcw")
2389 .Case("fstcww", "fnstcw")
2390 .Case("fstenv", "fnstenv")
2391 .Case("fstsw", "fnstsw")
2392 .Case("fstsww", "fnstsw")
2393 .Case("fclex", "fnclex")
2395 assert(Repl && "Unknown wait-prefixed instruction");
2397 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2400 bool WasOriginallyInvalidOperand = false;
2403 // First, try a direct match.
2404 switch (MatchInstructionImpl(Operands, Inst,
2405 ErrorInfo, MatchingInlineAsm,
2406 isParsingIntelSyntax())) {
2409 // Some instructions need post-processing to, for example, tweak which
2410 // encoding is selected. Loop on it while changes happen so the
2411 // individual transformations can chain off each other.
2412 if (!MatchingInlineAsm)
2413 while (processInstruction(Inst, Operands))
2417 if (!MatchingInlineAsm)
2418 Out.EmitInstruction(Inst);
2419 Opcode = Inst.getOpcode();
2421 case Match_MissingFeature: {
2422 assert(ErrorInfo && "Unknown missing feature!");
2423 // Special case the error message for the very common case where only
2424 // a single subtarget feature is missing.
2425 std::string Msg = "instruction requires:";
2427 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2428 if (ErrorInfo & Mask) {
2430 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
2434 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2436 case Match_InvalidOperand:
2437 WasOriginallyInvalidOperand = true;
2439 case Match_MnemonicFail:
2443 // FIXME: Ideally, we would only attempt suffix matches for things which are
2444 // valid prefixes, and we could just infer the right unambiguous
2445 // type. However, that requires substantially more matcher support than the
2448 // Change the operand to point to a temporary token.
2449 StringRef Base = Op->getToken();
2450 SmallString<16> Tmp;
2453 Op->setTokenValue(Tmp.str());
2455 // If this instruction starts with an 'f', then it is a floating point stack
2456 // instruction. These come in up to three forms for 32-bit, 64-bit, and
2457 // 80-bit floating point, which use the suffixes s,l,t respectively.
2459 // Otherwise, we assume that this may be an integer instruction, which comes
2460 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2461 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
2463 // Check for the various suffix matches.
2464 Tmp[Base.size()] = Suffixes[0];
2465 unsigned ErrorInfoIgnore;
2466 unsigned ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
2467 unsigned Match1, Match2, Match3, Match4;
2469 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2470 MatchingInlineAsm, isParsingIntelSyntax());
2471 // If this returned as a missing feature failure, remember that.
2472 if (Match1 == Match_MissingFeature)
2473 ErrorInfoMissingFeature = ErrorInfoIgnore;
2474 Tmp[Base.size()] = Suffixes[1];
2475 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2476 MatchingInlineAsm, isParsingIntelSyntax());
2477 // If this returned as a missing feature failure, remember that.
2478 if (Match2 == Match_MissingFeature)
2479 ErrorInfoMissingFeature = ErrorInfoIgnore;
2480 Tmp[Base.size()] = Suffixes[2];
2481 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2482 MatchingInlineAsm, isParsingIntelSyntax());
2483 // If this returned as a missing feature failure, remember that.
2484 if (Match3 == Match_MissingFeature)
2485 ErrorInfoMissingFeature = ErrorInfoIgnore;
2486 Tmp[Base.size()] = Suffixes[3];
2487 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2488 MatchingInlineAsm, isParsingIntelSyntax());
2489 // If this returned as a missing feature failure, remember that.
2490 if (Match4 == Match_MissingFeature)
2491 ErrorInfoMissingFeature = ErrorInfoIgnore;
2493 // Restore the old token.
2494 Op->setTokenValue(Base);
2496 // If exactly one matched, then we treat that as a successful match (and the
2497 // instruction will already have been filled in correctly, since the failing
2498 // matches won't have modified it).
2499 unsigned NumSuccessfulMatches =
2500 (Match1 == Match_Success) + (Match2 == Match_Success) +
2501 (Match3 == Match_Success) + (Match4 == Match_Success);
2502 if (NumSuccessfulMatches == 1) {
2504 if (!MatchingInlineAsm)
2505 Out.EmitInstruction(Inst);
2506 Opcode = Inst.getOpcode();
2510 // Otherwise, the match failed, try to produce a decent error message.
2512 // If we had multiple suffix matches, then identify this as an ambiguous
2514 if (NumSuccessfulMatches > 1) {
2516 unsigned NumMatches = 0;
2517 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
2518 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
2519 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
2520 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
2522 SmallString<126> Msg;
2523 raw_svector_ostream OS(Msg);
2524 OS << "ambiguous instructions require an explicit suffix (could be ";
2525 for (unsigned i = 0; i != NumMatches; ++i) {
2528 if (i + 1 == NumMatches)
2530 OS << "'" << Base << MatchChars[i] << "'";
2533 Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
2537 // Okay, we know that none of the variants matched successfully.
2539 // If all of the instructions reported an invalid mnemonic, then the original
2540 // mnemonic was invalid.
2541 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
2542 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
2543 if (!WasOriginallyInvalidOperand) {
2544 ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges :
2546 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
2547 Ranges, MatchingInlineAsm);
2550 // Recover location info for the operand if we know which was the problem.
2551 if (ErrorInfo != ~0U) {
2552 if (ErrorInfo >= Operands.size())
2553 return Error(IDLoc, "too few operands for instruction",
2554 EmptyRanges, MatchingInlineAsm);
2556 X86Operand *Operand = (X86Operand*)Operands[ErrorInfo];
2557 if (Operand->getStartLoc().isValid()) {
2558 SMRange OperandRange = Operand->getLocRange();
2559 return Error(Operand->getStartLoc(), "invalid operand for instruction",
2560 OperandRange, MatchingInlineAsm);
2564 return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2568 // If one instruction matched with a missing feature, report this as a
2570 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
2571 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
2572 std::string Msg = "instruction requires:";
2574 for (unsigned i = 0; i < (sizeof(ErrorInfoMissingFeature)*8-1); ++i) {
2575 if (ErrorInfoMissingFeature & Mask) {
2577 Msg += getSubtargetFeatureName(ErrorInfoMissingFeature & Mask);
2581 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2584 // If one instruction matched with an invalid operand, report this as an
2586 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
2587 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
2588 Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2593 // If all of these were an outright failure, report it in a useless way.
2594 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
2595 EmptyRanges, MatchingInlineAsm);
2600 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
2601 StringRef IDVal = DirectiveID.getIdentifier();
2602 if (IDVal == ".word")
2603 return ParseDirectiveWord(2, DirectiveID.getLoc());
2604 else if (IDVal.startswith(".code"))
2605 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
2606 else if (IDVal.startswith(".att_syntax")) {
2607 getParser().setAssemblerDialect(0);
2609 } else if (IDVal.startswith(".intel_syntax")) {
2610 getParser().setAssemblerDialect(1);
2611 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2612 if(Parser.getTok().getString() == "noprefix") {
2613 // FIXME : Handle noprefix
2623 /// ParseDirectiveWord
2624 /// ::= .word [ expression (, expression)* ]
2625 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2626 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2628 const MCExpr *Value;
2629 if (getParser().parseExpression(Value))
2632 getParser().getStreamer().EmitValue(Value, Size);
2634 if (getLexer().is(AsmToken::EndOfStatement))
2637 // FIXME: Improve diagnostic.
2638 if (getLexer().isNot(AsmToken::Comma))
2639 return Error(L, "unexpected token in directive");
2648 /// ParseDirectiveCode
2649 /// ::= .code32 | .code64
2650 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
2651 if (IDVal == ".code32") {
2653 if (is64BitMode()) {
2655 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2657 } else if (IDVal == ".code64") {
2659 if (!is64BitMode()) {
2661 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
2664 return Error(L, "unexpected directive " + IDVal);
2670 // Force static initialization.
2671 extern "C" void LLVMInitializeX86AsmParser() {
2672 RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
2673 RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
2676 #define GET_REGISTER_MATCHER
2677 #define GET_MATCHER_IMPLEMENTATION
2678 #define GET_SUBTARGET_FEATURE_NAME
2679 #include "X86GenAsmMatcher.inc"