1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "X86AsmInstrumentation.h"
12 #include "X86Operand.h"
13 #include "llvm/ADT/StringExtras.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/IR/Function.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstBuilder.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCTargetOptions.h"
24 #include "llvm/Support/CommandLine.h"
29 static cl::opt<bool> ClAsanInstrumentAssembly(
30 "asan-instrument-assembly",
31 cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
34 bool IsStackReg(unsigned Reg) {
35 return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
38 std::string FuncName(unsigned AccessSize, bool IsWrite) {
39 return std::string("__sanitizer_sanitize_") + (IsWrite ? "store" : "load") +
43 class X86AddressSanitizer : public X86AsmInstrumentation {
45 X86AddressSanitizer(const MCSubtargetInfo &STI) : STI(STI) {}
46 virtual ~X86AddressSanitizer() {}
48 // X86AsmInstrumentation implementation:
49 virtual void InstrumentInstruction(
50 const MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
51 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) override {
52 InstrumentMOV(Inst, Operands, Ctx, MII, Out);
55 // Should be implemented differently in x86_32 and x86_64 subclasses.
56 virtual void InstrumentMemOperandImpl(X86Operand *Op, unsigned AccessSize,
57 bool IsWrite, MCContext &Ctx,
60 void InstrumentMemOperand(MCParsedAsmOperand *Op, unsigned AccessSize,
61 bool IsWrite, MCContext &Ctx, MCStreamer &Out);
62 void InstrumentMOV(const MCInst &Inst,
63 SmallVectorImpl<MCParsedAsmOperand *> &Operands,
64 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
65 void EmitInstruction(MCStreamer &Out, const MCInst &Inst) {
66 Out.EmitInstruction(Inst, STI);
70 const MCSubtargetInfo &STI;
73 void X86AddressSanitizer::InstrumentMemOperand(
74 MCParsedAsmOperand *Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
76 assert(Op && Op->isMem() && "Op should be a memory operand.");
77 assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
78 "AccessSize should be a power of two, less or equal than 16.");
80 X86Operand *MemOp = static_cast<X86Operand *>(Op);
81 // FIXME: get rid of this limitation.
82 if (IsStackReg(MemOp->getMemBaseReg()) || IsStackReg(MemOp->getMemIndexReg()))
85 InstrumentMemOperandImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
88 void X86AddressSanitizer::InstrumentMOV(
89 const MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
90 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) {
91 // Access size in bytes.
92 unsigned AccessSize = 0;
94 switch (Inst.getOpcode()) {
125 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
126 for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
127 MCParsedAsmOperand *Op = Operands[Ix];
128 if (Op && Op->isMem())
129 InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
133 class X86AddressSanitizer32 : public X86AddressSanitizer {
135 X86AddressSanitizer32(const MCSubtargetInfo &STI)
136 : X86AddressSanitizer(STI) {}
137 virtual ~X86AddressSanitizer32() {}
139 virtual void InstrumentMemOperandImpl(X86Operand *Op, unsigned AccessSize,
140 bool IsWrite, MCContext &Ctx,
141 MCStreamer &Out) override;
144 void X86AddressSanitizer32::InstrumentMemOperandImpl(
145 X86Operand *Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
147 // FIXME: emit .cfi directives for correct stack unwinding.
148 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
151 Inst.setOpcode(X86::LEA32r);
152 Inst.addOperand(MCOperand::CreateReg(X86::EAX));
153 Op->addMemOperands(Inst, 5);
154 EmitInstruction(Out, Inst);
156 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
158 const std::string Func = FuncName(AccessSize, IsWrite);
159 const MCSymbol *FuncSym = Ctx.GetOrCreateSymbol(StringRef(Func));
160 const MCSymbolRefExpr *FuncExpr =
161 MCSymbolRefExpr::Create(FuncSym, MCSymbolRefExpr::VK_PLT, Ctx);
162 EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FuncExpr));
164 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri).addReg(X86::ESP)
165 .addReg(X86::ESP).addImm(4));
166 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
169 class X86AddressSanitizer64 : public X86AddressSanitizer {
171 X86AddressSanitizer64(const MCSubtargetInfo &STI)
172 : X86AddressSanitizer(STI) {}
173 virtual ~X86AddressSanitizer64() {}
175 virtual void InstrumentMemOperandImpl(X86Operand *Op, unsigned AccessSize,
176 bool IsWrite, MCContext &Ctx,
177 MCStreamer &Out) override;
180 void X86AddressSanitizer64::InstrumentMemOperandImpl(X86Operand *Op,
185 // FIXME: emit .cfi directives for correct stack unwinding.
187 // Set %rsp below current red zone (128 bytes wide) using LEA instruction to
191 Inst.setOpcode(X86::LEA64r);
192 Inst.addOperand(MCOperand::CreateReg(X86::RSP));
194 const MCExpr *Disp = MCConstantExpr::Create(-128, Ctx);
196 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc());
197 Op->addMemOperands(Inst, 5);
198 EmitInstruction(Out, Inst);
200 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RDI));
203 Inst.setOpcode(X86::LEA64r);
204 Inst.addOperand(MCOperand::CreateReg(X86::RDI));
205 Op->addMemOperands(Inst, 5);
206 EmitInstruction(Out, Inst);
209 const std::string Func = FuncName(AccessSize, IsWrite);
210 const MCSymbol *FuncSym = Ctx.GetOrCreateSymbol(StringRef(Func));
211 const MCSymbolRefExpr *FuncExpr =
212 MCSymbolRefExpr::Create(FuncSym, MCSymbolRefExpr::VK_PLT, Ctx);
213 EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FuncExpr));
215 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RDI));
217 // Restore old %rsp value.
220 Inst.setOpcode(X86::LEA64r);
221 Inst.addOperand(MCOperand::CreateReg(X86::RSP));
223 const MCExpr *Disp = MCConstantExpr::Create(128, Ctx);
225 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc());
226 Op->addMemOperands(Inst, 5);
227 EmitInstruction(Out, Inst);
231 } // End anonymous namespace
233 X86AsmInstrumentation::X86AsmInstrumentation() {}
234 X86AsmInstrumentation::~X86AsmInstrumentation() {}
236 void X86AsmInstrumentation::InstrumentInstruction(
237 const MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
238 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) {}
240 X86AsmInstrumentation *
241 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
242 const MCContext &Ctx, const MCSubtargetInfo &STI) {
243 Triple T(STI.getTargetTriple());
244 const bool hasCompilerRTSupport = T.isOSLinux();
245 if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
246 MCOptions.SanitizeAddress) {
247 if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
248 return new X86AddressSanitizer32(STI);
249 if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
250 return new X86AddressSanitizer64(STI);
252 return new X86AsmInstrumentation();
255 } // End llvm namespace