1 // WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*-
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief WebAssembly Memory operand code-gen constructs.
13 //===----------------------------------------------------------------------===//
17 // - WebAssemblyTargetLowering::isLegalAddressingMode
18 // - WebAssemblyTargetLowering having to do with atomics
19 // - Each has optional alignment and immediate byte offset.
21 // WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
22 // local types. These memory-only types instead zero- or sign-extend into local
23 // types when loading, and truncate when storing.
26 def LOAD_I32 : I<(outs I32:$dst), (ins I32:$addr),
27 [(set I32:$dst, (load I32:$addr))]>;
28 def LOAD_I64 : I<(outs I64:$dst), (ins I32:$addr),
29 [(set I64:$dst, (load I32:$addr))]>;
30 def LOAD_F32 : I<(outs F32:$dst), (ins I32:$addr),
31 [(set F32:$dst, (load I32:$addr))]>;
32 def LOAD_F64 : I<(outs F64:$dst), (ins I32:$addr),
33 [(set F64:$dst, (load I32:$addr))]>;
36 def LOAD8_S_I32 : I<(outs I32:$dst), (ins I32:$addr),
37 [(set I32:$dst, (sextloadi8 I32:$addr))]>;
38 def LOAD8_U_I32 : I<(outs I32:$dst), (ins I32:$addr),
39 [(set I32:$dst, (zextloadi8 I32:$addr))]>;
40 def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$addr),
41 [(set I32:$dst, (sextloadi16 I32:$addr))]>;
42 def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$addr),
43 [(set I32:$dst, (zextloadi16 I32:$addr))]>;
44 def LOAD8_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
45 [(set I64:$dst, (sextloadi8 I32:$addr))]>;
46 def LOAD8_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
47 [(set I64:$dst, (zextloadi8 I32:$addr))]>;
48 def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
49 [(set I64:$dst, (sextloadi16 I32:$addr))]>;
50 def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
51 [(set I64:$dst, (zextloadi16 I32:$addr))]>;
52 def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
53 [(set I64:$dst, (sextloadi32 I32:$addr))]>;
54 def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
55 [(set I64:$dst, (zextloadi32 I32:$addr))]>;
57 // "Don't care" extending load become zero-extending load.
58 def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD8_U_I32 $addr)>;
59 def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 $addr)>;
60 def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD8_U_I64 $addr)>;
61 def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 $addr)>;
62 def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 $addr)>;
65 // Note: WebAssembly inverts SelectionDAG's usual operand order.
66 def STORE_I32 : I<(outs), (ins I32:$addr, I32:$val),
67 [(store i32:$val, I32:$addr)]>;
68 def STORE_I64 : I<(outs), (ins I32:$addr, I64:$val),
69 [(store i64:$val, I32:$addr)]>;
70 def STORE_F32 : I<(outs), (ins I32:$addr, F32:$val),
71 [(store f32:$val, I32:$addr)]>;
72 def STORE_F64 : I<(outs), (ins I32:$addr, F64:$val),
73 [(store f64:$val, I32:$addr)]>;
76 def STORE8_I32 : I<(outs), (ins I32:$addr, I32:$val),
77 [(truncstorei8 I32:$val, I32:$addr)]>;
78 def STORE16_I32 : I<(outs), (ins I32:$addr, I32:$val),
79 [(truncstorei16 I32:$val, I32:$addr)]>;
80 def STORE8_I64 : I<(outs), (ins I32:$addr, I64:$val),
81 [(truncstorei8 I64:$val, I32:$addr)]>;
82 def STORE16_I64 : I<(outs), (ins I32:$addr, I64:$val),
83 [(truncstorei16 I64:$val, I32:$addr)]>;
84 def STORE32_I64 : I<(outs), (ins I32:$addr, I64:$val),
85 [(truncstorei32 I64:$val, I32:$addr)]>;
88 def memory_size_I32 : I<(outs I32:$dst), (ins),
89 [(set I32:$dst, (int_wasm_memory_size))]>,
90 Requires<[HasAddr32]>;
91 def memory_size_I64 : I<(outs I64:$dst), (ins),
92 [(set I64:$dst, (int_wasm_memory_size))]>,
93 Requires<[HasAddr64]>;
96 def grow_memory_I32 : I<(outs), (ins I32:$delta),
97 [(int_wasm_grow_memory I32:$delta)]>,
98 Requires<[HasAddr32]>;
99 def grow_memory_I64 : I<(outs), (ins I64:$delta),
100 [(int_wasm_grow_memory I64:$delta)]>,
101 Requires<[HasAddr64]>;