1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZISelLowering.h"
15 #include "SystemZCallingConv.h"
16 #include "SystemZConstantPoolValue.h"
17 #include "SystemZMachineFunctionInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #define DEBUG_TYPE "systemz-lower"
30 // Represents a sequence for extracting a 0/1 value from an IPM result:
31 // (((X ^ XORValue) + AddValue) >> Bit)
32 struct IPMConversion {
33 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
34 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
41 // Represents information about a comparison.
43 Comparison(SDValue Op0In, SDValue Op1In)
44 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
46 // The operands to the comparison.
49 // The opcode that should be used to compare Op0 and Op1.
52 // A SystemZICMP value. Only used for integer comparisons.
55 // The mask of CC values that Opcode can produce.
58 // The mask of CC values for which the original condition is true.
61 } // end anonymous namespace
63 // Classify VT as either 32 or 64 bit.
64 static bool is32Bit(EVT VT) {
65 switch (VT.getSimpleVT().SimpleTy) {
71 llvm_unreachable("Unsupported type");
75 // Return a version of MachineOperand that can be safely used before the
77 static MachineOperand earlyUseOperand(MachineOperand Op) {
83 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm)
84 : TargetLowering(tm, new TargetLoweringObjectFileELF()),
85 Subtarget(tm.getSubtarget<SystemZSubtarget>()) {
86 MVT PtrVT = getPointerTy();
88 // Set up the register classes.
89 if (Subtarget.hasHighWord())
90 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
92 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
93 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
94 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
95 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
96 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
98 // Compute derived properties from the register classes
99 computeRegisterProperties();
101 // Set up special registers.
102 setExceptionPointerRegister(SystemZ::R6D);
103 setExceptionSelectorRegister(SystemZ::R7D);
104 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
106 // TODO: It may be better to default to latency-oriented scheduling, however
107 // LLVM's current latency-oriented scheduler can't handle physreg definitions
108 // such as SystemZ has with CC, so set this to the register-pressure
109 // scheduler, because it can.
110 setSchedulingPreference(Sched::RegPressure);
112 setBooleanContents(ZeroOrOneBooleanContent);
113 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
115 // Instructions are strings of 2-byte aligned 2-byte values.
116 setMinFunctionAlignment(2);
118 // Handle operations that are handled in a similar way for all types.
119 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
120 I <= MVT::LAST_FP_VALUETYPE;
122 MVT VT = MVT::SimpleValueType(I);
123 if (isTypeLegal(VT)) {
124 // Lower SET_CC into an IPM-based sequence.
125 setOperationAction(ISD::SETCC, VT, Custom);
127 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
128 setOperationAction(ISD::SELECT, VT, Expand);
130 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
131 setOperationAction(ISD::SELECT_CC, VT, Custom);
132 setOperationAction(ISD::BR_CC, VT, Custom);
136 // Expand jump table branches as address arithmetic followed by an
138 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
140 // Expand BRCOND into a BR_CC (see above).
141 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
143 // Handle integer types.
144 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
145 I <= MVT::LAST_INTEGER_VALUETYPE;
147 MVT VT = MVT::SimpleValueType(I);
148 if (isTypeLegal(VT)) {
149 // Expand individual DIV and REMs into DIVREMs.
150 setOperationAction(ISD::SDIV, VT, Expand);
151 setOperationAction(ISD::UDIV, VT, Expand);
152 setOperationAction(ISD::SREM, VT, Expand);
153 setOperationAction(ISD::UREM, VT, Expand);
154 setOperationAction(ISD::SDIVREM, VT, Custom);
155 setOperationAction(ISD::UDIVREM, VT, Custom);
157 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
158 // stores, putting a serialization instruction after the stores.
159 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
160 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
162 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
163 // available, or if the operand is constant.
164 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
166 // No special instructions for these.
167 setOperationAction(ISD::CTPOP, VT, Expand);
168 setOperationAction(ISD::CTTZ, VT, Expand);
169 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
170 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
171 setOperationAction(ISD::ROTR, VT, Expand);
173 // Use *MUL_LOHI where possible instead of MULH*.
174 setOperationAction(ISD::MULHS, VT, Expand);
175 setOperationAction(ISD::MULHU, VT, Expand);
176 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
177 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
179 // Only z196 and above have native support for conversions to unsigned.
180 if (!Subtarget.hasFPExtension())
181 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
185 // Type legalization will convert 8- and 16-bit atomic operations into
186 // forms that operate on i32s (but still keeping the original memory VT).
187 // Lower them into full i32 operations.
188 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
189 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
190 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
191 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
192 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
193 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
194 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
195 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
196 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
197 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
198 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
199 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
201 // z10 has instructions for signed but not unsigned FP conversion.
202 // Handle unsigned 32-bit types as signed 64-bit types.
203 if (!Subtarget.hasFPExtension()) {
204 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
205 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
208 // We have native support for a 64-bit CTLZ, via FLOGR.
209 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
210 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
212 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
213 setOperationAction(ISD::OR, MVT::i64, Custom);
215 // FIXME: Can we support these natively?
216 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
217 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
218 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
220 // We have native instructions for i8, i16 and i32 extensions, but not i1.
221 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
223 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
224 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
226 // Handle the various types of symbolic address.
227 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
228 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
229 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
230 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
231 setOperationAction(ISD::JumpTable, PtrVT, Custom);
233 // We need to handle dynamic allocations specially because of the
234 // 160-byte area at the bottom of the stack.
235 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
237 // Use custom expanders so that we can force the function to use
239 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
240 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
242 // Handle prefetches with PFD or PFDRL.
243 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
245 // Handle floating-point types.
246 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
247 I <= MVT::LAST_FP_VALUETYPE;
249 MVT VT = MVT::SimpleValueType(I);
250 if (isTypeLegal(VT)) {
251 // We can use FI for FRINT.
252 setOperationAction(ISD::FRINT, VT, Legal);
254 // We can use the extended form of FI for other rounding operations.
255 if (Subtarget.hasFPExtension()) {
256 setOperationAction(ISD::FNEARBYINT, VT, Legal);
257 setOperationAction(ISD::FFLOOR, VT, Legal);
258 setOperationAction(ISD::FCEIL, VT, Legal);
259 setOperationAction(ISD::FTRUNC, VT, Legal);
260 setOperationAction(ISD::FROUND, VT, Legal);
263 // No special instructions for these.
264 setOperationAction(ISD::FSIN, VT, Expand);
265 setOperationAction(ISD::FCOS, VT, Expand);
266 setOperationAction(ISD::FREM, VT, Expand);
270 // We have fused multiply-addition for f32 and f64 but not f128.
271 setOperationAction(ISD::FMA, MVT::f32, Legal);
272 setOperationAction(ISD::FMA, MVT::f64, Legal);
273 setOperationAction(ISD::FMA, MVT::f128, Expand);
275 // Needed so that we don't try to implement f128 constant loads using
276 // a load-and-extend of a f80 constant (in cases where the constant
277 // would fit in an f80).
278 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
280 // Floating-point truncation and stores need to be done separately.
281 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
282 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
283 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
285 // We have 64-bit FPR<->GPR moves, but need special handling for
287 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
288 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
290 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
291 // structure, but VAEND is a no-op.
292 setOperationAction(ISD::VASTART, MVT::Other, Custom);
293 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
294 setOperationAction(ISD::VAEND, MVT::Other, Expand);
296 // Codes for which we want to perform some z-specific combinations.
297 setTargetDAGCombine(ISD::SIGN_EXTEND);
299 // We want to use MVC in preference to even a single load/store pair.
300 MaxStoresPerMemcpy = 0;
301 MaxStoresPerMemcpyOptSize = 0;
303 // The main memset sequence is a byte store followed by an MVC.
304 // Two STC or MV..I stores win over that, but the kind of fused stores
305 // generated by target-independent code don't when the byte value is
306 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
307 // than "STC;MVC". Handle the choice in target-specific code instead.
308 MaxStoresPerMemset = 0;
309 MaxStoresPerMemsetOptSize = 0;
312 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
315 return VT.changeVectorElementTypeToInteger();
318 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
319 VT = VT.getScalarType();
324 switch (VT.getSimpleVT().SimpleTy) {
337 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
338 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
339 return Imm.isZero() || Imm.isNegZero();
342 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
345 // Unaligned accesses should never be slower than the expanded version.
346 // We check specifically for aligned accesses in the few cases where
347 // they are required.
353 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
355 // Punt on globals for now, although they can be used in limited
356 // RELATIVE LONG cases.
360 // Require a 20-bit signed offset.
361 if (!isInt<20>(AM.BaseOffs))
364 // Indexing is OK but no scale factor can be applied.
365 return AM.Scale == 0 || AM.Scale == 1;
368 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
369 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
371 unsigned FromBits = FromType->getPrimitiveSizeInBits();
372 unsigned ToBits = ToType->getPrimitiveSizeInBits();
373 return FromBits > ToBits;
376 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
377 if (!FromVT.isInteger() || !ToVT.isInteger())
379 unsigned FromBits = FromVT.getSizeInBits();
380 unsigned ToBits = ToVT.getSizeInBits();
381 return FromBits > ToBits;
384 //===----------------------------------------------------------------------===//
385 // Inline asm support
386 //===----------------------------------------------------------------------===//
388 TargetLowering::ConstraintType
389 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
390 if (Constraint.size() == 1) {
391 switch (Constraint[0]) {
392 case 'a': // Address register
393 case 'd': // Data register (equivalent to 'r')
394 case 'f': // Floating-point register
395 case 'h': // High-part register
396 case 'r': // General-purpose register
397 return C_RegisterClass;
399 case 'Q': // Memory with base and unsigned 12-bit displacement
400 case 'R': // Likewise, plus an index
401 case 'S': // Memory with base and signed 20-bit displacement
402 case 'T': // Likewise, plus an index
403 case 'm': // Equivalent to 'T'.
406 case 'I': // Unsigned 8-bit constant
407 case 'J': // Unsigned 12-bit constant
408 case 'K': // Signed 16-bit constant
409 case 'L': // Signed 20-bit displacement (on all targets we support)
410 case 'M': // 0x7fffffff
417 return TargetLowering::getConstraintType(Constraint);
420 TargetLowering::ConstraintWeight SystemZTargetLowering::
421 getSingleConstraintMatchWeight(AsmOperandInfo &info,
422 const char *constraint) const {
423 ConstraintWeight weight = CW_Invalid;
424 Value *CallOperandVal = info.CallOperandVal;
425 // If we don't have a value, we can't do a match,
426 // but allow it at the lowest weight.
429 Type *type = CallOperandVal->getType();
430 // Look at the constraint type.
431 switch (*constraint) {
433 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
436 case 'a': // Address register
437 case 'd': // Data register (equivalent to 'r')
438 case 'h': // High-part register
439 case 'r': // General-purpose register
440 if (CallOperandVal->getType()->isIntegerTy())
441 weight = CW_Register;
444 case 'f': // Floating-point register
445 if (type->isFloatingPointTy())
446 weight = CW_Register;
449 case 'I': // Unsigned 8-bit constant
450 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
451 if (isUInt<8>(C->getZExtValue()))
452 weight = CW_Constant;
455 case 'J': // Unsigned 12-bit constant
456 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
457 if (isUInt<12>(C->getZExtValue()))
458 weight = CW_Constant;
461 case 'K': // Signed 16-bit constant
462 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
463 if (isInt<16>(C->getSExtValue()))
464 weight = CW_Constant;
467 case 'L': // Signed 20-bit displacement (on all targets we support)
468 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
469 if (isInt<20>(C->getSExtValue()))
470 weight = CW_Constant;
473 case 'M': // 0x7fffffff
474 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
475 if (C->getZExtValue() == 0x7fffffff)
476 weight = CW_Constant;
482 // Parse a "{tNNN}" register constraint for which the register type "t"
483 // has already been verified. MC is the class associated with "t" and
484 // Map maps 0-based register numbers to LLVM register numbers.
485 static std::pair<unsigned, const TargetRegisterClass *>
486 parseRegisterNumber(const std::string &Constraint,
487 const TargetRegisterClass *RC, const unsigned *Map) {
488 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
489 if (isdigit(Constraint[2])) {
490 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
491 unsigned Index = atoi(Suffix.c_str());
492 if (Index < 16 && Map[Index])
493 return std::make_pair(Map[Index], RC);
495 return std::make_pair(0U, nullptr);
498 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
499 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
500 if (Constraint.size() == 1) {
501 // GCC Constraint Letters
502 switch (Constraint[0]) {
504 case 'd': // Data register (equivalent to 'r')
505 case 'r': // General-purpose register
507 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
508 else if (VT == MVT::i128)
509 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
510 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
512 case 'a': // Address register
514 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
515 else if (VT == MVT::i128)
516 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
517 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
519 case 'h': // High-part register (an LLVM extension)
520 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
522 case 'f': // Floating-point register
524 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
525 else if (VT == MVT::f128)
526 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
527 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
530 if (Constraint[0] == '{') {
531 // We need to override the default register parsing for GPRs and FPRs
532 // because the interpretation depends on VT. The internal names of
533 // the registers are also different from the external names
534 // (F0D and F0S instead of F0, etc.).
535 if (Constraint[1] == 'r') {
537 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
538 SystemZMC::GR32Regs);
540 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
541 SystemZMC::GR128Regs);
542 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
543 SystemZMC::GR64Regs);
545 if (Constraint[1] == 'f') {
547 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
548 SystemZMC::FP32Regs);
550 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
551 SystemZMC::FP128Regs);
552 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
553 SystemZMC::FP64Regs);
556 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
559 void SystemZTargetLowering::
560 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
561 std::vector<SDValue> &Ops,
562 SelectionDAG &DAG) const {
563 // Only support length 1 constraints for now.
564 if (Constraint.length() == 1) {
565 switch (Constraint[0]) {
566 case 'I': // Unsigned 8-bit constant
567 if (auto *C = dyn_cast<ConstantSDNode>(Op))
568 if (isUInt<8>(C->getZExtValue()))
569 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
573 case 'J': // Unsigned 12-bit constant
574 if (auto *C = dyn_cast<ConstantSDNode>(Op))
575 if (isUInt<12>(C->getZExtValue()))
576 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
580 case 'K': // Signed 16-bit constant
581 if (auto *C = dyn_cast<ConstantSDNode>(Op))
582 if (isInt<16>(C->getSExtValue()))
583 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
587 case 'L': // Signed 20-bit displacement (on all targets we support)
588 if (auto *C = dyn_cast<ConstantSDNode>(Op))
589 if (isInt<20>(C->getSExtValue()))
590 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
594 case 'M': // 0x7fffffff
595 if (auto *C = dyn_cast<ConstantSDNode>(Op))
596 if (C->getZExtValue() == 0x7fffffff)
597 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
602 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
605 //===----------------------------------------------------------------------===//
606 // Calling conventions
607 //===----------------------------------------------------------------------===//
609 #include "SystemZGenCallingConv.inc"
611 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
612 Type *ToType) const {
613 return isTruncateFree(FromType, ToType);
616 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
617 if (!CI->isTailCall())
622 // Value is a value that has been passed to us in the location described by VA
623 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
624 // any loads onto Chain.
625 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
626 CCValAssign &VA, SDValue Chain,
628 // If the argument has been promoted from a smaller type, insert an
629 // assertion to capture this.
630 if (VA.getLocInfo() == CCValAssign::SExt)
631 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
632 DAG.getValueType(VA.getValVT()));
633 else if (VA.getLocInfo() == CCValAssign::ZExt)
634 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
635 DAG.getValueType(VA.getValVT()));
638 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
639 else if (VA.getLocInfo() == CCValAssign::Indirect)
640 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
641 MachinePointerInfo(), false, false, false, 0);
643 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
647 // Value is a value of type VA.getValVT() that we need to copy into
648 // the location described by VA. Return a copy of Value converted to
649 // VA.getValVT(). The caller is responsible for handling indirect values.
650 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
651 CCValAssign &VA, SDValue Value) {
652 switch (VA.getLocInfo()) {
653 case CCValAssign::SExt:
654 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
655 case CCValAssign::ZExt:
656 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
657 case CCValAssign::AExt:
658 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
659 case CCValAssign::Full:
662 llvm_unreachable("Unhandled getLocInfo()");
666 SDValue SystemZTargetLowering::
667 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
668 const SmallVectorImpl<ISD::InputArg> &Ins,
669 SDLoc DL, SelectionDAG &DAG,
670 SmallVectorImpl<SDValue> &InVals) const {
671 MachineFunction &MF = DAG.getMachineFunction();
672 MachineFrameInfo *MFI = MF.getFrameInfo();
673 MachineRegisterInfo &MRI = MF.getRegInfo();
674 SystemZMachineFunctionInfo *FuncInfo =
675 MF.getInfo<SystemZMachineFunctionInfo>();
676 auto *TFL = static_cast<const SystemZFrameLowering *>(
677 DAG.getTarget().getFrameLowering());
679 // Assign locations to all of the incoming arguments.
680 SmallVector<CCValAssign, 16> ArgLocs;
681 CCState CCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
683 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
685 unsigned NumFixedGPRs = 0;
686 unsigned NumFixedFPRs = 0;
687 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
689 CCValAssign &VA = ArgLocs[I];
690 EVT LocVT = VA.getLocVT();
692 // Arguments passed in registers
693 const TargetRegisterClass *RC;
694 switch (LocVT.getSimpleVT().SimpleTy) {
696 // Integers smaller than i64 should be promoted to i64.
697 llvm_unreachable("Unexpected argument type");
700 RC = &SystemZ::GR32BitRegClass;
704 RC = &SystemZ::GR64BitRegClass;
708 RC = &SystemZ::FP32BitRegClass;
712 RC = &SystemZ::FP64BitRegClass;
716 unsigned VReg = MRI.createVirtualRegister(RC);
717 MRI.addLiveIn(VA.getLocReg(), VReg);
718 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
720 assert(VA.isMemLoc() && "Argument not register or memory");
722 // Create the frame index object for this incoming parameter.
723 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
724 VA.getLocMemOffset(), true);
726 // Create the SelectionDAG nodes corresponding to a load
727 // from this parameter. Unpromoted ints and floats are
728 // passed as right-justified 8-byte values.
729 EVT PtrVT = getPointerTy();
730 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
731 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
732 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
733 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
734 MachinePointerInfo::getFixedStack(FI),
735 false, false, false, 0);
738 // Convert the value of the argument register into the value that's
740 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
744 // Save the number of non-varargs registers for later use by va_start, etc.
745 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
746 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
748 // Likewise the address (in the form of a frame index) of where the
749 // first stack vararg would be. The 1-byte size here is arbitrary.
750 int64_t StackSize = CCInfo.getNextStackOffset();
751 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
753 // ...and a similar frame index for the caller-allocated save area
754 // that will be used to store the incoming registers.
755 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
756 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
757 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
759 // Store the FPR varargs in the reserved frame slots. (We store the
760 // GPRs as part of the prologue.)
761 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
762 SDValue MemOps[SystemZ::NumArgFPRs];
763 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
764 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
765 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
766 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
767 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
768 &SystemZ::FP64BitRegClass);
769 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
770 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
771 MachinePointerInfo::getFixedStack(FI),
775 // Join the stores, which are independent of one another.
776 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
777 makeArrayRef(&MemOps[NumFixedFPRs],
778 SystemZ::NumArgFPRs-NumFixedFPRs));
785 static bool canUseSiblingCall(CCState ArgCCInfo,
786 SmallVectorImpl<CCValAssign> &ArgLocs) {
787 // Punt if there are any indirect or stack arguments, or if the call
788 // needs the call-saved argument register R6.
789 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
790 CCValAssign &VA = ArgLocs[I];
791 if (VA.getLocInfo() == CCValAssign::Indirect)
795 unsigned Reg = VA.getLocReg();
796 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
803 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
804 SmallVectorImpl<SDValue> &InVals) const {
805 SelectionDAG &DAG = CLI.DAG;
807 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
808 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
809 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
810 SDValue Chain = CLI.Chain;
811 SDValue Callee = CLI.Callee;
812 bool &IsTailCall = CLI.IsTailCall;
813 CallingConv::ID CallConv = CLI.CallConv;
814 bool IsVarArg = CLI.IsVarArg;
815 MachineFunction &MF = DAG.getMachineFunction();
816 EVT PtrVT = getPointerTy();
818 // Analyze the operands of the call, assigning locations to each operand.
819 SmallVector<CCValAssign, 16> ArgLocs;
820 CCState ArgCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
822 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
824 // We don't support GuaranteedTailCallOpt, only automatically-detected
826 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
829 // Get a count of how many bytes are to be pushed on the stack.
830 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
832 // Mark the start of the call.
834 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
837 // Copy argument values to their designated locations.
838 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
839 SmallVector<SDValue, 8> MemOpChains;
841 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
842 CCValAssign &VA = ArgLocs[I];
843 SDValue ArgValue = OutVals[I];
845 if (VA.getLocInfo() == CCValAssign::Indirect) {
846 // Store the argument in a stack slot and pass its address.
847 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
848 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
849 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
850 MachinePointerInfo::getFixedStack(FI),
852 ArgValue = SpillSlot;
854 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
857 // Queue up the argument copies and emit them at the end.
858 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
860 assert(VA.isMemLoc() && "Argument not register or memory");
862 // Work out the address of the stack slot. Unpromoted ints and
863 // floats are passed as right-justified 8-byte values.
864 if (!StackPtr.getNode())
865 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
866 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
867 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
869 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
870 DAG.getIntPtrConstant(Offset));
873 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
874 MachinePointerInfo(),
879 // Join the stores, which are independent of one another.
880 if (!MemOpChains.empty())
881 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
883 // Accept direct calls by converting symbolic call addresses to the
884 // associated Target* opcodes. Force %r1 to be used for indirect
887 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
888 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
889 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
890 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
891 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
892 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
893 } else if (IsTailCall) {
894 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
895 Glue = Chain.getValue(1);
896 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
899 // Build a sequence of copy-to-reg nodes, chained and glued together.
900 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
901 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
902 RegsToPass[I].second, Glue);
903 Glue = Chain.getValue(1);
906 // The first call operand is the chain and the second is the target address.
907 SmallVector<SDValue, 8> Ops;
908 Ops.push_back(Chain);
909 Ops.push_back(Callee);
911 // Add argument registers to the end of the list so that they are
912 // known live into the call.
913 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
914 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
915 RegsToPass[I].second.getValueType()));
917 // Glue the call to the argument copies, if any.
922 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
924 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
925 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
926 Glue = Chain.getValue(1);
928 // Mark the end of the call, which is glued to the call itself.
929 Chain = DAG.getCALLSEQ_END(Chain,
930 DAG.getConstant(NumBytes, PtrVT, true),
931 DAG.getConstant(0, PtrVT, true),
933 Glue = Chain.getValue(1);
935 // Assign locations to each value returned by this call.
936 SmallVector<CCValAssign, 16> RetLocs;
937 CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
939 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
941 // Copy all of the result registers out of their specified physreg.
942 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
943 CCValAssign &VA = RetLocs[I];
945 // Copy the value out, gluing the copy to the end of the call sequence.
946 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
947 VA.getLocVT(), Glue);
948 Chain = RetValue.getValue(1);
949 Glue = RetValue.getValue(2);
951 // Convert the value of the return register into the value that's
953 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
960 SystemZTargetLowering::LowerReturn(SDValue Chain,
961 CallingConv::ID CallConv, bool IsVarArg,
962 const SmallVectorImpl<ISD::OutputArg> &Outs,
963 const SmallVectorImpl<SDValue> &OutVals,
964 SDLoc DL, SelectionDAG &DAG) const {
965 MachineFunction &MF = DAG.getMachineFunction();
967 // Assign locations to each returned value.
968 SmallVector<CCValAssign, 16> RetLocs;
969 CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
971 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
973 // Quick exit for void returns
975 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
977 // Copy the result values into the output registers.
979 SmallVector<SDValue, 4> RetOps;
980 RetOps.push_back(Chain);
981 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
982 CCValAssign &VA = RetLocs[I];
983 SDValue RetValue = OutVals[I];
985 // Make the return register live on exit.
986 assert(VA.isRegLoc() && "Can only return in registers!");
988 // Promote the value as required.
989 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
991 // Chain and glue the copies together.
992 unsigned Reg = VA.getLocReg();
993 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
994 Glue = Chain.getValue(1);
995 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
998 // Update chain and glue.
1001 RetOps.push_back(Glue);
1003 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1006 SDValue SystemZTargetLowering::
1007 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
1008 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
1011 // CC is a comparison that will be implemented using an integer or
1012 // floating-point comparison. Return the condition code mask for
1013 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1014 // unsigned comparisons and clear for signed ones. In the floating-point
1015 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1016 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1018 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1019 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1020 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1024 llvm_unreachable("Invalid integer condition!");
1033 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1034 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1039 // Return a sequence for getting a 1 from an IPM result when CC has a
1040 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1041 // The handling of CC values outside CCValid doesn't matter.
1042 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1043 // Deal with cases where the result can be taken directly from a bit
1044 // of the IPM result.
1045 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1046 return IPMConversion(0, 0, SystemZ::IPM_CC);
1047 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1048 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1050 // Deal with cases where we can add a value to force the sign bit
1051 // to contain the right value. Putting the bit in 31 means we can
1052 // use SRL rather than RISBG(L), and also makes it easier to get a
1053 // 0/-1 value, so it has priority over the other tests below.
1055 // These sequences rely on the fact that the upper two bits of the
1056 // IPM result are zero.
1057 uint64_t TopBit = uint64_t(1) << 31;
1058 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1059 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1060 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1061 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1062 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1064 | SystemZ::CCMASK_2)))
1065 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1066 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1067 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1068 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1070 | SystemZ::CCMASK_3)))
1071 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1073 // Next try inverting the value and testing a bit. 0/1 could be
1074 // handled this way too, but we dealt with that case above.
1075 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1076 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1078 // Handle cases where adding a value forces a non-sign bit to contain
1080 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1081 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1082 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1083 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1085 // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are
1086 // can be done by inverting the low CC bit and applying one of the
1087 // sign-based extractions above.
1088 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1089 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1090 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1091 return IPMConversion(1 << SystemZ::IPM_CC,
1092 TopBit - (3 << SystemZ::IPM_CC), 31);
1093 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1095 | SystemZ::CCMASK_3)))
1096 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1097 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1099 | SystemZ::CCMASK_3)))
1100 return IPMConversion(1 << SystemZ::IPM_CC,
1101 TopBit - (1 << SystemZ::IPM_CC), 31);
1103 llvm_unreachable("Unexpected CC combination");
1106 // If C can be converted to a comparison against zero, adjust the operands
1108 static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {
1109 if (C.ICmpType == SystemZICMP::UnsignedOnly)
1112 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1116 int64_t Value = ConstOp1->getSExtValue();
1117 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1118 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1119 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1120 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1121 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1122 C.Op1 = DAG.getConstant(0, C.Op1.getValueType());
1126 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1127 // adjust the operands as necessary.
1128 static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {
1129 // For us to make any changes, it must a comparison between a single-use
1130 // load and a constant.
1131 if (!C.Op0.hasOneUse() ||
1132 C.Op0.getOpcode() != ISD::LOAD ||
1133 C.Op1.getOpcode() != ISD::Constant)
1136 // We must have an 8- or 16-bit load.
1137 auto *Load = cast<LoadSDNode>(C.Op0);
1138 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1139 if (NumBits != 8 && NumBits != 16)
1142 // The load must be an extending one and the constant must be within the
1143 // range of the unextended value.
1144 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1145 uint64_t Value = ConstOp1->getZExtValue();
1146 uint64_t Mask = (1 << NumBits) - 1;
1147 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1148 // Make sure that ConstOp1 is in range of C.Op0.
1149 int64_t SignedValue = ConstOp1->getSExtValue();
1150 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1152 if (C.ICmpType != SystemZICMP::SignedOnly) {
1153 // Unsigned comparison between two sign-extended values is equivalent
1154 // to unsigned comparison between two zero-extended values.
1156 } else if (NumBits == 8) {
1157 // Try to treat the comparison as unsigned, so that we can use CLI.
1158 // Adjust CCMask and Value as necessary.
1159 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1160 // Test whether the high bit of the byte is set.
1161 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1162 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1163 // Test whether the high bit of the byte is clear.
1164 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1166 // No instruction exists for this combination.
1168 C.ICmpType = SystemZICMP::UnsignedOnly;
1170 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1173 assert(C.ICmpType == SystemZICMP::Any &&
1174 "Signedness shouldn't matter here.");
1178 // Make sure that the first operand is an i32 of the right extension type.
1179 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1182 if (C.Op0.getValueType() != MVT::i32 ||
1183 Load->getExtensionType() != ExtType)
1184 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1185 Load->getChain(), Load->getBasePtr(),
1186 Load->getPointerInfo(), Load->getMemoryVT(),
1187 Load->isVolatile(), Load->isNonTemporal(),
1188 Load->getAlignment());
1190 // Make sure that the second operand is an i32 with the right value.
1191 if (C.Op1.getValueType() != MVT::i32 ||
1192 Value != ConstOp1->getZExtValue())
1193 C.Op1 = DAG.getConstant(Value, MVT::i32);
1196 // Return true if Op is either an unextended load, or a load suitable
1197 // for integer register-memory comparisons of type ICmpType.
1198 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1199 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1201 // There are no instructions to compare a register with a memory byte.
1202 if (Load->getMemoryVT() == MVT::i8)
1204 // Otherwise decide on extension type.
1205 switch (Load->getExtensionType()) {
1206 case ISD::NON_EXTLOAD:
1209 return ICmpType != SystemZICMP::UnsignedOnly;
1211 return ICmpType != SystemZICMP::SignedOnly;
1219 // Return true if it is better to swap the operands of C.
1220 static bool shouldSwapCmpOperands(const Comparison &C) {
1221 // Leave f128 comparisons alone, since they have no memory forms.
1222 if (C.Op0.getValueType() == MVT::f128)
1225 // Always keep a floating-point constant second, since comparisons with
1226 // zero can use LOAD TEST and comparisons with other constants make a
1227 // natural memory operand.
1228 if (isa<ConstantFPSDNode>(C.Op1))
1231 // Never swap comparisons with zero since there are many ways to optimize
1233 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1234 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1237 // Also keep natural memory operands second if the loaded value is
1238 // only used here. Several comparisons have memory forms.
1239 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1242 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1243 // In that case we generally prefer the memory to be second.
1244 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1245 // The only exceptions are when the second operand is a constant and
1246 // we can use things like CHHSI.
1249 // The unsigned memory-immediate instructions can handle 16-bit
1250 // unsigned integers.
1251 if (C.ICmpType != SystemZICMP::SignedOnly &&
1252 isUInt<16>(ConstOp1->getZExtValue()))
1254 // The signed memory-immediate instructions can handle 16-bit
1256 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1257 isInt<16>(ConstOp1->getSExtValue()))
1262 // Try to promote the use of CGFR and CLGFR.
1263 unsigned Opcode0 = C.Op0.getOpcode();
1264 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1266 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1268 if (C.ICmpType != SystemZICMP::SignedOnly &&
1269 Opcode0 == ISD::AND &&
1270 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1271 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1277 // Return a version of comparison CC mask CCMask in which the LT and GT
1278 // actions are swapped.
1279 static unsigned reverseCCMask(unsigned CCMask) {
1280 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1281 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1282 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1283 (CCMask & SystemZ::CCMASK_CMP_UO));
1286 // Check whether C tests for equality between X and Y and whether X - Y
1287 // or Y - X is also computed. In that case it's better to compare the
1288 // result of the subtraction against zero.
1289 static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
1290 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1291 C.CCMask == SystemZ::CCMASK_CMP_NE) {
1292 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1294 if (N->getOpcode() == ISD::SUB &&
1295 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1296 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1297 C.Op0 = SDValue(N, 0);
1298 C.Op1 = DAG.getConstant(0, N->getValueType(0));
1305 // Check whether C compares a floating-point value with zero and if that
1306 // floating-point value is also negated. In this case we can use the
1307 // negation to set CC, so avoiding separate LOAD AND TEST and
1308 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1309 static void adjustForFNeg(Comparison &C) {
1310 auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1311 if (C1 && C1->isZero()) {
1312 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1314 if (N->getOpcode() == ISD::FNEG) {
1315 C.Op0 = SDValue(N, 0);
1316 C.CCMask = reverseCCMask(C.CCMask);
1323 // Check whether C compares (shl X, 32) with 0 and whether X is
1324 // also sign-extended. In that case it is better to test the result
1325 // of the sign extension using LTGFR.
1327 // This case is important because InstCombine transforms a comparison
1328 // with (sext (trunc X)) into a comparison with (shl X, 32).
1329 static void adjustForLTGFR(Comparison &C) {
1330 // Check for a comparison between (shl X, 32) and 0.
1331 if (C.Op0.getOpcode() == ISD::SHL &&
1332 C.Op0.getValueType() == MVT::i64 &&
1333 C.Op1.getOpcode() == ISD::Constant &&
1334 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1335 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1336 if (C1 && C1->getZExtValue() == 32) {
1337 SDValue ShlOp0 = C.Op0.getOperand(0);
1338 // See whether X has any SIGN_EXTEND_INREG uses.
1339 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1341 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1342 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1343 C.Op0 = SDValue(N, 0);
1351 // If C compares the truncation of an extending load, try to compare
1352 // the untruncated value instead. This exposes more opportunities to
1354 static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {
1355 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1356 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1357 C.Op1.getOpcode() == ISD::Constant &&
1358 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1359 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1360 if (L->getMemoryVT().getStoreSizeInBits()
1361 <= C.Op0.getValueType().getSizeInBits()) {
1362 unsigned Type = L->getExtensionType();
1363 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1364 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1365 C.Op0 = C.Op0.getOperand(0);
1366 C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
1372 // Return true if shift operation N has an in-range constant shift value.
1373 // Store it in ShiftVal if so.
1374 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1375 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1379 uint64_t Amount = Shift->getZExtValue();
1380 if (Amount >= N.getValueType().getSizeInBits())
1387 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1388 // instruction and whether the CC value is descriptive enough to handle
1389 // a comparison of type Opcode between the AND result and CmpVal.
1390 // CCMask says which comparison result is being tested and BitSize is
1391 // the number of bits in the operands. If TEST UNDER MASK can be used,
1392 // return the corresponding CC mask, otherwise return 0.
1393 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1394 uint64_t Mask, uint64_t CmpVal,
1395 unsigned ICmpType) {
1396 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1398 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1399 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1400 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1403 // Work out the masks for the lowest and highest bits.
1404 unsigned HighShift = 63 - countLeadingZeros(Mask);
1405 uint64_t High = uint64_t(1) << HighShift;
1406 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1408 // Signed ordered comparisons are effectively unsigned if the sign
1410 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1412 // Check for equality comparisons with 0, or the equivalent.
1414 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1415 return SystemZ::CCMASK_TM_ALL_0;
1416 if (CCMask == SystemZ::CCMASK_CMP_NE)
1417 return SystemZ::CCMASK_TM_SOME_1;
1419 if (EffectivelyUnsigned && CmpVal <= Low) {
1420 if (CCMask == SystemZ::CCMASK_CMP_LT)
1421 return SystemZ::CCMASK_TM_ALL_0;
1422 if (CCMask == SystemZ::CCMASK_CMP_GE)
1423 return SystemZ::CCMASK_TM_SOME_1;
1425 if (EffectivelyUnsigned && CmpVal < Low) {
1426 if (CCMask == SystemZ::CCMASK_CMP_LE)
1427 return SystemZ::CCMASK_TM_ALL_0;
1428 if (CCMask == SystemZ::CCMASK_CMP_GT)
1429 return SystemZ::CCMASK_TM_SOME_1;
1432 // Check for equality comparisons with the mask, or the equivalent.
1433 if (CmpVal == Mask) {
1434 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1435 return SystemZ::CCMASK_TM_ALL_1;
1436 if (CCMask == SystemZ::CCMASK_CMP_NE)
1437 return SystemZ::CCMASK_TM_SOME_0;
1439 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1440 if (CCMask == SystemZ::CCMASK_CMP_GT)
1441 return SystemZ::CCMASK_TM_ALL_1;
1442 if (CCMask == SystemZ::CCMASK_CMP_LE)
1443 return SystemZ::CCMASK_TM_SOME_0;
1445 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1446 if (CCMask == SystemZ::CCMASK_CMP_GE)
1447 return SystemZ::CCMASK_TM_ALL_1;
1448 if (CCMask == SystemZ::CCMASK_CMP_LT)
1449 return SystemZ::CCMASK_TM_SOME_0;
1452 // Check for ordered comparisons with the top bit.
1453 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1454 if (CCMask == SystemZ::CCMASK_CMP_LE)
1455 return SystemZ::CCMASK_TM_MSB_0;
1456 if (CCMask == SystemZ::CCMASK_CMP_GT)
1457 return SystemZ::CCMASK_TM_MSB_1;
1459 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1460 if (CCMask == SystemZ::CCMASK_CMP_LT)
1461 return SystemZ::CCMASK_TM_MSB_0;
1462 if (CCMask == SystemZ::CCMASK_CMP_GE)
1463 return SystemZ::CCMASK_TM_MSB_1;
1466 // If there are just two bits, we can do equality checks for Low and High
1468 if (Mask == Low + High) {
1469 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1470 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1471 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1472 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1473 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1474 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1475 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1476 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1479 // Looks like we've exhausted our options.
1483 // See whether C can be implemented as a TEST UNDER MASK instruction.
1484 // Update the arguments with the TM version if so.
1485 static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
1486 // Check that we have a comparison with a constant.
1487 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1490 uint64_t CmpVal = ConstOp1->getZExtValue();
1492 // Check whether the nonconstant input is an AND with a constant mask.
1495 ConstantSDNode *Mask = nullptr;
1496 if (C.Op0.getOpcode() == ISD::AND) {
1497 NewC.Op0 = C.Op0.getOperand(0);
1498 NewC.Op1 = C.Op0.getOperand(1);
1499 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
1502 MaskVal = Mask->getZExtValue();
1504 // There is no instruction to compare with a 64-bit immediate
1505 // so use TMHH instead if possible. We need an unsigned ordered
1506 // comparison with an i64 immediate.
1507 if (NewC.Op0.getValueType() != MVT::i64 ||
1508 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
1509 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
1510 NewC.ICmpType == SystemZICMP::SignedOnly)
1512 // Convert LE and GT comparisons into LT and GE.
1513 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
1514 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
1515 if (CmpVal == uint64_t(-1))
1518 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1520 // If the low N bits of Op1 are zero than the low N bits of Op0 can
1521 // be masked off without changing the result.
1522 MaskVal = -(CmpVal & -CmpVal);
1523 NewC.ICmpType = SystemZICMP::UnsignedOnly;
1526 // Check whether the combination of mask, comparison value and comparison
1527 // type are suitable.
1528 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
1529 unsigned NewCCMask, ShiftVal;
1530 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1531 NewC.Op0.getOpcode() == ISD::SHL &&
1532 isSimpleShift(NewC.Op0, ShiftVal) &&
1533 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1534 MaskVal >> ShiftVal,
1536 SystemZICMP::Any))) {
1537 NewC.Op0 = NewC.Op0.getOperand(0);
1538 MaskVal >>= ShiftVal;
1539 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1540 NewC.Op0.getOpcode() == ISD::SRL &&
1541 isSimpleShift(NewC.Op0, ShiftVal) &&
1542 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1543 MaskVal << ShiftVal,
1545 SystemZICMP::UnsignedOnly))) {
1546 NewC.Op0 = NewC.Op0.getOperand(0);
1547 MaskVal <<= ShiftVal;
1549 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
1555 // Go ahead and make the change.
1556 C.Opcode = SystemZISD::TM;
1558 if (Mask && Mask->getZExtValue() == MaskVal)
1559 C.Op1 = SDValue(Mask, 0);
1561 C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
1562 C.CCValid = SystemZ::CCMASK_TM;
1563 C.CCMask = NewCCMask;
1566 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
1567 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
1568 ISD::CondCode Cond) {
1569 Comparison C(CmpOp0, CmpOp1);
1570 C.CCMask = CCMaskForCondCode(Cond);
1571 if (C.Op0.getValueType().isFloatingPoint()) {
1572 C.CCValid = SystemZ::CCMASK_FCMP;
1573 C.Opcode = SystemZISD::FCMP;
1576 C.CCValid = SystemZ::CCMASK_ICMP;
1577 C.Opcode = SystemZISD::ICMP;
1578 // Choose the type of comparison. Equality and inequality tests can
1579 // use either signed or unsigned comparisons. The choice also doesn't
1580 // matter if both sign bits are known to be clear. In those cases we
1581 // want to give the main isel code the freedom to choose whichever
1583 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1584 C.CCMask == SystemZ::CCMASK_CMP_NE ||
1585 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
1586 C.ICmpType = SystemZICMP::Any;
1587 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
1588 C.ICmpType = SystemZICMP::UnsignedOnly;
1590 C.ICmpType = SystemZICMP::SignedOnly;
1591 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
1592 adjustZeroCmp(DAG, C);
1593 adjustSubwordCmp(DAG, C);
1594 adjustForSubtraction(DAG, C);
1596 adjustICmpTruncate(DAG, C);
1599 if (shouldSwapCmpOperands(C)) {
1600 std::swap(C.Op0, C.Op1);
1601 C.CCMask = reverseCCMask(C.CCMask);
1604 adjustForTestUnderMask(DAG, C);
1608 // Emit the comparison instruction described by C.
1609 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1610 if (C.Opcode == SystemZISD::ICMP)
1611 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
1612 DAG.getConstant(C.ICmpType, MVT::i32));
1613 if (C.Opcode == SystemZISD::TM) {
1614 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
1615 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
1616 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
1617 DAG.getConstant(RegisterOnly, MVT::i32));
1619 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
1622 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
1623 // 64 bits. Extend is the extension type to use. Store the high part
1624 // in Hi and the low part in Lo.
1625 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
1626 unsigned Extend, SDValue Op0, SDValue Op1,
1627 SDValue &Hi, SDValue &Lo) {
1628 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1629 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
1630 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1631 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
1632 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
1633 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
1636 // Lower a binary operation that produces two VT results, one in each
1637 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1638 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1639 // on the extended Op0 and (unextended) Op1. Store the even register result
1640 // in Even and the odd register result in Odd.
1641 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1642 unsigned Extend, unsigned Opcode,
1643 SDValue Op0, SDValue Op1,
1644 SDValue &Even, SDValue &Odd) {
1645 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1646 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1647 SDValue(In128, 0), Op1);
1648 bool Is32Bit = is32Bit(VT);
1649 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
1650 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
1653 // Return an i32 value that is 1 if the CC value produced by Glue is
1654 // in the mask CCMask and 0 otherwise. CC is known to have a value
1655 // in CCValid, so other values can be ignored.
1656 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
1657 unsigned CCValid, unsigned CCMask) {
1658 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
1659 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
1661 if (Conversion.XORValue)
1662 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
1663 DAG.getConstant(Conversion.XORValue, MVT::i32));
1665 if (Conversion.AddValue)
1666 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
1667 DAG.getConstant(Conversion.AddValue, MVT::i32));
1669 // The SHR/AND sequence should get optimized to an RISBG.
1670 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
1671 DAG.getConstant(Conversion.Bit, MVT::i32));
1672 if (Conversion.Bit != 31)
1673 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
1674 DAG.getConstant(1, MVT::i32));
1678 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
1679 SelectionDAG &DAG) const {
1680 SDValue CmpOp0 = Op.getOperand(0);
1681 SDValue CmpOp1 = Op.getOperand(1);
1682 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1685 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1686 SDValue Glue = emitCmp(DAG, DL, C);
1687 return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
1690 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1691 SDValue Chain = Op.getOperand(0);
1692 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1693 SDValue CmpOp0 = Op.getOperand(2);
1694 SDValue CmpOp1 = Op.getOperand(3);
1695 SDValue Dest = Op.getOperand(4);
1698 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1699 SDValue Glue = emitCmp(DAG, DL, C);
1700 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1701 Chain, DAG.getConstant(C.CCValid, MVT::i32),
1702 DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
1705 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
1706 // allowing Pos and Neg to be wider than CmpOp.
1707 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
1708 return (Neg.getOpcode() == ISD::SUB &&
1709 Neg.getOperand(0).getOpcode() == ISD::Constant &&
1710 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
1711 Neg.getOperand(1) == Pos &&
1713 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
1714 Pos.getOperand(0) == CmpOp)));
1717 // Return the absolute or negative absolute of Op; IsNegative decides which.
1718 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
1720 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
1722 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
1723 DAG.getConstant(0, Op.getValueType()), Op);
1727 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1728 SelectionDAG &DAG) const {
1729 SDValue CmpOp0 = Op.getOperand(0);
1730 SDValue CmpOp1 = Op.getOperand(1);
1731 SDValue TrueOp = Op.getOperand(2);
1732 SDValue FalseOp = Op.getOperand(3);
1733 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1736 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1738 // Check for absolute and negative-absolute selections, including those
1739 // where the comparison value is sign-extended (for LPGFR and LNGFR).
1740 // This check supplements the one in DAGCombiner.
1741 if (C.Opcode == SystemZISD::ICMP &&
1742 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
1743 C.CCMask != SystemZ::CCMASK_CMP_NE &&
1744 C.Op1.getOpcode() == ISD::Constant &&
1745 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1746 if (isAbsolute(C.Op0, TrueOp, FalseOp))
1747 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
1748 if (isAbsolute(C.Op0, FalseOp, TrueOp))
1749 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
1752 SDValue Glue = emitCmp(DAG, DL, C);
1754 // Special case for handling -1/0 results. The shifts we use here
1755 // should get optimized with the IPM conversion sequence.
1756 auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
1757 auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
1758 if (TrueC && FalseC) {
1759 int64_t TrueVal = TrueC->getSExtValue();
1760 int64_t FalseVal = FalseC->getSExtValue();
1761 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
1762 // Invert the condition if we want -1 on false.
1764 C.CCMask ^= C.CCValid;
1765 SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
1766 EVT VT = Op.getValueType();
1767 // Extend the result to VT. Upper bits are ignored.
1769 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
1770 // Sign-extend from the low bit.
1771 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
1772 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
1773 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
1777 SmallVector<SDValue, 5> Ops;
1778 Ops.push_back(TrueOp);
1779 Ops.push_back(FalseOp);
1780 Ops.push_back(DAG.getConstant(C.CCValid, MVT::i32));
1781 Ops.push_back(DAG.getConstant(C.CCMask, MVT::i32));
1782 Ops.push_back(Glue);
1784 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1785 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
1788 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1789 SelectionDAG &DAG) const {
1791 const GlobalValue *GV = Node->getGlobal();
1792 int64_t Offset = Node->getOffset();
1793 EVT PtrVT = getPointerTy();
1794 Reloc::Model RM = DAG.getTarget().getRelocationModel();
1795 CodeModel::Model CM = DAG.getTarget().getCodeModel();
1798 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1799 // Assign anchors at 1<<12 byte boundaries.
1800 uint64_t Anchor = Offset & ~uint64_t(0xfff);
1801 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
1802 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1804 // The offset can be folded into the address if it is aligned to a halfword.
1806 if (Offset != 0 && (Offset & 1) == 0) {
1807 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
1808 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
1812 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1813 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1814 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1815 MachinePointerInfo::getGOT(), false, false, false, 0);
1818 // If there was a non-zero offset that we didn't fold, create an explicit
1821 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1822 DAG.getConstant(Offset, PtrVT));
1827 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1828 SelectionDAG &DAG) const {
1830 const GlobalValue *GV = Node->getGlobal();
1831 EVT PtrVT = getPointerTy();
1832 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
1834 if (model != TLSModel::LocalExec)
1835 llvm_unreachable("only local-exec TLS mode supported");
1837 // The high part of the thread pointer is in access register 0.
1838 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1839 DAG.getConstant(0, MVT::i32));
1840 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1842 // The low part of the thread pointer is in access register 1.
1843 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1844 DAG.getConstant(1, MVT::i32));
1845 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1847 // Merge them into a single 64-bit address.
1848 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1849 DAG.getConstant(32, PtrVT));
1850 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1852 // Get the offset of GA from the thread pointer.
1853 SystemZConstantPoolValue *CPV =
1854 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1856 // Force the offset into the constant pool and load it from there.
1857 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1858 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1859 CPAddr, MachinePointerInfo::getConstantPool(),
1860 false, false, false, 0);
1862 // Add the base and offset together.
1863 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1866 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1867 SelectionDAG &DAG) const {
1869 const BlockAddress *BA = Node->getBlockAddress();
1870 int64_t Offset = Node->getOffset();
1871 EVT PtrVT = getPointerTy();
1873 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1874 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1878 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1879 SelectionDAG &DAG) const {
1881 EVT PtrVT = getPointerTy();
1882 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1884 // Use LARL to load the address of the table.
1885 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1888 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1889 SelectionDAG &DAG) const {
1891 EVT PtrVT = getPointerTy();
1894 if (CP->isMachineConstantPoolEntry())
1895 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1896 CP->getAlignment());
1898 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1899 CP->getAlignment(), CP->getOffset());
1901 // Use LARL to load the address of the constant pool entry.
1902 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1905 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1906 SelectionDAG &DAG) const {
1908 SDValue In = Op.getOperand(0);
1909 EVT InVT = In.getValueType();
1910 EVT ResVT = Op.getValueType();
1912 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1914 if (Subtarget.hasHighWord()) {
1915 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
1917 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1918 MVT::i64, SDValue(U64, 0), In);
1920 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1921 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
1922 DAG.getConstant(32, MVT::i64));
1924 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
1925 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
1926 DL, MVT::f32, Out64);
1928 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1929 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1930 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1931 MVT::f64, SDValue(U64, 0), In);
1932 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
1933 if (Subtarget.hasHighWord())
1934 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
1936 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
1937 DAG.getConstant(32, MVT::i64));
1938 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1940 llvm_unreachable("Unexpected bitcast combination");
1943 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1944 SelectionDAG &DAG) const {
1945 MachineFunction &MF = DAG.getMachineFunction();
1946 SystemZMachineFunctionInfo *FuncInfo =
1947 MF.getInfo<SystemZMachineFunctionInfo>();
1948 EVT PtrVT = getPointerTy();
1950 SDValue Chain = Op.getOperand(0);
1951 SDValue Addr = Op.getOperand(1);
1952 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1955 // The initial values of each field.
1956 const unsigned NumFields = 4;
1957 SDValue Fields[NumFields] = {
1958 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1959 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1960 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1961 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1964 // Store each field into its respective slot.
1965 SDValue MemOps[NumFields];
1966 unsigned Offset = 0;
1967 for (unsigned I = 0; I < NumFields; ++I) {
1968 SDValue FieldAddr = Addr;
1970 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1971 DAG.getIntPtrConstant(Offset));
1972 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1973 MachinePointerInfo(SV, Offset),
1977 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1980 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1981 SelectionDAG &DAG) const {
1982 SDValue Chain = Op.getOperand(0);
1983 SDValue DstPtr = Op.getOperand(1);
1984 SDValue SrcPtr = Op.getOperand(2);
1985 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1986 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1989 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1990 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1991 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
1994 SDValue SystemZTargetLowering::
1995 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1996 SDValue Chain = Op.getOperand(0);
1997 SDValue Size = Op.getOperand(1);
2000 unsigned SPReg = getStackPointerRegisterToSaveRestore();
2002 // Get a reference to the stack pointer.
2003 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
2005 // Get the new stack pointer value.
2006 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
2008 // Copy the new stack pointer back.
2009 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2011 // The allocated data lives above the 160 bytes allocated for the standard
2012 // frame, plus any outgoing stack arguments. We don't know how much that
2013 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2014 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2015 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2017 SDValue Ops[2] = { Result, Chain };
2018 return DAG.getMergeValues(Ops, DL);
2021 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2022 SelectionDAG &DAG) const {
2023 EVT VT = Op.getValueType();
2027 // Just do a normal 64-bit multiplication and extract the results.
2028 // We define this so that it can be used for constant division.
2029 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2030 Op.getOperand(1), Ops[1], Ops[0]);
2032 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2034 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
2036 // but using the fact that the upper halves are either all zeros
2039 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
2041 // and grouping the right terms together since they are quicker than the
2044 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
2045 SDValue C63 = DAG.getConstant(63, MVT::i64);
2046 SDValue LL = Op.getOperand(0);
2047 SDValue RL = Op.getOperand(1);
2048 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
2049 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
2050 // UMUL_LOHI64 returns the low result in the odd register and the high
2051 // result in the even register. SMUL_LOHI is defined to return the
2052 // low half first, so the results are in reverse order.
2053 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2054 LL, RL, Ops[1], Ops[0]);
2055 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
2056 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
2057 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
2058 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
2060 return DAG.getMergeValues(Ops, DL);
2063 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
2064 SelectionDAG &DAG) const {
2065 EVT VT = Op.getValueType();
2069 // Just do a normal 64-bit multiplication and extract the results.
2070 // We define this so that it can be used for constant division.
2071 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
2072 Op.getOperand(1), Ops[1], Ops[0]);
2074 // UMUL_LOHI64 returns the low result in the odd register and the high
2075 // result in the even register. UMUL_LOHI is defined to return the
2076 // low half first, so the results are in reverse order.
2077 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2078 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2079 return DAG.getMergeValues(Ops, DL);
2082 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
2083 SelectionDAG &DAG) const {
2084 SDValue Op0 = Op.getOperand(0);
2085 SDValue Op1 = Op.getOperand(1);
2086 EVT VT = Op.getValueType();
2090 // We use DSGF for 32-bit division.
2092 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
2093 Opcode = SystemZISD::SDIVREM32;
2094 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
2095 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
2096 Opcode = SystemZISD::SDIVREM32;
2098 Opcode = SystemZISD::SDIVREM64;
2100 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
2101 // input is "don't care". The instruction returns the remainder in
2102 // the even register and the quotient in the odd register.
2104 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
2105 Op0, Op1, Ops[1], Ops[0]);
2106 return DAG.getMergeValues(Ops, DL);
2109 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
2110 SelectionDAG &DAG) const {
2111 EVT VT = Op.getValueType();
2114 // DL(G) uses a double-width dividend, so we need to clear the even
2115 // register in the GR128 input. The instruction returns the remainder
2116 // in the even register and the quotient in the odd register.
2119 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
2120 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2122 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
2123 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2124 return DAG.getMergeValues(Ops, DL);
2127 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
2128 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
2130 // Get the known-zero masks for each operand.
2131 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
2132 APInt KnownZero[2], KnownOne[2];
2133 DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
2134 DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
2136 // See if the upper 32 bits of one operand and the lower 32 bits of the
2137 // other are known zero. They are the low and high operands respectively.
2138 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
2139 KnownZero[1].getZExtValue() };
2141 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
2143 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
2148 SDValue LowOp = Ops[Low];
2149 SDValue HighOp = Ops[High];
2151 // If the high part is a constant, we're better off using IILH.
2152 if (HighOp.getOpcode() == ISD::Constant)
2155 // If the low part is a constant that is outside the range of LHI,
2156 // then we're better off using IILF.
2157 if (LowOp.getOpcode() == ISD::Constant) {
2158 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
2159 if (!isInt<16>(Value))
2163 // Check whether the high part is an AND that doesn't change the
2164 // high 32 bits and just masks out low bits. We can skip it if so.
2165 if (HighOp.getOpcode() == ISD::AND &&
2166 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
2167 SDValue HighOp0 = HighOp.getOperand(0);
2168 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
2169 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
2173 // Take advantage of the fact that all GR32 operations only change the
2174 // low 32 bits by truncating Low to an i32 and inserting it directly
2175 // using a subreg. The interesting cases are those where the truncation
2178 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
2179 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
2180 MVT::i64, HighOp, Low32);
2183 // Op is an atomic load. Lower it into a normal volatile load.
2184 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
2185 SelectionDAG &DAG) const {
2186 auto *Node = cast<AtomicSDNode>(Op.getNode());
2187 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
2188 Node->getChain(), Node->getBasePtr(),
2189 Node->getMemoryVT(), Node->getMemOperand());
2192 // Op is an atomic store. Lower it into a normal volatile store followed
2193 // by a serialization.
2194 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
2195 SelectionDAG &DAG) const {
2196 auto *Node = cast<AtomicSDNode>(Op.getNode());
2197 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
2198 Node->getBasePtr(), Node->getMemoryVT(),
2199 Node->getMemOperand());
2200 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
2204 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
2205 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
2206 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
2208 unsigned Opcode) const {
2209 auto *Node = cast<AtomicSDNode>(Op.getNode());
2211 // 32-bit operations need no code outside the main loop.
2212 EVT NarrowVT = Node->getMemoryVT();
2213 EVT WideVT = MVT::i32;
2214 if (NarrowVT == WideVT)
2217 int64_t BitSize = NarrowVT.getSizeInBits();
2218 SDValue ChainIn = Node->getChain();
2219 SDValue Addr = Node->getBasePtr();
2220 SDValue Src2 = Node->getVal();
2221 MachineMemOperand *MMO = Node->getMemOperand();
2223 EVT PtrVT = Addr.getValueType();
2225 // Convert atomic subtracts of constants into additions.
2226 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
2227 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
2228 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
2229 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
2232 // Get the address of the containing word.
2233 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2234 DAG.getConstant(-4, PtrVT));
2236 // Get the number of bits that the word must be rotated left in order
2237 // to bring the field to the top bits of a GR32.
2238 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2239 DAG.getConstant(3, PtrVT));
2240 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2242 // Get the complementing shift amount, for rotating a field in the top
2243 // bits back to its proper position.
2244 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2245 DAG.getConstant(0, WideVT), BitShift);
2247 // Extend the source operand to 32 bits and prepare it for the inner loop.
2248 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
2249 // operations require the source to be shifted in advance. (This shift
2250 // can be folded if the source is constant.) For AND and NAND, the lower
2251 // bits must be set, while for other opcodes they should be left clear.
2252 if (Opcode != SystemZISD::ATOMIC_SWAPW)
2253 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
2254 DAG.getConstant(32 - BitSize, WideVT));
2255 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
2256 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
2257 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
2258 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
2260 // Construct the ATOMIC_LOADW_* node.
2261 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2262 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
2263 DAG.getConstant(BitSize, WideVT) };
2264 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
2267 // Rotate the result of the final CS so that the field is in the lower
2268 // bits of a GR32, then truncate it.
2269 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
2270 DAG.getConstant(BitSize, WideVT));
2271 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
2273 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
2274 return DAG.getMergeValues(RetOps, DL);
2277 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
2278 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
2279 // operations into additions.
2280 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
2281 SelectionDAG &DAG) const {
2282 auto *Node = cast<AtomicSDNode>(Op.getNode());
2283 EVT MemVT = Node->getMemoryVT();
2284 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
2285 // A full-width operation.
2286 assert(Op.getValueType() == MemVT && "Mismatched VTs");
2287 SDValue Src2 = Node->getVal();
2291 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
2292 // Use an addition if the operand is constant and either LAA(G) is
2293 // available or the negative value is in the range of A(G)FHI.
2294 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
2295 if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
2296 NegSrc2 = DAG.getConstant(Value, MemVT);
2297 } else if (Subtarget.hasInterlockedAccess1())
2298 // Use LAA(G) if available.
2299 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
2302 if (NegSrc2.getNode())
2303 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
2304 Node->getChain(), Node->getBasePtr(), NegSrc2,
2305 Node->getMemOperand(), Node->getOrdering(),
2306 Node->getSynchScope());
2308 // Use the node as-is.
2312 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
2315 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
2316 // into a fullword ATOMIC_CMP_SWAPW operation.
2317 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
2318 SelectionDAG &DAG) const {
2319 auto *Node = cast<AtomicSDNode>(Op.getNode());
2321 // We have native support for 32-bit compare and swap.
2322 EVT NarrowVT = Node->getMemoryVT();
2323 EVT WideVT = MVT::i32;
2324 if (NarrowVT == WideVT)
2327 int64_t BitSize = NarrowVT.getSizeInBits();
2328 SDValue ChainIn = Node->getOperand(0);
2329 SDValue Addr = Node->getOperand(1);
2330 SDValue CmpVal = Node->getOperand(2);
2331 SDValue SwapVal = Node->getOperand(3);
2332 MachineMemOperand *MMO = Node->getMemOperand();
2334 EVT PtrVT = Addr.getValueType();
2336 // Get the address of the containing word.
2337 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2338 DAG.getConstant(-4, PtrVT));
2340 // Get the number of bits that the word must be rotated left in order
2341 // to bring the field to the top bits of a GR32.
2342 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2343 DAG.getConstant(3, PtrVT));
2344 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2346 // Get the complementing shift amount, for rotating a field in the top
2347 // bits back to its proper position.
2348 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2349 DAG.getConstant(0, WideVT), BitShift);
2351 // Construct the ATOMIC_CMP_SWAPW node.
2352 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2353 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
2354 NegBitShift, DAG.getConstant(BitSize, WideVT) };
2355 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
2356 VTList, Ops, NarrowVT, MMO);
2360 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
2361 SelectionDAG &DAG) const {
2362 MachineFunction &MF = DAG.getMachineFunction();
2363 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2364 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
2365 SystemZ::R15D, Op.getValueType());
2368 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
2369 SelectionDAG &DAG) const {
2370 MachineFunction &MF = DAG.getMachineFunction();
2371 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2372 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
2373 SystemZ::R15D, Op.getOperand(1));
2376 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
2377 SelectionDAG &DAG) const {
2378 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2380 // Just preserve the chain.
2381 return Op.getOperand(0);
2383 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2384 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
2385 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
2388 DAG.getConstant(Code, MVT::i32),
2391 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
2392 Node->getVTList(), Ops,
2393 Node->getMemoryVT(), Node->getMemOperand());
2396 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
2397 SelectionDAG &DAG) const {
2398 switch (Op.getOpcode()) {
2400 return lowerBR_CC(Op, DAG);
2401 case ISD::SELECT_CC:
2402 return lowerSELECT_CC(Op, DAG);
2404 return lowerSETCC(Op, DAG);
2405 case ISD::GlobalAddress:
2406 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
2407 case ISD::GlobalTLSAddress:
2408 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
2409 case ISD::BlockAddress:
2410 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
2411 case ISD::JumpTable:
2412 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
2413 case ISD::ConstantPool:
2414 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
2416 return lowerBITCAST(Op, DAG);
2418 return lowerVASTART(Op, DAG);
2420 return lowerVACOPY(Op, DAG);
2421 case ISD::DYNAMIC_STACKALLOC:
2422 return lowerDYNAMIC_STACKALLOC(Op, DAG);
2423 case ISD::SMUL_LOHI:
2424 return lowerSMUL_LOHI(Op, DAG);
2425 case ISD::UMUL_LOHI:
2426 return lowerUMUL_LOHI(Op, DAG);
2428 return lowerSDIVREM(Op, DAG);
2430 return lowerUDIVREM(Op, DAG);
2432 return lowerOR(Op, DAG);
2433 case ISD::ATOMIC_SWAP:
2434 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
2435 case ISD::ATOMIC_STORE:
2436 return lowerATOMIC_STORE(Op, DAG);
2437 case ISD::ATOMIC_LOAD:
2438 return lowerATOMIC_LOAD(Op, DAG);
2439 case ISD::ATOMIC_LOAD_ADD:
2440 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
2441 case ISD::ATOMIC_LOAD_SUB:
2442 return lowerATOMIC_LOAD_SUB(Op, DAG);
2443 case ISD::ATOMIC_LOAD_AND:
2444 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
2445 case ISD::ATOMIC_LOAD_OR:
2446 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
2447 case ISD::ATOMIC_LOAD_XOR:
2448 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
2449 case ISD::ATOMIC_LOAD_NAND:
2450 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
2451 case ISD::ATOMIC_LOAD_MIN:
2452 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
2453 case ISD::ATOMIC_LOAD_MAX:
2454 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
2455 case ISD::ATOMIC_LOAD_UMIN:
2456 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
2457 case ISD::ATOMIC_LOAD_UMAX:
2458 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
2459 case ISD::ATOMIC_CMP_SWAP:
2460 return lowerATOMIC_CMP_SWAP(Op, DAG);
2461 case ISD::STACKSAVE:
2462 return lowerSTACKSAVE(Op, DAG);
2463 case ISD::STACKRESTORE:
2464 return lowerSTACKRESTORE(Op, DAG);
2466 return lowerPREFETCH(Op, DAG);
2468 llvm_unreachable("Unexpected node to lower");
2472 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
2473 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
2478 OPCODE(PCREL_WRAPPER);
2479 OPCODE(PCREL_OFFSET);
2485 OPCODE(SELECT_CCMASK);
2486 OPCODE(ADJDYNALLOC);
2487 OPCODE(EXTRACT_ACCESS);
2488 OPCODE(UMUL_LOHI64);
2504 OPCODE(SEARCH_STRING);
2507 OPCODE(ATOMIC_SWAPW);
2508 OPCODE(ATOMIC_LOADW_ADD);
2509 OPCODE(ATOMIC_LOADW_SUB);
2510 OPCODE(ATOMIC_LOADW_AND);
2511 OPCODE(ATOMIC_LOADW_OR);
2512 OPCODE(ATOMIC_LOADW_XOR);
2513 OPCODE(ATOMIC_LOADW_NAND);
2514 OPCODE(ATOMIC_LOADW_MIN);
2515 OPCODE(ATOMIC_LOADW_MAX);
2516 OPCODE(ATOMIC_LOADW_UMIN);
2517 OPCODE(ATOMIC_LOADW_UMAX);
2518 OPCODE(ATOMIC_CMP_SWAPW);
2525 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
2526 DAGCombinerInfo &DCI) const {
2527 SelectionDAG &DAG = DCI.DAG;
2528 unsigned Opcode = N->getOpcode();
2529 if (Opcode == ISD::SIGN_EXTEND) {
2530 // Convert (sext (ashr (shl X, C1), C2)) to
2531 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
2532 // cheap as narrower ones.
2533 SDValue N0 = N->getOperand(0);
2534 EVT VT = N->getValueType(0);
2535 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
2536 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2537 SDValue Inner = N0.getOperand(0);
2538 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
2539 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
2540 unsigned Extra = (VT.getSizeInBits() -
2541 N0.getValueType().getSizeInBits());
2542 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
2543 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
2544 EVT ShiftVT = N0.getOperand(1).getValueType();
2545 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
2546 Inner.getOperand(0));
2547 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
2548 DAG.getConstant(NewShlAmt, ShiftVT));
2549 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
2550 DAG.getConstant(NewSraAmt, ShiftVT));
2558 //===----------------------------------------------------------------------===//
2560 //===----------------------------------------------------------------------===//
2562 // Create a new basic block after MBB.
2563 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
2564 MachineFunction &MF = *MBB->getParent();
2565 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
2566 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
2570 // Split MBB after MI and return the new block (the one that contains
2571 // instructions after MI).
2572 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
2573 MachineBasicBlock *MBB) {
2574 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2575 NewMBB->splice(NewMBB->begin(), MBB,
2576 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2577 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2581 // Split MBB before MI and return the new block (the one that contains MI).
2582 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
2583 MachineBasicBlock *MBB) {
2584 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2585 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
2586 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2590 // Force base value Base into a register before MI. Return the register.
2591 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
2592 const SystemZInstrInfo *TII) {
2594 return Base.getReg();
2596 MachineBasicBlock *MBB = MI->getParent();
2597 MachineFunction &MF = *MBB->getParent();
2598 MachineRegisterInfo &MRI = MF.getRegInfo();
2600 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2601 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
2602 .addOperand(Base).addImm(0).addReg(0);
2606 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
2608 SystemZTargetLowering::emitSelect(MachineInstr *MI,
2609 MachineBasicBlock *MBB) const {
2610 const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
2611 MBB->getParent()->getTarget().getInstrInfo());
2613 unsigned DestReg = MI->getOperand(0).getReg();
2614 unsigned TrueReg = MI->getOperand(1).getReg();
2615 unsigned FalseReg = MI->getOperand(2).getReg();
2616 unsigned CCValid = MI->getOperand(3).getImm();
2617 unsigned CCMask = MI->getOperand(4).getImm();
2618 DebugLoc DL = MI->getDebugLoc();
2620 MachineBasicBlock *StartMBB = MBB;
2621 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2622 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2625 // BRC CCMask, JoinMBB
2626 // # fallthrough to FalseMBB
2628 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2629 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2630 MBB->addSuccessor(JoinMBB);
2631 MBB->addSuccessor(FalseMBB);
2634 // # fallthrough to JoinMBB
2636 MBB->addSuccessor(JoinMBB);
2639 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
2642 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
2643 .addReg(TrueReg).addMBB(StartMBB)
2644 .addReg(FalseReg).addMBB(FalseMBB);
2646 MI->eraseFromParent();
2650 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
2651 // StoreOpcode is the store to use and Invert says whether the store should
2652 // happen when the condition is false rather than true. If a STORE ON
2653 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
2655 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
2656 MachineBasicBlock *MBB,
2657 unsigned StoreOpcode, unsigned STOCOpcode,
2658 bool Invert) const {
2659 const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
2660 MBB->getParent()->getTarget().getInstrInfo());
2662 unsigned SrcReg = MI->getOperand(0).getReg();
2663 MachineOperand Base = MI->getOperand(1);
2664 int64_t Disp = MI->getOperand(2).getImm();
2665 unsigned IndexReg = MI->getOperand(3).getReg();
2666 unsigned CCValid = MI->getOperand(4).getImm();
2667 unsigned CCMask = MI->getOperand(5).getImm();
2668 DebugLoc DL = MI->getDebugLoc();
2670 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2672 // Use STOCOpcode if possible. We could use different store patterns in
2673 // order to avoid matching the index register, but the performance trade-offs
2674 // might be more complicated in that case.
2675 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
2678 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
2679 .addReg(SrcReg).addOperand(Base).addImm(Disp)
2680 .addImm(CCValid).addImm(CCMask);
2681 MI->eraseFromParent();
2685 // Get the condition needed to branch around the store.
2689 MachineBasicBlock *StartMBB = MBB;
2690 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2691 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2694 // BRC CCMask, JoinMBB
2695 // # fallthrough to FalseMBB
2697 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2698 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2699 MBB->addSuccessor(JoinMBB);
2700 MBB->addSuccessor(FalseMBB);
2703 // store %SrcReg, %Disp(%Index,%Base)
2704 // # fallthrough to JoinMBB
2706 BuildMI(MBB, DL, TII->get(StoreOpcode))
2707 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
2708 MBB->addSuccessor(JoinMBB);
2710 MI->eraseFromParent();
2714 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
2715 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
2716 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
2717 // BitSize is the width of the field in bits, or 0 if this is a partword
2718 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
2719 // is one of the operands. Invert says whether the field should be
2720 // inverted after performing BinOpcode (e.g. for NAND).
2722 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
2723 MachineBasicBlock *MBB,
2726 bool Invert) const {
2727 MachineFunction &MF = *MBB->getParent();
2728 const SystemZInstrInfo *TII =
2729 static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
2730 MachineRegisterInfo &MRI = MF.getRegInfo();
2731 bool IsSubWord = (BitSize < 32);
2733 // Extract the operands. Base can be a register or a frame index.
2734 // Src2 can be a register or immediate.
2735 unsigned Dest = MI->getOperand(0).getReg();
2736 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2737 int64_t Disp = MI->getOperand(2).getImm();
2738 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
2739 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2740 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2741 DebugLoc DL = MI->getDebugLoc();
2743 BitSize = MI->getOperand(6).getImm();
2745 // Subword operations use 32-bit registers.
2746 const TargetRegisterClass *RC = (BitSize <= 32 ?
2747 &SystemZ::GR32BitRegClass :
2748 &SystemZ::GR64BitRegClass);
2749 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2750 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2752 // Get the right opcodes for the displacement.
2753 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2754 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2755 assert(LOpcode && CSOpcode && "Displacement out of range");
2757 // Create virtual registers for temporary results.
2758 unsigned OrigVal = MRI.createVirtualRegister(RC);
2759 unsigned OldVal = MRI.createVirtualRegister(RC);
2760 unsigned NewVal = (BinOpcode || IsSubWord ?
2761 MRI.createVirtualRegister(RC) : Src2.getReg());
2762 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2763 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2765 // Insert a basic block for the main loop.
2766 MachineBasicBlock *StartMBB = MBB;
2767 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2768 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2772 // %OrigVal = L Disp(%Base)
2773 // # fall through to LoopMMB
2775 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2776 .addOperand(Base).addImm(Disp).addReg(0);
2777 MBB->addSuccessor(LoopMBB);
2780 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
2781 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2782 // %RotatedNewVal = OP %RotatedOldVal, %Src2
2783 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2784 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2786 // # fall through to DoneMMB
2788 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2789 .addReg(OrigVal).addMBB(StartMBB)
2790 .addReg(Dest).addMBB(LoopMBB);
2792 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2793 .addReg(OldVal).addReg(BitShift).addImm(0);
2795 // Perform the operation normally and then invert every bit of the field.
2796 unsigned Tmp = MRI.createVirtualRegister(RC);
2797 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
2798 .addReg(RotatedOldVal).addOperand(Src2);
2800 // XILF with the upper BitSize bits set.
2801 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2802 .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
2803 else if (BitSize == 32)
2804 // XILF with every bit set.
2805 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2806 .addReg(Tmp).addImm(~uint32_t(0));
2808 // Use LCGR and add -1 to the result, which is more compact than
2809 // an XILF, XILH pair.
2810 unsigned Tmp2 = MRI.createVirtualRegister(RC);
2811 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
2812 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
2813 .addReg(Tmp2).addImm(-1);
2815 } else if (BinOpcode)
2816 // A simply binary operation.
2817 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
2818 .addReg(RotatedOldVal).addOperand(Src2);
2820 // Use RISBG to rotate Src2 into position and use it to replace the
2821 // field in RotatedOldVal.
2822 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
2823 .addReg(RotatedOldVal).addReg(Src2.getReg())
2824 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
2826 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2827 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2828 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2829 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2830 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2831 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2832 MBB->addSuccessor(LoopMBB);
2833 MBB->addSuccessor(DoneMBB);
2835 MI->eraseFromParent();
2839 // Implement EmitInstrWithCustomInserter for pseudo
2840 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
2841 // instruction that should be used to compare the current field with the
2842 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
2843 // for when the current field should be kept. BitSize is the width of
2844 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
2846 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
2847 MachineBasicBlock *MBB,
2848 unsigned CompareOpcode,
2849 unsigned KeepOldMask,
2850 unsigned BitSize) const {
2851 MachineFunction &MF = *MBB->getParent();
2852 const SystemZInstrInfo *TII =
2853 static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
2854 MachineRegisterInfo &MRI = MF.getRegInfo();
2855 bool IsSubWord = (BitSize < 32);
2857 // Extract the operands. Base can be a register or a frame index.
2858 unsigned Dest = MI->getOperand(0).getReg();
2859 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2860 int64_t Disp = MI->getOperand(2).getImm();
2861 unsigned Src2 = MI->getOperand(3).getReg();
2862 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2863 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2864 DebugLoc DL = MI->getDebugLoc();
2866 BitSize = MI->getOperand(6).getImm();
2868 // Subword operations use 32-bit registers.
2869 const TargetRegisterClass *RC = (BitSize <= 32 ?
2870 &SystemZ::GR32BitRegClass :
2871 &SystemZ::GR64BitRegClass);
2872 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2873 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2875 // Get the right opcodes for the displacement.
2876 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2877 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2878 assert(LOpcode && CSOpcode && "Displacement out of range");
2880 // Create virtual registers for temporary results.
2881 unsigned OrigVal = MRI.createVirtualRegister(RC);
2882 unsigned OldVal = MRI.createVirtualRegister(RC);
2883 unsigned NewVal = MRI.createVirtualRegister(RC);
2884 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2885 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
2886 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2888 // Insert 3 basic blocks for the loop.
2889 MachineBasicBlock *StartMBB = MBB;
2890 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2891 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2892 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2893 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2897 // %OrigVal = L Disp(%Base)
2898 // # fall through to LoopMMB
2900 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2901 .addOperand(Base).addImm(Disp).addReg(0);
2902 MBB->addSuccessor(LoopMBB);
2905 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2906 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2907 // CompareOpcode %RotatedOldVal, %Src2
2908 // BRC KeepOldMask, UpdateMBB
2910 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2911 .addReg(OrigVal).addMBB(StartMBB)
2912 .addReg(Dest).addMBB(UpdateMBB);
2914 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2915 .addReg(OldVal).addReg(BitShift).addImm(0);
2916 BuildMI(MBB, DL, TII->get(CompareOpcode))
2917 .addReg(RotatedOldVal).addReg(Src2);
2918 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2919 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2920 MBB->addSuccessor(UpdateMBB);
2921 MBB->addSuccessor(UseAltMBB);
2924 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2925 // # fall through to UpdateMMB
2928 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2929 .addReg(RotatedOldVal).addReg(Src2)
2930 .addImm(32).addImm(31 + BitSize).addImm(0);
2931 MBB->addSuccessor(UpdateMBB);
2934 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2935 // [ %RotatedAltVal, UseAltMBB ]
2936 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2937 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2939 // # fall through to DoneMMB
2941 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2942 .addReg(RotatedOldVal).addMBB(LoopMBB)
2943 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2945 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2946 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2947 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2948 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2949 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2950 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2951 MBB->addSuccessor(LoopMBB);
2952 MBB->addSuccessor(DoneMBB);
2954 MI->eraseFromParent();
2958 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2961 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2962 MachineBasicBlock *MBB) const {
2963 MachineFunction &MF = *MBB->getParent();
2964 const SystemZInstrInfo *TII =
2965 static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
2966 MachineRegisterInfo &MRI = MF.getRegInfo();
2968 // Extract the operands. Base can be a register or a frame index.
2969 unsigned Dest = MI->getOperand(0).getReg();
2970 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2971 int64_t Disp = MI->getOperand(2).getImm();
2972 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2973 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2974 unsigned BitShift = MI->getOperand(5).getReg();
2975 unsigned NegBitShift = MI->getOperand(6).getReg();
2976 int64_t BitSize = MI->getOperand(7).getImm();
2977 DebugLoc DL = MI->getDebugLoc();
2979 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2981 // Get the right opcodes for the displacement.
2982 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2983 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2984 assert(LOpcode && CSOpcode && "Displacement out of range");
2986 // Create virtual registers for temporary results.
2987 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2988 unsigned OldVal = MRI.createVirtualRegister(RC);
2989 unsigned CmpVal = MRI.createVirtualRegister(RC);
2990 unsigned SwapVal = MRI.createVirtualRegister(RC);
2991 unsigned StoreVal = MRI.createVirtualRegister(RC);
2992 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2993 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2994 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2996 // Insert 2 basic blocks for the loop.
2997 MachineBasicBlock *StartMBB = MBB;
2998 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2999 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3000 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
3004 // %OrigOldVal = L Disp(%Base)
3005 // # fall through to LoopMMB
3007 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
3008 .addOperand(Base).addImm(Disp).addReg(0);
3009 MBB->addSuccessor(LoopMBB);
3012 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
3013 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
3014 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
3015 // %Dest = RLL %OldVal, BitSize(%BitShift)
3016 // ^^ The low BitSize bits contain the field
3018 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
3019 // ^^ Replace the upper 32-BitSize bits of the
3020 // comparison value with those that we loaded,
3021 // so that we can use a full word comparison.
3022 // CR %Dest, %RetryCmpVal
3024 // # Fall through to SetMBB
3026 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
3027 .addReg(OrigOldVal).addMBB(StartMBB)
3028 .addReg(RetryOldVal).addMBB(SetMBB);
3029 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
3030 .addReg(OrigCmpVal).addMBB(StartMBB)
3031 .addReg(RetryCmpVal).addMBB(SetMBB);
3032 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
3033 .addReg(OrigSwapVal).addMBB(StartMBB)
3034 .addReg(RetrySwapVal).addMBB(SetMBB);
3035 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
3036 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
3037 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
3038 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
3039 BuildMI(MBB, DL, TII->get(SystemZ::CR))
3040 .addReg(Dest).addReg(RetryCmpVal);
3041 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3042 .addImm(SystemZ::CCMASK_ICMP)
3043 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
3044 MBB->addSuccessor(DoneMBB);
3045 MBB->addSuccessor(SetMBB);
3048 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
3049 // ^^ Replace the upper 32-BitSize bits of the new
3050 // value with those that we loaded.
3051 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
3052 // ^^ Rotate the new field to its proper position.
3053 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
3055 // # fall through to ExitMMB
3057 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
3058 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
3059 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
3060 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
3061 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
3062 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
3063 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3064 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
3065 MBB->addSuccessor(LoopMBB);
3066 MBB->addSuccessor(DoneMBB);
3068 MI->eraseFromParent();
3072 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
3073 // if the high register of the GR128 value must be cleared or false if
3074 // it's "don't care". SubReg is subreg_l32 when extending a GR32
3075 // and subreg_l64 when extending a GR64.
3077 SystemZTargetLowering::emitExt128(MachineInstr *MI,
3078 MachineBasicBlock *MBB,
3079 bool ClearEven, unsigned SubReg) const {
3080 MachineFunction &MF = *MBB->getParent();
3081 const SystemZInstrInfo *TII =
3082 static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
3083 MachineRegisterInfo &MRI = MF.getRegInfo();
3084 DebugLoc DL = MI->getDebugLoc();
3086 unsigned Dest = MI->getOperand(0).getReg();
3087 unsigned Src = MI->getOperand(1).getReg();
3088 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
3090 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
3092 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
3093 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
3095 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
3097 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
3098 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
3101 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
3102 .addReg(In128).addReg(Src).addImm(SubReg);
3104 MI->eraseFromParent();
3109 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
3110 MachineBasicBlock *MBB,
3111 unsigned Opcode) const {
3112 MachineFunction &MF = *MBB->getParent();
3113 const SystemZInstrInfo *TII =
3114 static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
3115 MachineRegisterInfo &MRI = MF.getRegInfo();
3116 DebugLoc DL = MI->getDebugLoc();
3118 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
3119 uint64_t DestDisp = MI->getOperand(1).getImm();
3120 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
3121 uint64_t SrcDisp = MI->getOperand(3).getImm();
3122 uint64_t Length = MI->getOperand(4).getImm();
3124 // When generating more than one CLC, all but the last will need to
3125 // branch to the end when a difference is found.
3126 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
3127 splitBlockAfter(MI, MBB) : nullptr);
3129 // Check for the loop form, in which operand 5 is the trip count.
3130 if (MI->getNumExplicitOperands() > 5) {
3131 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
3133 uint64_t StartCountReg = MI->getOperand(5).getReg();
3134 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
3135 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
3136 forceReg(MI, DestBase, TII));
3138 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
3139 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
3140 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
3141 MRI.createVirtualRegister(RC));
3142 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
3143 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
3144 MRI.createVirtualRegister(RC));
3146 RC = &SystemZ::GR64BitRegClass;
3147 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
3148 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
3150 MachineBasicBlock *StartMBB = MBB;
3151 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3152 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3153 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
3156 // # fall through to LoopMMB
3157 MBB->addSuccessor(LoopMBB);
3160 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
3161 // [ %NextDestReg, NextMBB ]
3162 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
3163 // [ %NextSrcReg, NextMBB ]
3164 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
3165 // [ %NextCountReg, NextMBB ]
3166 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
3167 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
3170 // The prefetch is used only for MVC. The JLH is used only for CLC.
3173 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
3174 .addReg(StartDestReg).addMBB(StartMBB)
3175 .addReg(NextDestReg).addMBB(NextMBB);
3176 if (!HaveSingleBase)
3177 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
3178 .addReg(StartSrcReg).addMBB(StartMBB)
3179 .addReg(NextSrcReg).addMBB(NextMBB);
3180 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
3181 .addReg(StartCountReg).addMBB(StartMBB)
3182 .addReg(NextCountReg).addMBB(NextMBB);
3183 if (Opcode == SystemZ::MVC)
3184 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
3185 .addImm(SystemZ::PFD_WRITE)
3186 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
3187 BuildMI(MBB, DL, TII->get(Opcode))
3188 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
3189 .addReg(ThisSrcReg).addImm(SrcDisp);
3191 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3192 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3194 MBB->addSuccessor(EndMBB);
3195 MBB->addSuccessor(NextMBB);
3199 // %NextDestReg = LA 256(%ThisDestReg)
3200 // %NextSrcReg = LA 256(%ThisSrcReg)
3201 // %NextCountReg = AGHI %ThisCountReg, -1
3202 // CGHI %NextCountReg, 0
3204 // # fall through to DoneMMB
3206 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
3209 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
3210 .addReg(ThisDestReg).addImm(256).addReg(0);
3211 if (!HaveSingleBase)
3212 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
3213 .addReg(ThisSrcReg).addImm(256).addReg(0);
3214 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
3215 .addReg(ThisCountReg).addImm(-1);
3216 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
3217 .addReg(NextCountReg).addImm(0);
3218 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3219 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3221 MBB->addSuccessor(LoopMBB);
3222 MBB->addSuccessor(DoneMBB);
3224 DestBase = MachineOperand::CreateReg(NextDestReg, false);
3225 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
3229 // Handle any remaining bytes with straight-line code.
3230 while (Length > 0) {
3231 uint64_t ThisLength = std::min(Length, uint64_t(256));
3232 // The previous iteration might have created out-of-range displacements.
3233 // Apply them using LAY if so.
3234 if (!isUInt<12>(DestDisp)) {
3235 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3236 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
3237 .addOperand(DestBase).addImm(DestDisp).addReg(0);
3238 DestBase = MachineOperand::CreateReg(Reg, false);
3241 if (!isUInt<12>(SrcDisp)) {
3242 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3243 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
3244 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
3245 SrcBase = MachineOperand::CreateReg(Reg, false);
3248 BuildMI(*MBB, MI, DL, TII->get(Opcode))
3249 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
3250 .addOperand(SrcBase).addImm(SrcDisp);
3251 DestDisp += ThisLength;
3252 SrcDisp += ThisLength;
3253 Length -= ThisLength;
3254 // If there's another CLC to go, branch to the end if a difference
3256 if (EndMBB && Length > 0) {
3257 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
3258 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3259 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3261 MBB->addSuccessor(EndMBB);
3262 MBB->addSuccessor(NextMBB);
3267 MBB->addSuccessor(EndMBB);
3269 MBB->addLiveIn(SystemZ::CC);
3272 MI->eraseFromParent();
3276 // Decompose string pseudo-instruction MI into a loop that continually performs
3277 // Opcode until CC != 3.
3279 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
3280 MachineBasicBlock *MBB,
3281 unsigned Opcode) const {
3282 MachineFunction &MF = *MBB->getParent();
3283 const SystemZInstrInfo *TII =
3284 static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
3285 MachineRegisterInfo &MRI = MF.getRegInfo();
3286 DebugLoc DL = MI->getDebugLoc();
3288 uint64_t End1Reg = MI->getOperand(0).getReg();
3289 uint64_t Start1Reg = MI->getOperand(1).getReg();
3290 uint64_t Start2Reg = MI->getOperand(2).getReg();
3291 uint64_t CharReg = MI->getOperand(3).getReg();
3293 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
3294 uint64_t This1Reg = MRI.createVirtualRegister(RC);
3295 uint64_t This2Reg = MRI.createVirtualRegister(RC);
3296 uint64_t End2Reg = MRI.createVirtualRegister(RC);
3298 MachineBasicBlock *StartMBB = MBB;
3299 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3300 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3303 // # fall through to LoopMMB
3304 MBB->addSuccessor(LoopMBB);
3307 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
3308 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
3310 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
3312 // # fall through to DoneMMB
3314 // The load of R0L can be hoisted by post-RA LICM.
3317 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
3318 .addReg(Start1Reg).addMBB(StartMBB)
3319 .addReg(End1Reg).addMBB(LoopMBB);
3320 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
3321 .addReg(Start2Reg).addMBB(StartMBB)
3322 .addReg(End2Reg).addMBB(LoopMBB);
3323 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
3324 BuildMI(MBB, DL, TII->get(Opcode))
3325 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
3326 .addReg(This1Reg).addReg(This2Reg);
3327 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3328 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
3329 MBB->addSuccessor(LoopMBB);
3330 MBB->addSuccessor(DoneMBB);
3332 DoneMBB->addLiveIn(SystemZ::CC);
3334 MI->eraseFromParent();
3338 MachineBasicBlock *SystemZTargetLowering::
3339 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
3340 switch (MI->getOpcode()) {
3341 case SystemZ::Select32Mux:
3342 case SystemZ::Select32:
3343 case SystemZ::SelectF32:
3344 case SystemZ::Select64:
3345 case SystemZ::SelectF64:
3346 case SystemZ::SelectF128:
3347 return emitSelect(MI, MBB);
3349 case SystemZ::CondStore8Mux:
3350 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
3351 case SystemZ::CondStore8MuxInv:
3352 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
3353 case SystemZ::CondStore16Mux:
3354 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
3355 case SystemZ::CondStore16MuxInv:
3356 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
3357 case SystemZ::CondStore8:
3358 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
3359 case SystemZ::CondStore8Inv:
3360 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
3361 case SystemZ::CondStore16:
3362 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
3363 case SystemZ::CondStore16Inv:
3364 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
3365 case SystemZ::CondStore32:
3366 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
3367 case SystemZ::CondStore32Inv:
3368 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
3369 case SystemZ::CondStore64:
3370 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
3371 case SystemZ::CondStore64Inv:
3372 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
3373 case SystemZ::CondStoreF32:
3374 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
3375 case SystemZ::CondStoreF32Inv:
3376 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
3377 case SystemZ::CondStoreF64:
3378 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
3379 case SystemZ::CondStoreF64Inv:
3380 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
3382 case SystemZ::AEXT128_64:
3383 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
3384 case SystemZ::ZEXT128_32:
3385 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
3386 case SystemZ::ZEXT128_64:
3387 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
3389 case SystemZ::ATOMIC_SWAPW:
3390 return emitAtomicLoadBinary(MI, MBB, 0, 0);
3391 case SystemZ::ATOMIC_SWAP_32:
3392 return emitAtomicLoadBinary(MI, MBB, 0, 32);
3393 case SystemZ::ATOMIC_SWAP_64:
3394 return emitAtomicLoadBinary(MI, MBB, 0, 64);
3396 case SystemZ::ATOMIC_LOADW_AR:
3397 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
3398 case SystemZ::ATOMIC_LOADW_AFI:
3399 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
3400 case SystemZ::ATOMIC_LOAD_AR:
3401 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
3402 case SystemZ::ATOMIC_LOAD_AHI:
3403 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
3404 case SystemZ::ATOMIC_LOAD_AFI:
3405 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
3406 case SystemZ::ATOMIC_LOAD_AGR:
3407 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
3408 case SystemZ::ATOMIC_LOAD_AGHI:
3409 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
3410 case SystemZ::ATOMIC_LOAD_AGFI:
3411 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
3413 case SystemZ::ATOMIC_LOADW_SR:
3414 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
3415 case SystemZ::ATOMIC_LOAD_SR:
3416 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
3417 case SystemZ::ATOMIC_LOAD_SGR:
3418 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
3420 case SystemZ::ATOMIC_LOADW_NR:
3421 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
3422 case SystemZ::ATOMIC_LOADW_NILH:
3423 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
3424 case SystemZ::ATOMIC_LOAD_NR:
3425 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
3426 case SystemZ::ATOMIC_LOAD_NILL:
3427 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
3428 case SystemZ::ATOMIC_LOAD_NILH:
3429 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
3430 case SystemZ::ATOMIC_LOAD_NILF:
3431 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
3432 case SystemZ::ATOMIC_LOAD_NGR:
3433 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
3434 case SystemZ::ATOMIC_LOAD_NILL64:
3435 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
3436 case SystemZ::ATOMIC_LOAD_NILH64:
3437 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
3438 case SystemZ::ATOMIC_LOAD_NIHL64:
3439 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
3440 case SystemZ::ATOMIC_LOAD_NIHH64:
3441 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
3442 case SystemZ::ATOMIC_LOAD_NILF64:
3443 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
3444 case SystemZ::ATOMIC_LOAD_NIHF64:
3445 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
3447 case SystemZ::ATOMIC_LOADW_OR:
3448 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
3449 case SystemZ::ATOMIC_LOADW_OILH:
3450 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
3451 case SystemZ::ATOMIC_LOAD_OR:
3452 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
3453 case SystemZ::ATOMIC_LOAD_OILL:
3454 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
3455 case SystemZ::ATOMIC_LOAD_OILH:
3456 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
3457 case SystemZ::ATOMIC_LOAD_OILF:
3458 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
3459 case SystemZ::ATOMIC_LOAD_OGR:
3460 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
3461 case SystemZ::ATOMIC_LOAD_OILL64:
3462 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
3463 case SystemZ::ATOMIC_LOAD_OILH64:
3464 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
3465 case SystemZ::ATOMIC_LOAD_OIHL64:
3466 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
3467 case SystemZ::ATOMIC_LOAD_OIHH64:
3468 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
3469 case SystemZ::ATOMIC_LOAD_OILF64:
3470 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
3471 case SystemZ::ATOMIC_LOAD_OIHF64:
3472 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
3474 case SystemZ::ATOMIC_LOADW_XR:
3475 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
3476 case SystemZ::ATOMIC_LOADW_XILF:
3477 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
3478 case SystemZ::ATOMIC_LOAD_XR:
3479 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
3480 case SystemZ::ATOMIC_LOAD_XILF:
3481 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
3482 case SystemZ::ATOMIC_LOAD_XGR:
3483 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
3484 case SystemZ::ATOMIC_LOAD_XILF64:
3485 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
3486 case SystemZ::ATOMIC_LOAD_XIHF64:
3487 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
3489 case SystemZ::ATOMIC_LOADW_NRi:
3490 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
3491 case SystemZ::ATOMIC_LOADW_NILHi:
3492 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
3493 case SystemZ::ATOMIC_LOAD_NRi:
3494 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
3495 case SystemZ::ATOMIC_LOAD_NILLi:
3496 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
3497 case SystemZ::ATOMIC_LOAD_NILHi:
3498 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
3499 case SystemZ::ATOMIC_LOAD_NILFi:
3500 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
3501 case SystemZ::ATOMIC_LOAD_NGRi:
3502 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
3503 case SystemZ::ATOMIC_LOAD_NILL64i:
3504 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
3505 case SystemZ::ATOMIC_LOAD_NILH64i:
3506 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
3507 case SystemZ::ATOMIC_LOAD_NIHL64i:
3508 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
3509 case SystemZ::ATOMIC_LOAD_NIHH64i:
3510 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
3511 case SystemZ::ATOMIC_LOAD_NILF64i:
3512 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
3513 case SystemZ::ATOMIC_LOAD_NIHF64i:
3514 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
3516 case SystemZ::ATOMIC_LOADW_MIN:
3517 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3518 SystemZ::CCMASK_CMP_LE, 0);
3519 case SystemZ::ATOMIC_LOAD_MIN_32:
3520 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3521 SystemZ::CCMASK_CMP_LE, 32);
3522 case SystemZ::ATOMIC_LOAD_MIN_64:
3523 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3524 SystemZ::CCMASK_CMP_LE, 64);
3526 case SystemZ::ATOMIC_LOADW_MAX:
3527 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3528 SystemZ::CCMASK_CMP_GE, 0);
3529 case SystemZ::ATOMIC_LOAD_MAX_32:
3530 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3531 SystemZ::CCMASK_CMP_GE, 32);
3532 case SystemZ::ATOMIC_LOAD_MAX_64:
3533 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3534 SystemZ::CCMASK_CMP_GE, 64);
3536 case SystemZ::ATOMIC_LOADW_UMIN:
3537 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3538 SystemZ::CCMASK_CMP_LE, 0);
3539 case SystemZ::ATOMIC_LOAD_UMIN_32:
3540 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3541 SystemZ::CCMASK_CMP_LE, 32);
3542 case SystemZ::ATOMIC_LOAD_UMIN_64:
3543 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3544 SystemZ::CCMASK_CMP_LE, 64);
3546 case SystemZ::ATOMIC_LOADW_UMAX:
3547 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3548 SystemZ::CCMASK_CMP_GE, 0);
3549 case SystemZ::ATOMIC_LOAD_UMAX_32:
3550 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3551 SystemZ::CCMASK_CMP_GE, 32);
3552 case SystemZ::ATOMIC_LOAD_UMAX_64:
3553 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3554 SystemZ::CCMASK_CMP_GE, 64);
3556 case SystemZ::ATOMIC_CMP_SWAPW:
3557 return emitAtomicCmpSwapW(MI, MBB);
3558 case SystemZ::MVCSequence:
3559 case SystemZ::MVCLoop:
3560 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
3561 case SystemZ::NCSequence:
3562 case SystemZ::NCLoop:
3563 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
3564 case SystemZ::OCSequence:
3565 case SystemZ::OCLoop:
3566 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
3567 case SystemZ::XCSequence:
3568 case SystemZ::XCLoop:
3569 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
3570 case SystemZ::CLCSequence:
3571 case SystemZ::CLCLoop:
3572 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
3573 case SystemZ::CLSTLoop:
3574 return emitStringWrapper(MI, MBB, SystemZ::CLST);
3575 case SystemZ::MVSTLoop:
3576 return emitStringWrapper(MI, MBB, SystemZ::MVST);
3577 case SystemZ::SRSTLoop:
3578 return emitStringWrapper(MI, MBB, SystemZ::SRST);
3580 llvm_unreachable("Unexpected instr type to insert");