1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/MC/MCTargetAsmParser.h"
21 #include "llvm/Support/TargetRegistry.h"
25 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
26 // namespace. But SPARC backend uses "SP" as its namespace.
35 class SparcAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
48 // public interface of the MCTargetAsmParser.
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 OperandVector &Operands, MCStreamer &Out,
52 bool MatchingInlineAsm) override;
53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
54 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
55 SMLoc NameLoc, OperandVector &Operands) override;
56 bool ParseDirective(AsmToken DirectiveID) override;
58 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
59 unsigned Kind) override;
61 // Custom parse functions for Sparc specific operands.
62 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
64 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
67 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
70 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
72 // returns true if Tok is matched to a register and returns register in RegNo.
73 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
76 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
77 bool parseDirectiveWord(unsigned Size, SMLoc L);
79 bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
81 void expandSET(MCInst &Inst, SMLoc IDLoc,
82 SmallVectorImpl<MCInst> &Instructions);
85 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
86 const MCInstrInfo &MII,
87 const MCTargetOptions &Options)
88 : MCTargetAsmParser(), STI(sti), Parser(parser) {
89 // Initialize the set of available features.
90 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
95 static unsigned IntRegs[32] = {
96 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
97 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
98 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
99 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
100 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
101 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
102 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
103 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
105 static unsigned FloatRegs[32] = {
106 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
107 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
108 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
109 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
110 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
111 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
112 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
113 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
115 static unsigned DoubleRegs[32] = {
116 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
117 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
118 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
119 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
120 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
121 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
122 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
123 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
125 static unsigned QuadFPRegs[32] = {
126 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
127 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
128 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
129 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
131 static unsigned ASRRegs[32] = {
132 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
133 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
134 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
135 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
136 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
137 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
138 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
139 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
141 /// SparcOperand - Instances of this class represent a parsed Sparc machine
143 class SparcOperand : public MCParsedAsmOperand {
163 SMLoc StartLoc, EndLoc;
192 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
194 bool isToken() const override { return Kind == k_Token; }
195 bool isReg() const override { return Kind == k_Register; }
196 bool isImm() const override { return Kind == k_Immediate; }
197 bool isMem() const override { return isMEMrr() || isMEMri(); }
198 bool isMEMrr() const { return Kind == k_MemoryReg; }
199 bool isMEMri() const { return Kind == k_MemoryImm; }
201 bool isFloatReg() const {
202 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
205 bool isFloatOrDoubleReg() const {
206 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
207 || Reg.Kind == rk_DoubleReg));
211 StringRef getToken() const {
212 assert(Kind == k_Token && "Invalid access!");
213 return StringRef(Tok.Data, Tok.Length);
216 unsigned getReg() const override {
217 assert((Kind == k_Register) && "Invalid access!");
221 const MCExpr *getImm() const {
222 assert((Kind == k_Immediate) && "Invalid access!");
226 unsigned getMemBase() const {
227 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
231 unsigned getMemOffsetReg() const {
232 assert((Kind == k_MemoryReg) && "Invalid access!");
233 return Mem.OffsetReg;
236 const MCExpr *getMemOff() const {
237 assert((Kind == k_MemoryImm) && "Invalid access!");
241 /// getStartLoc - Get the location of the first token of this operand.
242 SMLoc getStartLoc() const override {
245 /// getEndLoc - Get the location of the last token of this operand.
246 SMLoc getEndLoc() const override {
250 void print(raw_ostream &OS) const override {
252 case k_Token: OS << "Token: " << getToken() << "\n"; break;
253 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
254 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
255 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
256 << getMemOffsetReg() << "\n"; break;
257 case k_MemoryImm: assert(getMemOff() != nullptr);
258 OS << "Mem: " << getMemBase()
259 << "+" << *getMemOff()
264 void addRegOperands(MCInst &Inst, unsigned N) const {
265 assert(N == 1 && "Invalid number of operands!");
266 Inst.addOperand(MCOperand::createReg(getReg()));
269 void addImmOperands(MCInst &Inst, unsigned N) const {
270 assert(N == 1 && "Invalid number of operands!");
271 const MCExpr *Expr = getImm();
275 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
276 // Add as immediate when possible. Null MCExpr = 0.
278 Inst.addOperand(MCOperand::createImm(0));
279 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
280 Inst.addOperand(MCOperand::createImm(CE->getValue()));
282 Inst.addOperand(MCOperand::createExpr(Expr));
285 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
286 assert(N == 2 && "Invalid number of operands!");
288 Inst.addOperand(MCOperand::createReg(getMemBase()));
290 assert(getMemOffsetReg() != 0 && "Invalid offset");
291 Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
294 void addMEMriOperands(MCInst &Inst, unsigned N) const {
295 assert(N == 2 && "Invalid number of operands!");
297 Inst.addOperand(MCOperand::createReg(getMemBase()));
299 const MCExpr *Expr = getMemOff();
303 static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
304 auto Op = make_unique<SparcOperand>(k_Token);
305 Op->Tok.Data = Str.data();
306 Op->Tok.Length = Str.size();
312 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
314 auto Op = make_unique<SparcOperand>(k_Register);
315 Op->Reg.RegNum = RegNum;
316 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
322 static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S,
324 auto Op = make_unique<SparcOperand>(k_Immediate);
331 static bool MorphToDoubleReg(SparcOperand &Op) {
332 unsigned Reg = Op.getReg();
333 assert(Op.Reg.Kind == rk_FloatReg);
334 unsigned regIdx = Reg - Sparc::F0;
335 if (regIdx % 2 || regIdx > 31)
337 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
338 Op.Reg.Kind = rk_DoubleReg;
342 static bool MorphToQuadReg(SparcOperand &Op) {
343 unsigned Reg = Op.getReg();
345 switch (Op.Reg.Kind) {
346 default: llvm_unreachable("Unexpected register kind!");
348 regIdx = Reg - Sparc::F0;
349 if (regIdx % 4 || regIdx > 31)
351 Reg = QuadFPRegs[regIdx / 4];
354 regIdx = Reg - Sparc::D0;
355 if (regIdx % 2 || regIdx > 31)
357 Reg = QuadFPRegs[regIdx / 2];
361 Op.Reg.Kind = rk_QuadReg;
365 static std::unique_ptr<SparcOperand>
366 MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
367 unsigned offsetReg = Op->getReg();
368 Op->Kind = k_MemoryReg;
370 Op->Mem.OffsetReg = offsetReg;
371 Op->Mem.Off = nullptr;
375 static std::unique_ptr<SparcOperand>
376 CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
377 auto Op = make_unique<SparcOperand>(k_MemoryReg);
379 Op->Mem.OffsetReg = Sparc::G0; // always 0
380 Op->Mem.Off = nullptr;
386 static std::unique_ptr<SparcOperand>
387 MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
388 const MCExpr *Imm = Op->getImm();
389 Op->Kind = k_MemoryImm;
391 Op->Mem.OffsetReg = 0;
399 void SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
400 SmallVectorImpl<MCInst> &Instructions) {
401 MCOperand MCRegOp = Inst.getOperand(0);
402 MCOperand MCValOp = Inst.getOperand(1);
403 assert(MCRegOp.isReg());
404 assert(MCValOp.isImm() || MCValOp.isExpr());
406 // the imm operand can be either an expression or an immediate.
407 bool IsImm = Inst.getOperand(1).isImm();
408 uint64_t ImmValue = IsImm ? MCValOp.getImm() : 0;
409 const MCExpr *ValExpr;
411 ValExpr = MCConstantExpr::Create(ImmValue, getContext());
413 ValExpr = MCValOp.getExpr();
415 MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
417 if (!IsImm || (ImmValue & ~0x1fff)) {
420 SparcMCExpr::Create(SparcMCExpr::VK_Sparc_HI, ValExpr, getContext());
421 TmpInst.setLoc(IDLoc);
422 TmpInst.setOpcode(SP::SETHIi);
423 TmpInst.addOperand(MCRegOp);
424 TmpInst.addOperand(MCOperand::createExpr(Expr));
425 Instructions.push_back(TmpInst);
429 if (!IsImm || ((ImmValue & 0x1fff) != 0 || ImmValue == 0)) {
432 SparcMCExpr::Create(SparcMCExpr::VK_Sparc_LO, ValExpr, getContext());
433 TmpInst.setLoc(IDLoc);
434 TmpInst.setOpcode(SP::ORri);
435 TmpInst.addOperand(MCRegOp);
436 TmpInst.addOperand(PrevReg);
437 TmpInst.addOperand(MCOperand::createExpr(Expr));
438 Instructions.push_back(TmpInst);
442 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
443 OperandVector &Operands,
446 bool MatchingInlineAsm) {
448 SmallVector<MCInst, 8> Instructions;
449 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
451 switch (MatchResult) {
452 case Match_Success: {
453 switch (Inst.getOpcode()) {
456 Instructions.push_back(Inst);
459 expandSET(Inst, IDLoc, Instructions);
463 for (const MCInst &I : Instructions) {
464 Out.EmitInstruction(I, STI);
469 case Match_MissingFeature:
471 "instruction requires a CPU feature not currently enabled");
473 case Match_InvalidOperand: {
474 SMLoc ErrorLoc = IDLoc;
475 if (ErrorInfo != ~0ULL) {
476 if (ErrorInfo >= Operands.size())
477 return Error(IDLoc, "too few operands for instruction");
479 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
480 if (ErrorLoc == SMLoc())
484 return Error(ErrorLoc, "invalid operand for instruction");
486 case Match_MnemonicFail:
487 return Error(IDLoc, "invalid instruction mnemonic");
489 llvm_unreachable("Implement any new match types added!");
492 bool SparcAsmParser::
493 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
495 const AsmToken &Tok = Parser.getTok();
496 StartLoc = Tok.getLoc();
497 EndLoc = Tok.getEndLoc();
499 if (getLexer().getKind() != AsmToken::Percent)
502 unsigned regKind = SparcOperand::rk_None;
503 if (matchRegisterName(Tok, RegNo, regKind)) {
508 return Error(StartLoc, "invalid register name");
511 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
514 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
515 StringRef Name, SMLoc NameLoc,
516 OperandVector &Operands) {
518 // First operand in MCInst is instruction mnemonic.
519 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
521 // apply mnemonic aliases, if any, so that we can parse operands correctly.
522 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
524 if (getLexer().isNot(AsmToken::EndOfStatement)) {
525 // Read the first operand.
526 if (getLexer().is(AsmToken::Comma)) {
527 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
528 SMLoc Loc = getLexer().getLoc();
529 Parser.eatToEndOfStatement();
530 return Error(Loc, "unexpected token");
533 if (parseOperand(Operands, Name) != MatchOperand_Success) {
534 SMLoc Loc = getLexer().getLoc();
535 Parser.eatToEndOfStatement();
536 return Error(Loc, "unexpected token");
539 while (getLexer().is(AsmToken::Comma)) {
540 Parser.Lex(); // Eat the comma.
541 // Parse and remember the operand.
542 if (parseOperand(Operands, Name) != MatchOperand_Success) {
543 SMLoc Loc = getLexer().getLoc();
544 Parser.eatToEndOfStatement();
545 return Error(Loc, "unexpected token");
549 if (getLexer().isNot(AsmToken::EndOfStatement)) {
550 SMLoc Loc = getLexer().getLoc();
551 Parser.eatToEndOfStatement();
552 return Error(Loc, "unexpected token");
554 Parser.Lex(); // Consume the EndOfStatement.
558 bool SparcAsmParser::
559 ParseDirective(AsmToken DirectiveID)
561 StringRef IDVal = DirectiveID.getString();
563 if (IDVal == ".byte")
564 return parseDirectiveWord(1, DirectiveID.getLoc());
566 if (IDVal == ".half")
567 return parseDirectiveWord(2, DirectiveID.getLoc());
569 if (IDVal == ".word")
570 return parseDirectiveWord(4, DirectiveID.getLoc());
572 if (IDVal == ".nword")
573 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
575 if (is64Bit() && IDVal == ".xword")
576 return parseDirectiveWord(8, DirectiveID.getLoc());
578 if (IDVal == ".register") {
579 // For now, ignore .register directive.
580 Parser.eatToEndOfStatement();
584 // Let the MC layer to handle other directives.
588 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
589 if (getLexer().isNot(AsmToken::EndOfStatement)) {
592 if (getParser().parseExpression(Value))
595 getParser().getStreamer().EmitValue(Value, Size);
597 if (getLexer().is(AsmToken::EndOfStatement))
600 // FIXME: Improve diagnostic.
601 if (getLexer().isNot(AsmToken::Comma))
602 return Error(L, "unexpected token in directive");
610 SparcAsmParser::OperandMatchResultTy
611 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
614 unsigned BaseReg = 0;
616 if (ParseRegister(BaseReg, S, E)) {
617 return MatchOperand_NoMatch;
620 switch (getLexer().getKind()) {
621 default: return MatchOperand_NoMatch;
623 case AsmToken::Comma:
624 case AsmToken::RBrac:
625 case AsmToken::EndOfStatement:
626 Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
627 return MatchOperand_Success;
629 case AsmToken:: Plus:
630 Parser.Lex(); // Eat the '+'
632 case AsmToken::Minus:
636 std::unique_ptr<SparcOperand> Offset;
637 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
638 if (ResTy != MatchOperand_Success || !Offset)
639 return MatchOperand_NoMatch;
642 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
643 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
645 return MatchOperand_Success;
648 SparcAsmParser::OperandMatchResultTy
649 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
651 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
653 // If there wasn't a custom match, try the generic matcher below. Otherwise,
654 // there was a match, but an error occurred, in which case, just return that
655 // the operand parsing failed.
656 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
659 if (getLexer().is(AsmToken::LBrac)) {
661 Operands.push_back(SparcOperand::CreateToken("[",
662 Parser.getTok().getLoc()));
663 Parser.Lex(); // Eat the [
665 if (Mnemonic == "cas" || Mnemonic == "casx") {
666 SMLoc S = Parser.getTok().getLoc();
667 if (getLexer().getKind() != AsmToken::Percent)
668 return MatchOperand_NoMatch;
669 Parser.Lex(); // eat %
671 unsigned RegNo, RegKind;
672 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
673 return MatchOperand_NoMatch;
675 Parser.Lex(); // Eat the identifier token.
676 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
677 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
678 ResTy = MatchOperand_Success;
680 ResTy = parseMEMOperand(Operands);
683 if (ResTy != MatchOperand_Success)
686 if (!getLexer().is(AsmToken::RBrac))
687 return MatchOperand_ParseFail;
689 Operands.push_back(SparcOperand::CreateToken("]",
690 Parser.getTok().getLoc()));
691 Parser.Lex(); // Eat the ]
693 // Parse an optional address-space identifier after the address.
694 if (getLexer().is(AsmToken::Integer)) {
695 std::unique_ptr<SparcOperand> Op;
696 ResTy = parseSparcAsmOperand(Op, false);
697 if (ResTy != MatchOperand_Success || !Op)
698 return MatchOperand_ParseFail;
699 Operands.push_back(std::move(Op));
701 return MatchOperand_Success;
704 std::unique_ptr<SparcOperand> Op;
706 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
707 if (ResTy != MatchOperand_Success || !Op)
708 return MatchOperand_ParseFail;
710 // Push the parsed operand into the list of operands
711 Operands.push_back(std::move(Op));
713 return MatchOperand_Success;
716 SparcAsmParser::OperandMatchResultTy
717 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
720 SMLoc S = Parser.getTok().getLoc();
721 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
725 switch (getLexer().getKind()) {
728 case AsmToken::Percent:
729 Parser.Lex(); // Eat the '%'.
732 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
733 StringRef name = Parser.getTok().getString();
734 Parser.Lex(); // Eat the identifier token.
735 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
738 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
741 Op = SparcOperand::CreateToken("%psr", S);
744 Op = SparcOperand::CreateToken("%wim", S);
747 Op = SparcOperand::CreateToken("%tbr", S);
751 Op = SparcOperand::CreateToken("%xcc", S);
753 Op = SparcOperand::CreateToken("%icc", S);
758 if (matchSparcAsmModifiers(EVal, E)) {
759 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
760 Op = SparcOperand::CreateImm(EVal, S, E);
764 case AsmToken::Minus:
765 case AsmToken::Integer:
766 case AsmToken::LParen:
767 if (!getParser().parseExpression(EVal, E))
768 Op = SparcOperand::CreateImm(EVal, S, E);
771 case AsmToken::Identifier: {
772 StringRef Identifier;
773 if (!getParser().parseIdentifier(Identifier)) {
774 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
775 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
777 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
780 getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
781 Res = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_WPLT30, Res,
783 Op = SparcOperand::CreateImm(Res, S, E);
788 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
791 SparcAsmParser::OperandMatchResultTy
792 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
794 // parse (,a|,pn|,pt)+
796 while (getLexer().is(AsmToken::Comma)) {
798 Parser.Lex(); // Eat the comma
800 if (!getLexer().is(AsmToken::Identifier))
801 return MatchOperand_ParseFail;
802 StringRef modName = Parser.getTok().getString();
803 if (modName == "a" || modName == "pn" || modName == "pt") {
804 Operands.push_back(SparcOperand::CreateToken(modName,
805 Parser.getTok().getLoc()));
806 Parser.Lex(); // eat the identifier.
809 return MatchOperand_Success;
812 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
818 RegKind = SparcOperand::rk_None;
819 if (Tok.is(AsmToken::Identifier)) {
820 StringRef name = Tok.getString();
823 if (name.equals("fp")) {
825 RegKind = SparcOperand::rk_IntReg;
829 if (name.equals("sp")) {
831 RegKind = SparcOperand::rk_IntReg;
835 if (name.equals("y")) {
837 RegKind = SparcOperand::rk_Special;
841 if (name.substr(0, 3).equals_lower("asr")
842 && !name.substr(3).getAsInteger(10, intVal)
843 && intVal > 0 && intVal < 32) {
844 RegNo = ASRRegs[intVal];
845 RegKind = SparcOperand::rk_Special;
849 if (name.equals("icc")) {
851 RegKind = SparcOperand::rk_Special;
855 if (name.equals("psr")) {
857 RegKind = SparcOperand::rk_Special;
861 if (name.equals("wim")) {
863 RegKind = SparcOperand::rk_Special;
867 if (name.equals("tbr")) {
869 RegKind = SparcOperand::rk_Special;
873 if (name.equals("xcc")) {
874 // FIXME:: check 64bit.
876 RegKind = SparcOperand::rk_Special;
881 if (name.substr(0, 3).equals_lower("fcc")
882 && !name.substr(3).getAsInteger(10, intVal)
884 // FIXME: check 64bit and handle %fcc1 - %fcc3
885 RegNo = Sparc::FCC0 + intVal;
886 RegKind = SparcOperand::rk_Special;
891 if (name.substr(0, 1).equals_lower("g")
892 && !name.substr(1).getAsInteger(10, intVal)
894 RegNo = IntRegs[intVal];
895 RegKind = SparcOperand::rk_IntReg;
899 if (name.substr(0, 1).equals_lower("o")
900 && !name.substr(1).getAsInteger(10, intVal)
902 RegNo = IntRegs[8 + intVal];
903 RegKind = SparcOperand::rk_IntReg;
906 if (name.substr(0, 1).equals_lower("l")
907 && !name.substr(1).getAsInteger(10, intVal)
909 RegNo = IntRegs[16 + intVal];
910 RegKind = SparcOperand::rk_IntReg;
913 if (name.substr(0, 1).equals_lower("i")
914 && !name.substr(1).getAsInteger(10, intVal)
916 RegNo = IntRegs[24 + intVal];
917 RegKind = SparcOperand::rk_IntReg;
921 if (name.substr(0, 1).equals_lower("f")
922 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
923 RegNo = FloatRegs[intVal];
924 RegKind = SparcOperand::rk_FloatReg;
928 if (name.substr(0, 1).equals_lower("f")
929 && !name.substr(1, 2).getAsInteger(10, intVal)
930 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
932 RegNo = DoubleRegs[intVal/2];
933 RegKind = SparcOperand::rk_DoubleReg;
938 if (name.substr(0, 1).equals_lower("r")
939 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
940 RegNo = IntRegs[intVal];
941 RegKind = SparcOperand::rk_IntReg;
948 static bool hasGOTReference(const MCExpr *Expr) {
949 switch (Expr->getKind()) {
951 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
952 return hasGOTReference(SE->getSubExpr());
955 case MCExpr::Constant:
958 case MCExpr::Binary: {
959 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
960 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
963 case MCExpr::SymbolRef: {
964 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
965 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
969 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
974 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
977 AsmToken Tok = Parser.getTok();
978 if (!Tok.is(AsmToken::Identifier))
981 StringRef name = Tok.getString();
983 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
985 if (VK == SparcMCExpr::VK_Sparc_None)
988 Parser.Lex(); // Eat the identifier.
989 if (Parser.getTok().getKind() != AsmToken::LParen)
992 Parser.Lex(); // Eat the LParen token.
993 const MCExpr *subExpr;
994 if (Parser.parseParenExpression(subExpr, EndLoc))
997 bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
1001 case SparcMCExpr::VK_Sparc_LO:
1002 VK = (hasGOTReference(subExpr)
1003 ? SparcMCExpr::VK_Sparc_PC10
1004 : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
1006 case SparcMCExpr::VK_Sparc_HI:
1007 VK = (hasGOTReference(subExpr)
1008 ? SparcMCExpr::VK_Sparc_PC22
1009 : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
1013 EVal = SparcMCExpr::Create(VK, subExpr, getContext());
1017 extern "C" void LLVMInitializeSparcAsmParser() {
1018 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
1019 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
1020 RegisterMCAsmParser<SparcAsmParser> C(TheSparcelTarget);
1023 #define GET_REGISTER_MATCHER
1024 #define GET_MATCHER_IMPLEMENTATION
1025 #include "SparcGenAsmMatcher.inc"
1027 unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
1029 SparcOperand &Op = (SparcOperand &)GOp;
1030 if (Op.isFloatOrDoubleReg()) {
1034 if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
1035 return MCTargetAsmParser::Match_Success;
1038 if (SparcOperand::MorphToQuadReg(Op))
1039 return MCTargetAsmParser::Match_Success;
1043 return Match_InvalidOperand;