1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/MC/MCTargetAsmParser.h"
21 #include "llvm/Support/TargetRegistry.h"
25 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
26 // namespace. But SPARC backend uses "SP" as its namespace.
35 class SparcAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
48 // public interface of the MCTargetAsmParser.
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
51 MCStreamer &Out, unsigned &ErrorInfo,
52 bool MatchingInlineAsm);
53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
54 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
56 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
57 bool ParseDirective(AsmToken DirectiveID);
59 virtual unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
62 // Custom parse functions for Sparc specific operands.
64 parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
67 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
71 parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false);
74 parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
76 // returns true if Tok is matched to a register and returns register in RegNo.
77 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
80 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
81 bool parseDirectiveWord(unsigned Size, SMLoc L);
83 bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
85 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
86 const MCInstrInfo &MII)
87 : MCTargetAsmParser(), STI(sti), Parser(parser) {
88 // Initialize the set of available features.
89 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
94 static unsigned IntRegs[32] = {
95 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
96 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
97 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
98 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
99 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
100 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
101 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
102 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
104 static unsigned FloatRegs[32] = {
105 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
106 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
107 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
108 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
109 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
110 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
111 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
112 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
114 static unsigned DoubleRegs[32] = {
115 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
116 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
117 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
118 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
119 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
120 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
121 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
122 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
124 static unsigned QuadFPRegs[32] = {
125 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
126 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
127 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
128 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
131 /// SparcOperand - Instances of this class represent a parsed Sparc machine
133 class SparcOperand : public MCParsedAsmOperand {
153 SMLoc StartLoc, EndLoc;
155 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
184 bool isToken() const { return Kind == k_Token; }
185 bool isReg() const { return Kind == k_Register; }
186 bool isImm() const { return Kind == k_Immediate; }
187 bool isMem() const { return isMEMrr() || isMEMri(); }
188 bool isMEMrr() const { return Kind == k_MemoryReg; }
189 bool isMEMri() const { return Kind == k_MemoryImm; }
191 bool isFloatReg() const {
192 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
195 bool isFloatOrDoubleReg() const {
196 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
197 || Reg.Kind == rk_DoubleReg));
201 StringRef getToken() const {
202 assert(Kind == k_Token && "Invalid access!");
203 return StringRef(Tok.Data, Tok.Length);
206 unsigned getReg() const {
207 assert((Kind == k_Register) && "Invalid access!");
211 const MCExpr *getImm() const {
212 assert((Kind == k_Immediate) && "Invalid access!");
216 unsigned getMemBase() const {
217 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
221 unsigned getMemOffsetReg() const {
222 assert((Kind == k_MemoryReg) && "Invalid access!");
223 return Mem.OffsetReg;
226 const MCExpr *getMemOff() const {
227 assert((Kind == k_MemoryImm) && "Invalid access!");
231 /// getStartLoc - Get the location of the first token of this operand.
232 SMLoc getStartLoc() const {
235 /// getEndLoc - Get the location of the last token of this operand.
236 SMLoc getEndLoc() const {
240 virtual void print(raw_ostream &OS) const {
242 case k_Token: OS << "Token: " << getToken() << "\n"; break;
243 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
244 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
245 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
246 << getMemOffsetReg() << "\n"; break;
247 case k_MemoryImm: assert(getMemOff() != 0);
248 OS << "Mem: " << getMemBase()
249 << "+" << *getMemOff()
254 void addRegOperands(MCInst &Inst, unsigned N) const {
255 assert(N == 1 && "Invalid number of operands!");
256 Inst.addOperand(MCOperand::CreateReg(getReg()));
259 void addImmOperands(MCInst &Inst, unsigned N) const {
260 assert(N == 1 && "Invalid number of operands!");
261 const MCExpr *Expr = getImm();
265 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
266 // Add as immediate when possible. Null MCExpr = 0.
268 Inst.addOperand(MCOperand::CreateImm(0));
269 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
270 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
272 Inst.addOperand(MCOperand::CreateExpr(Expr));
275 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
276 assert(N == 2 && "Invalid number of operands!");
278 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
280 assert(getMemOffsetReg() != 0 && "Invalid offset");
281 Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
284 void addMEMriOperands(MCInst &Inst, unsigned N) const {
285 assert(N == 2 && "Invalid number of operands!");
287 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
289 const MCExpr *Expr = getMemOff();
293 static SparcOperand *CreateToken(StringRef Str, SMLoc S) {
294 SparcOperand *Op = new SparcOperand(k_Token);
295 Op->Tok.Data = Str.data();
296 Op->Tok.Length = Str.size();
302 static SparcOperand *CreateReg(unsigned RegNum,
305 SparcOperand *Op = new SparcOperand(k_Register);
306 Op->Reg.RegNum = RegNum;
307 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
313 static SparcOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
314 SparcOperand *Op = new SparcOperand(k_Immediate);
321 static SparcOperand *MorphToDoubleReg(SparcOperand *Op) {
322 unsigned Reg = Op->getReg();
323 assert(Op->Reg.Kind == rk_FloatReg);
324 unsigned regIdx = Reg - Sparc::F0;
325 if (regIdx % 2 || regIdx > 31)
327 Op->Reg.RegNum = DoubleRegs[regIdx / 2];
328 Op->Reg.Kind = rk_DoubleReg;
332 static SparcOperand *MorphToQuadReg(SparcOperand *Op) {
333 unsigned Reg = Op->getReg();
335 switch (Op->Reg.Kind) {
336 default: assert(0 && "Unexpected register kind!");
338 regIdx = Reg - Sparc::F0;
339 if (regIdx % 4 || regIdx > 31)
341 Reg = QuadFPRegs[regIdx / 4];
344 regIdx = Reg - Sparc::D0;
345 if (regIdx % 2 || regIdx > 31)
347 Reg = QuadFPRegs[regIdx / 2];
350 Op->Reg.RegNum = Reg;
351 Op->Reg.Kind = rk_QuadReg;
355 static SparcOperand *MorphToMEMrr(unsigned Base, SparcOperand *Op) {
356 unsigned offsetReg = Op->getReg();
357 Op->Kind = k_MemoryReg;
359 Op->Mem.OffsetReg = offsetReg;
364 static SparcOperand *CreateMEMri(unsigned Base,
367 SparcOperand *Op = new SparcOperand(k_MemoryImm);
369 Op->Mem.OffsetReg = 0;
376 static SparcOperand *MorphToMEMri(unsigned Base, SparcOperand *Op) {
377 const MCExpr *Imm = Op->getImm();
378 Op->Kind = k_MemoryImm;
380 Op->Mem.OffsetReg = 0;
388 bool SparcAsmParser::
389 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
390 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
391 MCStreamer &Out, unsigned &ErrorInfo,
392 bool MatchingInlineAsm) {
394 SmallVector<MCInst, 8> Instructions;
395 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
397 switch (MatchResult) {
401 case Match_Success: {
403 Out.EmitInstruction(Inst, STI);
407 case Match_MissingFeature:
409 "instruction requires a CPU feature not currently enabled");
411 case Match_InvalidOperand: {
412 SMLoc ErrorLoc = IDLoc;
413 if (ErrorInfo != ~0U) {
414 if (ErrorInfo >= Operands.size())
415 return Error(IDLoc, "too few operands for instruction");
417 ErrorLoc = ((SparcOperand*) Operands[ErrorInfo])->getStartLoc();
418 if (ErrorLoc == SMLoc())
422 return Error(ErrorLoc, "invalid operand for instruction");
424 case Match_MnemonicFail:
425 return Error(IDLoc, "invalid instruction mnemonic");
430 bool SparcAsmParser::
431 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
433 const AsmToken &Tok = Parser.getTok();
434 StartLoc = Tok.getLoc();
435 EndLoc = Tok.getEndLoc();
437 if (getLexer().getKind() != AsmToken::Percent)
440 unsigned regKind = SparcOperand::rk_None;
441 if (matchRegisterName(Tok, RegNo, regKind)) {
446 return Error(StartLoc, "invalid register name");
449 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
452 bool SparcAsmParser::
453 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
455 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
458 // First operand in MCInst is instruction mnemonic.
459 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
461 // apply mnemonic aliases, if any, so that we can parse operands correctly.
462 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
464 if (getLexer().isNot(AsmToken::EndOfStatement)) {
465 // Read the first operand.
466 if (getLexer().is(AsmToken::Comma)) {
467 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
468 SMLoc Loc = getLexer().getLoc();
469 Parser.eatToEndOfStatement();
470 return Error(Loc, "unexpected token");
473 if (parseOperand(Operands, Name) != MatchOperand_Success) {
474 SMLoc Loc = getLexer().getLoc();
475 Parser.eatToEndOfStatement();
476 return Error(Loc, "unexpected token");
479 while (getLexer().is(AsmToken::Comma)) {
480 Parser.Lex(); // Eat the comma.
481 // Parse and remember the operand.
482 if (parseOperand(Operands, Name) != MatchOperand_Success) {
483 SMLoc Loc = getLexer().getLoc();
484 Parser.eatToEndOfStatement();
485 return Error(Loc, "unexpected token");
489 if (getLexer().isNot(AsmToken::EndOfStatement)) {
490 SMLoc Loc = getLexer().getLoc();
491 Parser.eatToEndOfStatement();
492 return Error(Loc, "unexpected token");
494 Parser.Lex(); // Consume the EndOfStatement.
498 bool SparcAsmParser::
499 ParseDirective(AsmToken DirectiveID)
501 StringRef IDVal = DirectiveID.getString();
503 if (IDVal == ".byte")
504 return parseDirectiveWord(1, DirectiveID.getLoc());
506 if (IDVal == ".half")
507 return parseDirectiveWord(2, DirectiveID.getLoc());
509 if (IDVal == ".word")
510 return parseDirectiveWord(4, DirectiveID.getLoc());
512 if (IDVal == ".nword")
513 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
515 if (is64Bit() && IDVal == ".xword")
516 return parseDirectiveWord(8, DirectiveID.getLoc());
518 if (IDVal == ".register") {
519 // For now, ignore .register directive.
520 Parser.eatToEndOfStatement();
524 // Let the MC layer to handle other directives.
528 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
529 if (getLexer().isNot(AsmToken::EndOfStatement)) {
532 if (getParser().parseExpression(Value))
535 getParser().getStreamer().EmitValue(Value, Size);
537 if (getLexer().is(AsmToken::EndOfStatement))
540 // FIXME: Improve diagnostic.
541 if (getLexer().isNot(AsmToken::Comma))
542 return Error(L, "unexpected token in directive");
550 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
551 parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands)
555 unsigned BaseReg = 0;
557 if (ParseRegister(BaseReg, S, E)) {
558 return MatchOperand_NoMatch;
561 switch (getLexer().getKind()) {
562 default: return MatchOperand_NoMatch;
564 case AsmToken::Comma:
565 case AsmToken::RBrac:
566 case AsmToken::EndOfStatement:
567 Operands.push_back(SparcOperand::CreateMEMri(BaseReg, 0, S, E));
568 return MatchOperand_Success;
570 case AsmToken:: Plus:
571 Parser.Lex(); // Eat the '+'
573 case AsmToken::Minus:
577 SparcOperand *Offset = 0;
578 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
579 if (ResTy != MatchOperand_Success || !Offset)
580 return MatchOperand_NoMatch;
582 Offset = (Offset->isImm()
583 ? SparcOperand::MorphToMEMri(BaseReg, Offset)
584 : SparcOperand::MorphToMEMrr(BaseReg, Offset));
586 Operands.push_back(Offset);
587 return MatchOperand_Success;
590 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
591 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
595 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
597 // If there wasn't a custom match, try the generic matcher below. Otherwise,
598 // there was a match, but an error occurred, in which case, just return that
599 // the operand parsing failed.
600 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
603 if (getLexer().is(AsmToken::LBrac)) {
605 Operands.push_back(SparcOperand::CreateToken("[",
606 Parser.getTok().getLoc()));
607 Parser.Lex(); // Eat the [
609 if (Mnemonic == "cas" || Mnemonic == "casx") {
610 SMLoc S = Parser.getTok().getLoc();
611 if (getLexer().getKind() != AsmToken::Percent)
612 return MatchOperand_NoMatch;
613 Parser.Lex(); // eat %
615 unsigned RegNo, RegKind;
616 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
617 return MatchOperand_NoMatch;
619 Parser.Lex(); // Eat the identifier token.
620 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
621 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
622 ResTy = MatchOperand_Success;
624 ResTy = parseMEMOperand(Operands);
627 if (ResTy != MatchOperand_Success)
630 if (!getLexer().is(AsmToken::RBrac))
631 return MatchOperand_ParseFail;
633 Operands.push_back(SparcOperand::CreateToken("]",
634 Parser.getTok().getLoc()));
635 Parser.Lex(); // Eat the ]
636 return MatchOperand_Success;
639 SparcOperand *Op = 0;
641 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
642 if (ResTy != MatchOperand_Success || !Op)
643 return MatchOperand_ParseFail;
645 // Push the parsed operand into the list of operands
646 Operands.push_back(Op);
648 return MatchOperand_Success;
651 SparcAsmParser::OperandMatchResultTy
652 SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall)
655 SMLoc S = Parser.getTok().getLoc();
656 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
660 switch (getLexer().getKind()) {
663 case AsmToken::Percent:
664 Parser.Lex(); // Eat the '%'.
667 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
668 StringRef name = Parser.getTok().getString();
669 Parser.Lex(); // Eat the identifier token.
670 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
673 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
676 Op = SparcOperand::CreateToken("%y", S);
681 Op = SparcOperand::CreateToken("%xcc", S);
683 Op = SparcOperand::CreateToken("%icc", S);
688 if (matchSparcAsmModifiers(EVal, E)) {
689 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
690 Op = SparcOperand::CreateImm(EVal, S, E);
694 case AsmToken::Minus:
695 case AsmToken::Integer:
696 if (!getParser().parseExpression(EVal, E))
697 Op = SparcOperand::CreateImm(EVal, S, E);
700 case AsmToken::Identifier: {
701 StringRef Identifier;
702 if (!getParser().parseIdentifier(Identifier)) {
703 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
704 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
706 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
709 getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
710 Res = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_WPLT30, Res,
712 Op = SparcOperand::CreateImm(Res, S, E);
717 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
720 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
721 parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
723 // parse (,a|,pn|,pt)+
725 while (getLexer().is(AsmToken::Comma)) {
727 Parser.Lex(); // Eat the comma
729 if (!getLexer().is(AsmToken::Identifier))
730 return MatchOperand_ParseFail;
731 StringRef modName = Parser.getTok().getString();
732 if (modName == "a" || modName == "pn" || modName == "pt") {
733 Operands.push_back(SparcOperand::CreateToken(modName,
734 Parser.getTok().getLoc()));
735 Parser.Lex(); // eat the identifier.
738 return MatchOperand_Success;
741 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
747 RegKind = SparcOperand::rk_None;
748 if (Tok.is(AsmToken::Identifier)) {
749 StringRef name = Tok.getString();
752 if (name.equals("fp")) {
754 RegKind = SparcOperand::rk_IntReg;
758 if (name.equals("sp")) {
760 RegKind = SparcOperand::rk_IntReg;
764 if (name.equals("y")) {
766 RegKind = SparcOperand::rk_Y;
770 if (name.equals("icc")) {
772 RegKind = SparcOperand::rk_CCReg;
776 if (name.equals("xcc")) {
777 // FIXME:: check 64bit.
779 RegKind = SparcOperand::rk_CCReg;
784 if (name.substr(0, 3).equals_lower("fcc")
785 && !name.substr(3).getAsInteger(10, intVal)
787 // FIXME: check 64bit and handle %fcc1 - %fcc3
788 RegNo = Sparc::FCC0 + intVal;
789 RegKind = SparcOperand::rk_CCReg;
794 if (name.substr(0, 1).equals_lower("g")
795 && !name.substr(1).getAsInteger(10, intVal)
797 RegNo = IntRegs[intVal];
798 RegKind = SparcOperand::rk_IntReg;
802 if (name.substr(0, 1).equals_lower("o")
803 && !name.substr(1).getAsInteger(10, intVal)
805 RegNo = IntRegs[8 + intVal];
806 RegKind = SparcOperand::rk_IntReg;
809 if (name.substr(0, 1).equals_lower("l")
810 && !name.substr(1).getAsInteger(10, intVal)
812 RegNo = IntRegs[16 + intVal];
813 RegKind = SparcOperand::rk_IntReg;
816 if (name.substr(0, 1).equals_lower("i")
817 && !name.substr(1).getAsInteger(10, intVal)
819 RegNo = IntRegs[24 + intVal];
820 RegKind = SparcOperand::rk_IntReg;
824 if (name.substr(0, 1).equals_lower("f")
825 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
826 RegNo = FloatRegs[intVal];
827 RegKind = SparcOperand::rk_FloatReg;
831 if (name.substr(0, 1).equals_lower("f")
832 && !name.substr(1, 2).getAsInteger(10, intVal)
833 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
835 RegNo = DoubleRegs[intVal/2];
836 RegKind = SparcOperand::rk_DoubleReg;
841 if (name.substr(0, 1).equals_lower("r")
842 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
843 RegNo = IntRegs[intVal];
844 RegKind = SparcOperand::rk_IntReg;
851 static bool hasGOTReference(const MCExpr *Expr) {
852 switch (Expr->getKind()) {
854 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
855 return hasGOTReference(SE->getSubExpr());
858 case MCExpr::Constant:
861 case MCExpr::Binary: {
862 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
863 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
866 case MCExpr::SymbolRef: {
867 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
868 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
872 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
877 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
880 AsmToken Tok = Parser.getTok();
881 if (!Tok.is(AsmToken::Identifier))
884 StringRef name = Tok.getString();
886 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
888 if (VK == SparcMCExpr::VK_Sparc_None)
891 Parser.Lex(); // Eat the identifier.
892 if (Parser.getTok().getKind() != AsmToken::LParen)
895 Parser.Lex(); // Eat the LParen token.
896 const MCExpr *subExpr;
897 if (Parser.parseParenExpression(subExpr, EndLoc))
900 bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
904 case SparcMCExpr::VK_Sparc_LO:
905 VK = (hasGOTReference(subExpr)
906 ? SparcMCExpr::VK_Sparc_PC10
907 : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
909 case SparcMCExpr::VK_Sparc_HI:
910 VK = (hasGOTReference(subExpr)
911 ? SparcMCExpr::VK_Sparc_PC22
912 : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
916 EVal = SparcMCExpr::Create(VK, subExpr, getContext());
921 extern "C" void LLVMInitializeSparcAsmParser() {
922 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
923 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
926 #define GET_REGISTER_MATCHER
927 #define GET_MATCHER_IMPLEMENTATION
928 #include "SparcGenAsmMatcher.inc"
932 unsigned SparcAsmParser::
933 validateTargetOperandClass(MCParsedAsmOperand *GOp,
936 SparcOperand *Op = (SparcOperand*)GOp;
937 if (Op->isFloatOrDoubleReg()) {
941 if (!Op->isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
942 return MCTargetAsmParser::Match_Success;
945 if (SparcOperand::MorphToQuadReg(Op))
946 return MCTargetAsmParser::Match_Success;
950 return Match_InvalidOperand;