1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCInst.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/MC/MCTargetAsmParser.h"
18 #include "llvm/Support/TargetRegistry.h"
22 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
23 // namespace. But SPARC backend uses "SP" as its namespace.
31 class SparcAsmParser : public MCTargetAsmParser {
36 /// @name Auto-generated Match Functions
39 #define GET_ASSEMBLER_HEADER
40 #include "SparcGenAsmMatcher.inc"
44 // public interface of the MCTargetAsmParser.
45 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
46 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
47 MCStreamer &Out, unsigned &ErrorInfo,
48 bool MatchingInlineAsm);
49 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
50 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
52 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
53 bool ParseDirective(AsmToken DirectiveID);
56 // Custom parse functions for Sparc specific operands.
58 parseMEMrrOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
60 parseMEMriOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
63 parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
67 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
70 // returns true if Tok is matched to a register and returns register in RegNo.
71 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo, bool isDFP,
75 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
76 const MCInstrInfo &MII)
77 : MCTargetAsmParser(), STI(sti), Parser(parser) {
78 // Initialize the set of available features.
79 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
84 static unsigned IntRegs[32] = {
85 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
86 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
87 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
88 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
89 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
90 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
91 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
92 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
94 static unsigned FloatRegs[32] = {
95 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
96 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
97 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
98 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
99 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
100 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
101 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
102 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
104 static unsigned DoubleRegs[32] = {
105 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
106 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
107 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
108 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
109 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
110 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
111 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
112 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
114 static unsigned QuadFPRegs[32] = {
115 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
116 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
117 Sparc::Q8, Sparc::Q7, Sparc::Q8, Sparc::Q9,
118 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
121 /// SparcOperand - Instances of this class represent a parsed Sparc machine
123 class SparcOperand : public MCParsedAsmOperand {
143 SMLoc StartLoc, EndLoc;
145 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
174 bool isToken() const { return Kind == k_Token; }
175 bool isReg() const { return Kind == k_Register; }
176 bool isImm() const { return Kind == k_Immediate; }
177 bool isMem() const { return isMEMrr() || isMEMri(); }
178 bool isMEMrr() const { return Kind == k_MemoryReg; }
179 bool isMEMri() const { return Kind == k_MemoryImm; }
181 StringRef getToken() const {
182 assert(Kind == k_Token && "Invalid access!");
183 return StringRef(Tok.Data, Tok.Length);
186 unsigned getReg() const {
187 assert((Kind == k_Register) && "Invalid access!");
191 const MCExpr *getImm() const {
192 assert((Kind == k_Immediate) && "Invalid access!");
196 unsigned getMemBase() const {
197 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
201 unsigned getMemOffsetReg() const {
202 assert((Kind == k_MemoryReg) && "Invalid access!");
203 return Mem.OffsetReg;
206 const MCExpr *getMemOff() const {
207 assert((Kind == k_MemoryImm) && "Invalid access!");
211 /// getStartLoc - Get the location of the first token of this operand.
212 SMLoc getStartLoc() const {
215 /// getEndLoc - Get the location of the last token of this operand.
216 SMLoc getEndLoc() const {
220 virtual void print(raw_ostream &OS) const {
222 case k_Token: OS << "Token: " << getToken() << "\n"; break;
223 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
224 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
225 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
226 << getMemOffsetReg() << "\n"; break;
227 case k_MemoryImm: assert(getMemOff() != 0);
228 OS << "Mem: " << getMemBase()
229 << "+" << *getMemOff()
234 void addRegOperands(MCInst &Inst, unsigned N) const {
235 assert(N == 1 && "Invalid number of operands!");
236 Inst.addOperand(MCOperand::CreateReg(getReg()));
239 void addImmOperands(MCInst &Inst, unsigned N) const {
240 assert(N == 1 && "Invalid number of operands!");
241 const MCExpr *Expr = getImm();
245 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
246 // Add as immediate when possible. Null MCExpr = 0.
248 Inst.addOperand(MCOperand::CreateImm(0));
249 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
250 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
252 Inst.addOperand(MCOperand::CreateExpr(Expr));
255 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
256 assert(N == 2 && "Invalid number of operands!");
258 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
260 assert(getMemOffsetReg() != 0 && "Invalid offset");
261 Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
264 void addMEMriOperands(MCInst &Inst, unsigned N) const {
265 assert(N == 2 && "Invalid number of operands!");
267 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
269 const MCExpr *Expr = getMemOff();
273 static SparcOperand *CreateToken(StringRef Str, SMLoc S) {
274 SparcOperand *Op = new SparcOperand(k_Token);
275 Op->Tok.Data = Str.data();
276 Op->Tok.Length = Str.size();
282 static SparcOperand *CreateReg(unsigned RegNum,
283 SparcOperand::RegisterKind Kind,
285 SparcOperand *Op = new SparcOperand(k_Register);
286 Op->Reg.RegNum = RegNum;
293 static SparcOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
294 SparcOperand *Op = new SparcOperand(k_Immediate);
306 bool SparcAsmParser::
307 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
308 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
309 MCStreamer &Out, unsigned &ErrorInfo,
310 bool MatchingInlineAsm) {
312 SmallVector<MCInst, 8> Instructions;
313 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
315 switch (MatchResult) {
319 case Match_Success: {
321 Out.EmitInstruction(Inst);
325 case Match_MissingFeature:
327 "instruction requires a CPU feature not currently enabled");
329 case Match_InvalidOperand: {
330 SMLoc ErrorLoc = IDLoc;
331 if (ErrorInfo != ~0U) {
332 if (ErrorInfo >= Operands.size())
333 return Error(IDLoc, "too few operands for instruction");
335 ErrorLoc = ((SparcOperand*) Operands[ErrorInfo])->getStartLoc();
336 if (ErrorLoc == SMLoc())
340 return Error(ErrorLoc, "invalid operand for instruction");
342 case Match_MnemonicFail:
343 return Error(IDLoc, "invalid instruction");
348 bool SparcAsmParser::
349 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
351 const AsmToken &Tok = Parser.getTok();
352 StartLoc = Tok.getLoc();
353 EndLoc = Tok.getEndLoc();
355 if (getLexer().getKind() != AsmToken::Percent)
358 if (matchRegisterName(Tok, RegNo, false, false)) {
363 return Error(StartLoc, "invalid register name");
366 bool SparcAsmParser::
367 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
369 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
371 // Check if we have valid mnemonic.
372 if (!mnemonicIsValid(Name, 0)) {
373 Parser.eatToEndOfStatement();
374 return Error(NameLoc, "Unknown instruction");
376 // First operand in MCInst is instruction mnemonic.
377 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
379 if (getLexer().isNot(AsmToken::EndOfStatement)) {
380 // Read the first operand.
381 if (parseOperand(Operands, Name) != MatchOperand_Success) {
382 SMLoc Loc = getLexer().getLoc();
383 Parser.eatToEndOfStatement();
384 return Error(Loc, "unexpected token");
387 while (getLexer().is(AsmToken::Comma)) {
388 Parser.Lex(); // Eat the comma.
389 // Parse and remember the operand.
390 if (parseOperand(Operands, Name) != MatchOperand_Success) {
391 SMLoc Loc = getLexer().getLoc();
392 Parser.eatToEndOfStatement();
393 return Error(Loc, "unexpected token");
397 if (getLexer().isNot(AsmToken::EndOfStatement)) {
398 SMLoc Loc = getLexer().getLoc();
399 Parser.eatToEndOfStatement();
400 return Error(Loc, "unexpected token");
402 Parser.Lex(); // Consume the EndOfStatement.
406 bool SparcAsmParser::
407 ParseDirective(AsmToken DirectiveID)
409 // Ignore all directives for now.
410 Parser.eatToEndOfStatement();
414 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
415 parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
418 // FIXME: Implement memory operand parsing here.
419 return MatchOperand_NoMatch;
422 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
423 parseMEMrrOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands)
425 return parseMEMOperand(Operands, 2);
428 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
429 parseMEMriOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands)
431 return parseMEMOperand(Operands, 1);
434 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
435 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
438 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
439 if (ResTy == MatchOperand_Success)
441 // If there wasn't a custom match, try the generic matcher below. Otherwise,
442 // there was a match, but an error occurred, in which case, just return that
443 // the operand parsing failed.
444 if (ResTy == MatchOperand_ParseFail)
447 SMLoc S = Parser.getTok().getLoc();
448 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
451 switch (getLexer().getKind()) {
452 case AsmToken::Percent:
453 Parser.Lex(); // Eat the '%'.
455 if (matchRegisterName(Parser.getTok(), RegNo, false, false)) {
456 Parser.Lex(); // Eat the identifier token.
457 Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E);
460 // FIXME: Handle modifiers like %hi, %lo etc.,
461 return MatchOperand_ParseFail;
463 case AsmToken::Minus:
464 case AsmToken::Integer:
465 if (getParser().parseExpression(EVal))
466 return MatchOperand_ParseFail;
468 Op = SparcOperand::CreateImm(EVal, S, E);
471 case AsmToken::Identifier: {
472 StringRef Identifier;
473 if (getParser().parseIdentifier(Identifier))
474 return MatchOperand_ParseFail;
475 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
476 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
478 // Otherwise create a symbol reference.
479 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
482 Op = SparcOperand::CreateImm(Res, S, E);
486 case AsmToken::LBrac: // handle [
487 return parseMEMOperand(Operands, 0);
490 return MatchOperand_ParseFail;
492 // Push the parsed operand into the list of operands
493 Operands.push_back(Op);
494 return MatchOperand_Success;
497 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
504 if (Tok.is(AsmToken::Identifier)) {
505 StringRef name = Tok.getString();
508 if (name.equals("fp")) {
513 if (name.equals("sp")) {
518 if (name.equals("y")) {
523 if (name.equals("icc")) {
528 if (name.equals("xcc")) {
529 // FIXME:: check 64bit.
535 if (name.substr(0, 3).equals_lower("fcc")
536 && !name.substr(3).getAsInteger(10, intVal)
538 // FIXME: check 64bit and handle %fcc1 - %fcc3
544 if (name.substr(0, 1).equals_lower("g")
545 && !name.substr(1).getAsInteger(10, intVal)
547 RegNo = IntRegs[intVal];
551 if (name.substr(0, 1).equals_lower("o")
552 && !name.substr(1).getAsInteger(10, intVal)
554 RegNo = IntRegs[8 + intVal];
557 if (name.substr(0, 1).equals_lower("l")
558 && !name.substr(1).getAsInteger(10, intVal)
560 RegNo = IntRegs[16 + intVal];
563 if (name.substr(0, 1).equals_lower("i")
564 && !name.substr(1).getAsInteger(10, intVal)
566 RegNo = IntRegs[24 + intVal];
570 if (name.substr(0, 1).equals_lower("f")
571 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
572 if (isDFP && (intVal%2 == 0)) {
573 RegNo = DoubleRegs[intVal/2];
574 } else if (isQFP && (intVal%4 == 0)) {
575 RegNo = QuadFPRegs[intVal/4];
577 RegNo = FloatRegs[intVal];
582 if (name.substr(0, 1).equals_lower("f")
583 && !name.substr(1, 2).getAsInteger(10, intVal)
584 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
586 RegNo = DoubleRegs[16 + intVal/2];
587 } else if (isQFP && (intVal % 4 == 0)) {
588 RegNo = QuadFPRegs[8 + intVal/4];
596 if (name.substr(0, 1).equals_lower("r")
597 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
598 RegNo = IntRegs[intVal];
607 extern "C" void LLVMInitializeSparcAsmParser() {
608 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
609 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
612 #define GET_REGISTER_MATCHER
613 #define GET_MATCHER_IMPLEMENTATION
614 #include "SparcGenAsmMatcher.inc"