1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "SIRegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "SIInstrInfo.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/LLVMContext.h"
28 SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
29 : AMDGPURegisterInfo(st)
32 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
33 BitVector Reserved(getNumRegs());
34 Reserved.set(AMDGPU::EXEC);
36 // EXEC_LO and EXEC_HI could be allocated and used as regular register,
37 // but this seems likely to result in bugs, so I'm marking them as reserved.
38 Reserved.set(AMDGPU::EXEC_LO);
39 Reserved.set(AMDGPU::EXEC_HI);
41 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
42 Reserved.set(AMDGPU::FLAT_SCR);
44 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
45 Reserved.set(AMDGPU::VGPR255);
46 Reserved.set(AMDGPU::VGPR254);
51 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
52 MachineFunction &MF) const {
53 return RC->getNumRegs();
56 bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
57 return Fn.getFrameInfo()->hasStackObjects();
60 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
63 case AMDGPU::SI_SPILL_S512_SAVE:
64 case AMDGPU::SI_SPILL_S512_RESTORE:
65 case AMDGPU::SI_SPILL_V512_SAVE:
66 case AMDGPU::SI_SPILL_V512_RESTORE:
68 case AMDGPU::SI_SPILL_S256_SAVE:
69 case AMDGPU::SI_SPILL_S256_RESTORE:
70 case AMDGPU::SI_SPILL_V256_SAVE:
71 case AMDGPU::SI_SPILL_V256_RESTORE:
73 case AMDGPU::SI_SPILL_S128_SAVE:
74 case AMDGPU::SI_SPILL_S128_RESTORE:
75 case AMDGPU::SI_SPILL_V128_SAVE:
76 case AMDGPU::SI_SPILL_V128_RESTORE:
78 case AMDGPU::SI_SPILL_V96_SAVE:
79 case AMDGPU::SI_SPILL_V96_RESTORE:
81 case AMDGPU::SI_SPILL_S64_SAVE:
82 case AMDGPU::SI_SPILL_S64_RESTORE:
83 case AMDGPU::SI_SPILL_V64_SAVE:
84 case AMDGPU::SI_SPILL_V64_RESTORE:
86 case AMDGPU::SI_SPILL_S32_SAVE:
87 case AMDGPU::SI_SPILL_S32_RESTORE:
88 case AMDGPU::SI_SPILL_V32_SAVE:
89 case AMDGPU::SI_SPILL_V32_RESTORE:
91 default: llvm_unreachable("Invalid spill opcode");
95 void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
96 int SPAdj, unsigned FIOperandNum,
97 RegScavenger *RS) const {
98 MachineFunction *MF = MI->getParent()->getParent();
99 MachineBasicBlock *MBB = MI->getParent();
100 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
101 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
102 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
103 DebugLoc DL = MI->getDebugLoc();
105 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
106 int Index = MI->getOperand(FIOperandNum).getIndex();
108 switch (MI->getOpcode()) {
109 // SGPR register spill
110 case AMDGPU::SI_SPILL_S512_SAVE:
111 case AMDGPU::SI_SPILL_S256_SAVE:
112 case AMDGPU::SI_SPILL_S128_SAVE:
113 case AMDGPU::SI_SPILL_S64_SAVE:
114 case AMDGPU::SI_SPILL_S32_SAVE: {
115 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
117 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
118 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
119 &AMDGPU::SGPR_32RegClass, i);
120 struct SIMachineFunctionInfo::SpilledReg Spill =
121 MFI->getSpilledReg(MF, Index, i);
123 if (Spill.VGPR == AMDGPU::NoRegister) {
124 LLVMContext &Ctx = MF->getFunction()->getContext();
125 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
128 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR)
133 MI->eraseFromParent();
137 // SGPR register restore
138 case AMDGPU::SI_SPILL_S512_RESTORE:
139 case AMDGPU::SI_SPILL_S256_RESTORE:
140 case AMDGPU::SI_SPILL_S128_RESTORE:
141 case AMDGPU::SI_SPILL_S64_RESTORE:
142 case AMDGPU::SI_SPILL_S32_RESTORE: {
143 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
145 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
146 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
147 &AMDGPU::SGPR_32RegClass, i);
148 bool isM0 = SubReg == AMDGPU::M0;
149 struct SIMachineFunctionInfo::SpilledReg Spill =
150 MFI->getSpilledReg(MF, Index, i);
152 if (Spill.VGPR == AMDGPU::NoRegister) {
153 LLVMContext &Ctx = MF->getFunction()->getContext();
154 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
158 SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
161 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
165 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
169 TII->insertNOPs(MI, 3);
170 MI->eraseFromParent();
174 // VGPR register spill
175 case AMDGPU::SI_SPILL_V512_SAVE:
176 case AMDGPU::SI_SPILL_V256_SAVE:
177 case AMDGPU::SI_SPILL_V128_SAVE:
178 case AMDGPU::SI_SPILL_V96_SAVE:
179 case AMDGPU::SI_SPILL_V64_SAVE:
180 case AMDGPU::SI_SPILL_V32_SAVE: {
181 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
182 unsigned SrcReg = MI->getOperand(0).getReg();
183 int64_t Offset = FrameInfo->getObjectOffset(Index);
184 unsigned Size = NumSubRegs * 4;
185 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
187 for (unsigned i = 0, e = NumSubRegs; i != e; ++i) {
188 unsigned SubReg = NumSubRegs > 1 ?
189 getPhysRegSubReg(SrcReg, &AMDGPU::VGPR_32RegClass, i) :
192 MFI->LDSWaveSpillSize = std::max((unsigned)Offset + 4, (unsigned)MFI->LDSWaveSpillSize);
194 unsigned AddrReg = TII->calculateLDSSpillAddress(*MBB, MI, RS, TmpReg,
197 if (AddrReg == AMDGPU::NoRegister) {
198 LLVMContext &Ctx = MF->getFunction()->getContext();
199 Ctx.emitError("Ran out of VGPRs for spilling VGPRS");
200 AddrReg = AMDGPU::VGPR0;
203 // Store the value in LDS
204 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::DS_WRITE_B32))
206 .addReg(AddrReg, RegState::Kill) // addr
207 .addReg(SubReg) // data0
208 .addImm(0); // offset
211 MI->eraseFromParent();
214 case AMDGPU::SI_SPILL_V32_RESTORE:
215 case AMDGPU::SI_SPILL_V64_RESTORE:
216 case AMDGPU::SI_SPILL_V128_RESTORE:
217 case AMDGPU::SI_SPILL_V256_RESTORE:
218 case AMDGPU::SI_SPILL_V512_RESTORE: {
219 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
220 unsigned DstReg = MI->getOperand(0).getReg();
221 int64_t Offset = FrameInfo->getObjectOffset(Index);
222 unsigned Size = NumSubRegs * 4;
223 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
225 // FIXME: We could use DS_READ_B64 here to optimize for larger registers.
226 for (unsigned i = 0, e = NumSubRegs; i != e; ++i) {
227 unsigned SubReg = NumSubRegs > 1 ?
228 getPhysRegSubReg(DstReg, &AMDGPU::VGPR_32RegClass, i) :
232 unsigned AddrReg = TII->calculateLDSSpillAddress(*MBB, MI, RS, TmpReg,
234 if (AddrReg == AMDGPU::NoRegister) {
235 LLVMContext &Ctx = MF->getFunction()->getContext();
236 Ctx.emitError("Ran out of VGPRs for spilling VGPRs");
237 AddrReg = AMDGPU::VGPR0;
240 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::DS_READ_B32), SubReg)
242 .addReg(AddrReg, RegState::Kill) // addr
245 MI->eraseFromParent();
250 int64_t Offset = FrameInfo->getObjectOffset(Index);
251 FIOp.ChangeToImmediate(Offset);
252 if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
253 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VReg_32RegClass, MI, SPAdj);
254 BuildMI(*MBB, MI, MI->getDebugLoc(),
255 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
257 FIOp.ChangeToRegister(TmpReg, false);
263 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
265 switch(VT.SimpleTy) {
267 case MVT::i32: return &AMDGPU::VReg_32RegClass;
271 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
272 return getEncodingValue(Reg) & 0xff;
275 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
276 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
278 static const TargetRegisterClass *BaseClasses[] = {
279 &AMDGPU::VReg_32RegClass,
280 &AMDGPU::SReg_32RegClass,
281 &AMDGPU::VReg_64RegClass,
282 &AMDGPU::SReg_64RegClass,
283 &AMDGPU::VReg_96RegClass,
284 &AMDGPU::VReg_128RegClass,
285 &AMDGPU::SReg_128RegClass,
286 &AMDGPU::VReg_256RegClass,
287 &AMDGPU::SReg_256RegClass,
288 &AMDGPU::VReg_512RegClass
291 for (const TargetRegisterClass *BaseClass : BaseClasses) {
292 if (BaseClass->contains(Reg)) {
299 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
300 return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
301 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
302 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
303 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
304 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
305 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
308 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
309 const TargetRegisterClass *SRC) const {
312 } else if (SRC == &AMDGPU::SCCRegRegClass) {
313 return &AMDGPU::VCCRegRegClass;
314 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
315 return &AMDGPU::VReg_32RegClass;
316 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
317 return &AMDGPU::VReg_64RegClass;
318 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
319 return &AMDGPU::VReg_128RegClass;
320 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
321 return &AMDGPU::VReg_256RegClass;
322 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
323 return &AMDGPU::VReg_512RegClass;
328 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
329 const TargetRegisterClass *RC, unsigned SubIdx) const {
330 if (SubIdx == AMDGPU::NoSubRegister)
333 // If this register has a sub-register, we can safely assume it is a 32-bit
334 // register, because all of SI's sub-registers are 32-bit.
335 if (isSGPRClass(RC)) {
336 return &AMDGPU::SGPR_32RegClass;
338 return &AMDGPU::VGPR_32RegClass;
342 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
343 const TargetRegisterClass *SubRC,
344 unsigned Channel) const {
349 case 0: return AMDGPU::VCC_LO;
350 case 1: return AMDGPU::VCC_HI;
351 default: llvm_unreachable("Invalid SubIdx for VCC");
354 case AMDGPU::FLAT_SCR:
357 return AMDGPU::FLAT_SCR_LO;
359 return AMDGPU::FLAT_SCR_HI;
361 llvm_unreachable("Invalid SubIdx for FLAT_SCR");
368 return AMDGPU::EXEC_LO;
370 return AMDGPU::EXEC_HI;
372 llvm_unreachable("Invalid SubIdx for EXEC");
377 const TargetRegisterClass *RC = getPhysRegClass(Reg);
378 // 32-bit registers don't have sub-registers, so we can just return the
379 // Reg. We need to have this check here, because the calculation below
380 // using getHWRegIndex() will fail with special 32-bit registers like
381 // VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
382 if (RC->getSize() == 4) {
383 assert(Channel == 0);
387 unsigned Index = getHWRegIndex(Reg);
388 return SubRC->getRegister(Index + Channel);
391 bool SIRegisterInfo::regClassCanUseLiteralConstant(int RCID) const {
393 default: return false;
394 case AMDGPU::SSrc_32RegClassID:
395 case AMDGPU::SSrc_64RegClassID:
396 case AMDGPU::VSrc_32RegClassID:
397 case AMDGPU::VSrc_64RegClassID:
402 bool SIRegisterInfo::regClassCanUseLiteralConstant(
403 const TargetRegisterClass *RC) const {
404 return regClassCanUseLiteralConstant(RC->getID());
407 bool SIRegisterInfo::regClassCanUseInlineConstant(int RCID) const {
408 if (regClassCanUseLiteralConstant(RCID))
412 default: return false;
413 case AMDGPU::VCSrc_32RegClassID:
414 case AMDGPU::VCSrc_64RegClassID:
419 bool SIRegisterInfo::regClassCanUseInlineConstant(
420 const TargetRegisterClass *RC) const {
421 return regClassCanUseInlineConstant(RC->getID());
425 unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
426 enum PreloadedValue Value) const {
428 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
430 case SIRegisterInfo::TGID_X:
431 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
432 case SIRegisterInfo::TGID_Y:
433 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
434 case SIRegisterInfo::TGID_Z:
435 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
436 case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
437 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
438 case SIRegisterInfo::SCRATCH_PTR:
439 return AMDGPU::SGPR2_SGPR3;
440 case SIRegisterInfo::INPUT_PTR:
441 return AMDGPU::SGPR0_SGPR1;
442 case SIRegisterInfo::TIDIG_X:
443 return AMDGPU::VGPR0;
444 case SIRegisterInfo::TIDIG_Y:
445 return AMDGPU::VGPR1;
446 case SIRegisterInfo::TIDIG_Z:
447 return AMDGPU::VGPR2;
449 llvm_unreachable("unexpected preloaded value type");
452 /// \brief Returns a register that is not used at any point in the function.
453 /// If all registers are used, then this function will return
454 // AMDGPU::NoRegister.
455 unsigned SIRegisterInfo::findUnusedVGPR(const MachineRegisterInfo &MRI) const {
457 const TargetRegisterClass *RC = &AMDGPU::VGPR_32RegClass;
459 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
461 if (!MRI.isPhysRegUsed(*I))
464 return AMDGPU::NoRegister;