1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_SIISELLOWERING_H
16 #define LLVM_LIB_TARGET_R600_SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering : public AMDGPUTargetLowering {
24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset, bool Signed) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27 SelectionDAG &DAG) const;
28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
29 SelectionDAG &DAG) const override;
31 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
40 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
41 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
42 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
44 bool foldImm(SDValue &Operand, int32_t &Immediate,
45 bool &ScalarSlotUsed) const;
46 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
47 const SDValue &Op) const;
48 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
49 unsigned RegClass) const;
51 SDNode *legalizeOperands(MachineSDNode *N, SelectionDAG &DAG) const;
52 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
53 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
55 static SDValue performUCharToFloatCombine(SDNode *N,
56 DAGCombinerInfo &DCI);
57 SDValue performSHLPtrCombine(SDNode *N,
59 DAGCombinerInfo &DCI) const;
62 SITargetLowering(TargetMachine &tm);
64 bool isLegalAddressingMode(const AddrMode &AM,
65 Type *Ty) const override;
67 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
69 bool *IsFast) const override;
71 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
72 unsigned SrcAlign, bool IsMemset,
75 MachineFunction &MF) const override;
77 TargetLoweringBase::LegalizeTypeAction
78 getPreferredVectorAction(EVT VT) const override;
80 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
81 Type *Ty) const override;
83 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
85 const SmallVectorImpl<ISD::InputArg> &Ins,
86 SDLoc DL, SelectionDAG &DAG,
87 SmallVectorImpl<SDValue> &InVals) const override;
89 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
90 MachineBasicBlock * BB) const override;
91 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
92 MVT getScalarShiftAmountTy(EVT VT) const override;
93 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
94 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
95 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
96 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
97 void AdjustInstrPostInstrSelection(MachineInstr *MI,
98 SDNode *Node) const override;
100 int32_t analyzeImmediate(const SDNode *N) const;
101 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
102 unsigned Reg, EVT VT) const override;
105 } // End namespace llvm