1 //===-- R600ExpandSpecialInstrs.cpp - Expand special instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Vector, Reduction, and Cube instructions need to fill the entire instruction
12 /// group to work correctly. This pass expands these individual instructions
13 /// into several instructions that will completely fill the instruction group.
15 //===----------------------------------------------------------------------===//
18 #include "R600Defines.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "AMDGPUSubtarget.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
35 const R600InstrInfo *TII;
37 void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
41 R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
44 bool runOnMachineFunction(MachineFunction &MF) override;
46 const char *getPassName() const override {
47 return "R600 Expand special instructions pass";
51 } // End anonymous namespace
53 char R600ExpandSpecialInstrsPass::ID = 0;
55 FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) {
56 return new R600ExpandSpecialInstrsPass(TM);
59 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
60 const MachineInstr *OldMI, unsigned Op) {
61 int OpIdx = TII->getOperandIdx(*OldMI, Op);
63 uint64_t Val = OldMI->getOperand(OpIdx).getImm();
64 TII->setImmOperand(NewMI, Op, Val);
68 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
69 TII = static_cast<const R600InstrInfo *>(
70 MF.getTarget().getSubtargetImpl()->getInstrInfo());
72 const R600RegisterInfo &TRI = TII->getRegisterInfo();
74 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
76 MachineBasicBlock &MBB = *BB;
77 MachineBasicBlock::iterator I = MBB.begin();
78 while (I != MBB.end()) {
79 MachineInstr &MI = *I;
82 // Expand LDS_*_RET instructions
83 if (TII->isLDSRetInstr(MI.getOpcode())) {
84 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
86 MachineOperand &DstOp = MI.getOperand(DstIdx);
87 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
88 DstOp.getReg(), AMDGPU::OQAP);
89 DstOp.setReg(AMDGPU::OQAP);
90 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
91 AMDGPU::OpName::pred_sel);
92 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
93 AMDGPU::OpName::pred_sel);
94 // Copy the pred_sel bit
95 Mov->getOperand(MovPredSelIdx).setReg(
96 MI.getOperand(LDSPredSelIdx).getReg());
99 switch (MI.getOpcode()) {
101 // Expand PRED_X to one of the PRED_SET instructions.
102 case AMDGPU::PRED_X: {
103 uint64_t Flags = MI.getOperand(3).getImm();
104 // The native opcode used by PRED_X is stored as an immediate in the
106 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
107 MI.getOperand(2).getImm(), // opcode
108 MI.getOperand(0).getReg(), // dst
109 MI.getOperand(1).getReg(), // src0
110 AMDGPU::ZERO); // src1
111 TII->addFlag(PredSet, 0, MO_FLAG_MASK);
112 if (Flags & MO_FLAG_PUSH) {
113 TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1);
115 TII->setImmOperand(PredSet, AMDGPU::OpName::update_pred, 1);
117 MI.eraseFromParent();
121 case AMDGPU::INTERP_PAIR_XY: {
123 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
124 MI.getOperand(2).getImm());
126 for (unsigned Chan = 0; Chan < 4; ++Chan) {
130 DstReg = MI.getOperand(Chan).getReg();
132 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
134 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
135 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
138 BMI->bundleWithPred();
141 TII->addFlag(BMI, 0, MO_FLAG_MASK);
143 TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
146 MI.eraseFromParent();
150 case AMDGPU::INTERP_PAIR_ZW: {
152 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
153 MI.getOperand(2).getImm());
155 for (unsigned Chan = 0; Chan < 4; ++Chan) {
159 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
161 DstReg = MI.getOperand(Chan-2).getReg();
163 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
164 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
167 BMI->bundleWithPred();
170 TII->addFlag(BMI, 0, MO_FLAG_MASK);
172 TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
175 MI.eraseFromParent();
179 case AMDGPU::INTERP_VEC_LOAD: {
180 const R600RegisterInfo &TRI = TII->getRegisterInfo();
182 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
183 MI.getOperand(1).getImm());
184 unsigned DstReg = MI.getOperand(0).getReg();
186 for (unsigned Chan = 0; Chan < 4; ++Chan) {
187 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
188 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
190 BMI->bundleWithPred();
193 TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
196 MI.eraseFromParent();
199 case AMDGPU::DOT_4: {
201 const R600RegisterInfo &TRI = TII->getRegisterInfo();
203 unsigned DstReg = MI.getOperand(0).getReg();
204 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
206 for (unsigned Chan = 0; Chan < 4; ++Chan) {
207 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
209 AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
211 TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
213 BMI->bundleWithPred();
216 TII->addFlag(BMI, 0, MO_FLAG_MASK);
219 TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
220 unsigned Opcode = BMI->getOpcode();
221 // While not strictly necessary from hw point of view, we force
222 // all src operands of a dot4 inst to belong to the same slot.
223 unsigned Src0 = BMI->getOperand(
224 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
226 unsigned Src1 = BMI->getOperand(
227 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
231 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
232 (TRI.getEncodingValue(Src1) & 0xff) < 127)
233 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
235 MI.eraseFromParent();
240 bool IsReduction = TII->isReductionOp(MI.getOpcode());
241 bool IsVector = TII->isVector(MI);
242 bool IsCube = TII->isCubeOp(MI.getOpcode());
243 if (!IsReduction && !IsVector && !IsCube) {
247 // Expand the instruction
249 // Reduction instructions:
250 // T0_X = DP4 T1_XYZW, T2_XYZW
252 // TO_X = DP4 T1_X, T2_X
253 // TO_Y (write masked) = DP4 T1_Y, T2_Y
254 // TO_Z (write masked) = DP4 T1_Z, T2_Z
255 // TO_W (write masked) = DP4 T1_W, T2_W
257 // Vector instructions:
258 // T0_X = MULLO_INT T1_X, T2_X
260 // T0_X = MULLO_INT T1_X, T2_X
261 // T0_Y (write masked) = MULLO_INT T1_X, T2_X
262 // T0_Z (write masked) = MULLO_INT T1_X, T2_X
263 // T0_W (write masked) = MULLO_INT T1_X, T2_X
265 // Cube instructions:
266 // T0_XYZW = CUBE T1_XYZW
268 // TO_X = CUBE T1_Z, T1_Y
269 // T0_Y = CUBE T1_Z, T1_X
270 // T0_Z = CUBE T1_X, T1_Z
271 // T0_W = CUBE T1_Y, T1_Z
272 for (unsigned Chan = 0; Chan < 4; Chan++) {
273 unsigned DstReg = MI.getOperand(
274 TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg();
275 unsigned Src0 = MI.getOperand(
276 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
279 // Determine the correct source registers
281 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
283 Src1 = MI.getOperand(Src1Idx).getReg();
287 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
288 Src0 = TRI.getSubReg(Src0, SubRegIndex);
289 Src1 = TRI.getSubReg(Src1, SubRegIndex);
291 static const int CubeSrcSwz[] = {2, 2, 0, 1};
292 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
293 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
294 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
295 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
298 // Determine the correct destination registers;
302 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
303 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
305 // Mask the write if the original instruction does not write to
306 // the current Channel.
307 Mask = (Chan != TRI.getHWRegChan(DstReg));
308 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
309 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
312 // Set the IsLast bit
313 NotLast = (Chan != 3 );
315 // Add the new instruction
316 unsigned Opcode = MI.getOpcode();
318 case AMDGPU::CUBE_r600_pseudo:
319 Opcode = AMDGPU::CUBE_r600_real;
321 case AMDGPU::CUBE_eg_pseudo:
322 Opcode = AMDGPU::CUBE_eg_real;
328 MachineInstr *NewMI =
329 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
332 NewMI->bundleWithPred();
334 TII->addFlag(NewMI, 0, MO_FLAG_MASK);
337 TII->addFlag(NewMI, 0, MO_FLAG_NOT_LAST);
339 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::clamp);
340 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::literal);
341 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_abs);
342 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_abs);
343 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_neg);
344 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_neg);
346 MI.eraseFromParent();