1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file provides AMDGPU specific target descriptions.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUMCAsmInfo.h"
17 #include "SIDefines.h"
18 #include "InstPrinter/AMDGPUInstPrinter.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MachineLocation.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
30 #define GET_INSTRINFO_MC_DESC
31 #include "AMDGPUGenInstrInfo.inc"
33 #define GET_SUBTARGETINFO_MC_DESC
34 #include "AMDGPUGenSubtargetInfo.inc"
36 #define GET_REGINFO_MC_DESC
37 #include "AMDGPUGenRegisterInfo.inc"
39 static MCInstrInfo *createAMDGPUMCInstrInfo() {
40 MCInstrInfo *X = new MCInstrInfo();
41 InitAMDGPUMCInstrInfo(X);
45 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
46 MCRegisterInfo *X = new MCRegisterInfo();
47 InitAMDGPUMCRegisterInfo(X, 0);
51 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
53 MCSubtargetInfo * X = new MCSubtargetInfo();
54 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
58 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
60 CodeGenOpt::Level OL) {
61 MCCodeGenInfo *X = new MCCodeGenInfo();
62 X->InitMCCodeGenInfo(RM, CM, OL);
66 static MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T,
67 unsigned SyntaxVariant,
69 const MCInstrInfo &MII,
70 const MCRegisterInfo &MRI,
71 const MCSubtargetInfo &STI) {
72 return new AMDGPUInstPrinter(MAI, MII, MRI);
75 static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
76 const MCRegisterInfo &MRI,
77 const MCSubtargetInfo &STI,
79 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
80 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
82 return createR600MCCodeEmitter(MCII, MRI, STI);
86 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
87 MCContext &Ctx, MCAsmBackend &MAB,
88 raw_ostream &_OS, MCCodeEmitter *_Emitter,
89 const MCSubtargetInfo &STI, bool RelaxAll) {
90 return createELFStreamer(Ctx, MAB, _OS, _Emitter, false);
93 extern "C" void LLVMInitializeR600TargetMC() {
95 RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget);
96 RegisterMCAsmInfo<AMDGPUMCAsmInfo> Z(TheGCNTarget);
98 TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo);
99 TargetRegistry::RegisterMCCodeGenInfo(TheGCNTarget, createAMDGPUMCCodeGenInfo);
101 TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo);
102 TargetRegistry::RegisterMCInstrInfo(TheGCNTarget, createAMDGPUMCInstrInfo);
104 TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo);
105 TargetRegistry::RegisterMCRegInfo(TheGCNTarget, createAMDGPUMCRegisterInfo);
107 TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo);
108 TargetRegistry::RegisterMCSubtargetInfo(TheGCNTarget, createAMDGPUMCSubtargetInfo);
110 TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter);
111 TargetRegistry::RegisterMCInstPrinter(TheGCNTarget, createAMDGPUMCInstPrinter);
113 TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createAMDGPUMCCodeEmitter);
114 TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createAMDGPUMCCodeEmitter);
116 TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend);
117 TargetRegistry::RegisterMCAsmBackend(TheGCNTarget, createAMDGPUAsmBackend);
119 TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer);
120 TargetRegistry::RegisterMCObjectStreamer(TheGCNTarget, createMCStreamer);