1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "SIDefines.h"
14 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/MathExtras.h"
22 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
25 printInstruction(MI, OS);
27 printAnnotation(OS, Annot);
30 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
32 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
35 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
37 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
40 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
42 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
45 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
47 if (MI->getOperand(OpNo).getImm())
51 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
53 if (MI->getOperand(OpNo).getImm())
57 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
59 if (MI->getOperand(OpNo).getImm())
63 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
65 if (MI->getOperand(OpNo).getImm()) {
67 printU16ImmOperand(MI, OpNo, O);
71 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
73 if (MI->getOperand(OpNo).getImm())
77 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
79 if (MI->getOperand(OpNo).getImm())
83 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
85 if (MI->getOperand(OpNo).getImm())
89 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
103 case AMDGPU::FLAT_SCR:
112 case AMDGPU::EXEC_LO:
115 case AMDGPU::EXEC_HI:
118 case AMDGPU::FLAT_SCR_LO:
119 O << "flat_scratch_lo";
121 case AMDGPU::FLAT_SCR_HI:
122 O << "flat_scratch_hi";
131 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
134 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
137 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
140 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
143 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
146 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
149 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
152 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
155 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
158 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
161 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
165 O << getRegisterName(reg);
169 // The low 8 bits of the encoding value is the register index, for both VGPRs
171 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
177 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
180 void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
181 int32_t SImm = static_cast<int32_t>(Imm);
182 if (SImm >= -16 && SImm <= 64) {
187 if (Imm == FloatToBits(0.0f))
189 else if (Imm == FloatToBits(1.0f))
191 else if (Imm == FloatToBits(-1.0f))
193 else if (Imm == FloatToBits(0.5f))
195 else if (Imm == FloatToBits(-0.5f))
197 else if (Imm == FloatToBits(2.0f))
199 else if (Imm == FloatToBits(-2.0f))
201 else if (Imm == FloatToBits(4.0f))
203 else if (Imm == FloatToBits(-4.0f))
206 O << formatHex(static_cast<uint64_t>(Imm));
210 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
213 const MCOperand &Op = MI->getOperand(OpNo);
215 switch (Op.getReg()) {
216 // This is the default predicate state, so we don't need to print it.
217 case AMDGPU::PRED_SEL_OFF:
221 printRegOperand(Op.getReg(), O);
224 } else if (Op.isImm()) {
225 printImmediate(Op.getImm(), O);
226 } else if (Op.isFPImm()) {
228 // We special case 0.0 because otherwise it will be printed as an integer.
229 if (Op.getFPImm() == 0.0)
232 printImmediate(FloatToBits(Op.getFPImm()), O);
233 } else if (Op.isExpr()) {
234 const MCExpr *Exp = Op.getExpr();
237 llvm_unreachable("unknown operand type in printOperand");
241 void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
243 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
244 if (InputModifiers & SISrcMods::NEG)
246 if (InputModifiers & SISrcMods::ABS)
248 printOperand(MI, OpNo + 1, O);
249 if (InputModifiers & SISrcMods::ABS)
253 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
255 unsigned Imm = MI->getOperand(OpNum).getImm();
259 } else if (Imm == 1) {
261 } else if (Imm == 0) {
264 llvm_unreachable("Invalid interpolation parameter slot");
268 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
270 printOperand(MI, OpNo, O);
272 printOperand(MI, OpNo + 1, O);
275 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
276 raw_ostream &O, StringRef Asm,
278 const MCOperand &Op = MI->getOperand(OpNo);
280 if (Op.getImm() == 1) {
287 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
289 printIfSet(MI, OpNo, O, "|");
292 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
294 printIfSet(MI, OpNo, O, "_SAT");
297 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
299 if (MI->getOperand(OpNo).getImm())
303 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
305 int Imm = MI->getOperand(OpNo).getImm();
306 if (Imm == SIOutMods::MUL2)
308 else if (Imm == SIOutMods::MUL4)
310 else if (Imm == SIOutMods::DIV2)
314 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
316 int32_t Imm = MI->getOperand(OpNo).getImm();
317 O << Imm << '(' << BitsToFloat(Imm) << ')';
320 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
322 printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
325 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
327 printIfSet(MI, OpNo, O, "-");
330 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
332 switch (MI->getOperand(OpNo).getImm()) {
346 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
348 printIfSet(MI, OpNo, O, "+");
351 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
353 printIfSet(MI, OpNo, O, "ExecMask,");
356 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
358 printIfSet(MI, OpNo, O, "Pred,");
361 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
363 const MCOperand &Op = MI->getOperand(OpNo);
364 if (Op.getImm() == 0) {
369 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
371 const char * chans = "XYZW";
372 int sel = MI->getOperand(OpNo).getImm();
381 O << cb << '[' << sel << ']';
382 } else if (sel >= 448) {
385 } else if (sel >= 0){
390 O << '.' << chans[chan];
393 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
395 int BankSwizzle = MI->getOperand(OpNo).getImm();
396 switch (BankSwizzle) {
398 O << "BS:VEC_021/SCL_122";
401 O << "BS:VEC_120/SCL_212";
404 O << "BS:VEC_102/SCL_221";
418 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
420 unsigned Sel = MI->getOperand(OpNo).getImm();
448 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
450 unsigned CT = MI->getOperand(OpNo).getImm();
463 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
465 int KCacheMode = MI->getOperand(OpNo).getImm();
466 if (KCacheMode > 0) {
467 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
468 O << "CB" << KCacheBank << ':';
469 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
470 int LineSize = (KCacheMode == 1) ? 16 : 32;
471 O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
475 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
477 unsigned SImm16 = MI->getOperand(OpNo).getImm();
478 unsigned Msg = SImm16 & 0xF;
479 if (Msg == 2 || Msg == 3) {
480 unsigned Op = (SImm16 >> 4) & 0xF;
488 unsigned Stream = (SImm16 >> 8) & 0x3;
495 O << " stream " << Stream;
503 O << "unknown(" << Msg << ") ";
506 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
508 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
509 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
510 // works so it might be a misprint in docs.
511 unsigned SImm16 = MI->getOperand(OpNo).getImm();
512 unsigned Vmcnt = SImm16 & 0xF;
513 unsigned Expcnt = (SImm16 >> 4) & 0xF;
514 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
516 bool NeedSpace = false;
519 O << "vmcnt(" << Vmcnt << ')';
526 O << "expcnt(" << Expcnt << ')';
530 if (Lgkmcnt != 0x7) {
533 O << "lgkmcnt(" << Lgkmcnt << ')';
537 #include "AMDGPUGenAsmWriter.inc"