1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
106 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 // Library functions. These default to Expand, but we have instructions
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
136 // Lower floating point store/load to integer store/load to reduce the number
137 // of patterns in tablegen.
138 setOperationAction(ISD::STORE, MVT::f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
141 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
142 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::i64, Promote);
145 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
147 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
150 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
153 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
156 setOperationAction(ISD::STORE, MVT::f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
159 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
162 // Custom lowering of vector stores is required for local address space
164 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
165 // XXX: Native v2i32 local address space stores are possible, but not
166 // currently implemented.
167 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
169 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
170 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
171 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
173 // XXX: This can be change to Custom, once ExpandVectorStores can
174 // handle 64-bit stores.
175 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
179 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
180 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
181 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
184 setOperationAction(ISD::LOAD, MVT::f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
187 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::i64, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
232 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
234 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
235 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
236 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
237 setOperationAction(ISD::FRINT, MVT::f64, Custom);
238 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
241 if (!Subtarget->hasBFI()) {
242 // fcopysign can be done in a single instruction with BFI.
243 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
244 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
247 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
249 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
250 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
251 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
253 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
254 for (MVT VT : ScalarIntVTs) {
255 setOperationAction(ISD::SREM, VT, Expand);
256 setOperationAction(ISD::SDIV, VT, Expand);
258 // GPU does not have divrem function for signed or unsigned.
259 setOperationAction(ISD::SDIVREM, VT, Custom);
260 setOperationAction(ISD::UDIVREM, VT, Custom);
262 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
263 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
264 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
266 setOperationAction(ISD::BSWAP, VT, Expand);
267 setOperationAction(ISD::CTTZ, VT, Expand);
268 setOperationAction(ISD::CTLZ, VT, Expand);
271 if (!Subtarget->hasBCNT(32))
272 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
274 if (!Subtarget->hasBCNT(64))
275 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
277 // The hardware supports 32-bit ROTR, but not ROTL.
278 setOperationAction(ISD::ROTL, MVT::i32, Expand);
279 setOperationAction(ISD::ROTL, MVT::i64, Expand);
280 setOperationAction(ISD::ROTR, MVT::i64, Expand);
282 setOperationAction(ISD::MUL, MVT::i64, Expand);
283 setOperationAction(ISD::MULHU, MVT::i64, Expand);
284 setOperationAction(ISD::MULHS, MVT::i64, Expand);
285 setOperationAction(ISD::UDIV, MVT::i32, Expand);
286 setOperationAction(ISD::UREM, MVT::i32, Expand);
287 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
288 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
289 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
290 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
291 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
293 if (!Subtarget->hasFFBH())
294 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
296 if (!Subtarget->hasFFBL())
297 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
299 static const MVT::SimpleValueType VectorIntTypes[] = {
300 MVT::v2i32, MVT::v4i32
303 for (MVT VT : VectorIntTypes) {
304 // Expand the following operations for the current type by default.
305 setOperationAction(ISD::ADD, VT, Expand);
306 setOperationAction(ISD::AND, VT, Expand);
307 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
308 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
309 setOperationAction(ISD::MUL, VT, Expand);
310 setOperationAction(ISD::OR, VT, Expand);
311 setOperationAction(ISD::SHL, VT, Expand);
312 setOperationAction(ISD::SRA, VT, Expand);
313 setOperationAction(ISD::SRL, VT, Expand);
314 setOperationAction(ISD::ROTL, VT, Expand);
315 setOperationAction(ISD::ROTR, VT, Expand);
316 setOperationAction(ISD::SUB, VT, Expand);
317 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
318 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
319 setOperationAction(ISD::SDIV, VT, Expand);
320 setOperationAction(ISD::UDIV, VT, Expand);
321 setOperationAction(ISD::SREM, VT, Expand);
322 setOperationAction(ISD::UREM, VT, Expand);
323 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
324 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325 setOperationAction(ISD::SDIVREM, VT, Custom);
326 setOperationAction(ISD::UDIVREM, VT, Custom);
327 setOperationAction(ISD::ADDC, VT, Expand);
328 setOperationAction(ISD::SUBC, VT, Expand);
329 setOperationAction(ISD::ADDE, VT, Expand);
330 setOperationAction(ISD::SUBE, VT, Expand);
331 setOperationAction(ISD::SELECT, VT, Expand);
332 setOperationAction(ISD::VSELECT, VT, Expand);
333 setOperationAction(ISD::SELECT_CC, VT, Expand);
334 setOperationAction(ISD::XOR, VT, Expand);
335 setOperationAction(ISD::BSWAP, VT, Expand);
336 setOperationAction(ISD::CTPOP, VT, Expand);
337 setOperationAction(ISD::CTTZ, VT, Expand);
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
339 setOperationAction(ISD::CTLZ, VT, Expand);
340 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
341 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
344 static const MVT::SimpleValueType FloatVectorTypes[] = {
345 MVT::v2f32, MVT::v4f32
348 for (MVT VT : FloatVectorTypes) {
349 setOperationAction(ISD::FABS, VT, Expand);
350 setOperationAction(ISD::FMINNUM, VT, Expand);
351 setOperationAction(ISD::FMAXNUM, VT, Expand);
352 setOperationAction(ISD::FADD, VT, Expand);
353 setOperationAction(ISD::FCEIL, VT, Expand);
354 setOperationAction(ISD::FCOS, VT, Expand);
355 setOperationAction(ISD::FDIV, VT, Expand);
356 setOperationAction(ISD::FEXP2, VT, Expand);
357 setOperationAction(ISD::FLOG2, VT, Expand);
358 setOperationAction(ISD::FREM, VT, Expand);
359 setOperationAction(ISD::FPOW, VT, Expand);
360 setOperationAction(ISD::FFLOOR, VT, Expand);
361 setOperationAction(ISD::FTRUNC, VT, Expand);
362 setOperationAction(ISD::FMUL, VT, Expand);
363 setOperationAction(ISD::FMA, VT, Expand);
364 setOperationAction(ISD::FRINT, VT, Expand);
365 setOperationAction(ISD::FNEARBYINT, VT, Expand);
366 setOperationAction(ISD::FSQRT, VT, Expand);
367 setOperationAction(ISD::FSIN, VT, Expand);
368 setOperationAction(ISD::FSUB, VT, Expand);
369 setOperationAction(ISD::FNEG, VT, Expand);
370 setOperationAction(ISD::SELECT, VT, Expand);
371 setOperationAction(ISD::VSELECT, VT, Expand);
372 setOperationAction(ISD::SELECT_CC, VT, Expand);
373 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
374 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
377 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
378 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
380 setTargetDAGCombine(ISD::MUL);
381 setTargetDAGCombine(ISD::SELECT_CC);
382 setTargetDAGCombine(ISD::STORE);
384 setSchedulingPreference(Sched::RegPressure);
385 setJumpIsExpensive(true);
387 // SI at least has hardware support for floating point exceptions, but no way
388 // of using or handling them is implemented. They are also optional in OpenCL
390 setHasFloatingPointExceptions(false);
392 setSelectIsExpensive(false);
393 PredictableSelectIsExpensive = false;
395 // There are no integer divide instructions, and these expand to a pretty
396 // large sequence of instructions.
397 setIntDivIsCheap(false);
398 setPow2SDivIsCheap(false);
400 // FIXME: Need to really handle these.
401 MaxStoresPerMemcpy = 4096;
402 MaxStoresPerMemmove = 4096;
403 MaxStoresPerMemset = 4096;
406 //===----------------------------------------------------------------------===//
407 // Target Information
408 //===----------------------------------------------------------------------===//
410 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
414 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
418 // The backend supports 32 and 64 bit floating point immediates.
419 // FIXME: Why are we reporting vectors of FP immediates as legal?
420 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
421 EVT ScalarVT = VT.getScalarType();
422 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
425 // We don't want to shrink f64 / f32 constants.
426 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
427 EVT ScalarVT = VT.getScalarType();
428 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
431 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
433 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
436 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
437 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
439 return ((LScalarSize <= CastScalarSize) ||
440 (CastScalarSize >= 32) ||
444 //===---------------------------------------------------------------------===//
446 //===---------------------------------------------------------------------===//
448 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
449 assert(VT.isFloatingPoint());
450 return VT == MVT::f32 || VT == MVT::f64;
453 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
454 assert(VT.isFloatingPoint());
455 return VT == MVT::f32 || VT == MVT::f64;
458 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
459 // Truncate is just accessing a subregister.
460 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
463 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
464 // Truncate is just accessing a subregister.
465 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
466 (Dest->getPrimitiveSizeInBits() % 32 == 0);
469 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
470 const DataLayout *DL = getDataLayout();
471 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
472 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
474 return SrcSize == 32 && DestSize == 64;
477 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
478 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
479 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
480 // this will enable reducing 64-bit operations the 32-bit, which is always
482 return Src == MVT::i32 && Dest == MVT::i64;
485 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
486 return isZExtFree(Val.getValueType(), VT2);
489 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
490 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
491 // limited number of native 64-bit operations. Shrinking an operation to fit
492 // in a single 32-bit register should always be helpful. As currently used,
493 // this is much less general than the name suggests, and is only used in
494 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
495 // not profitable, and may actually be harmful.
496 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
499 //===---------------------------------------------------------------------===//
500 // TargetLowering Callbacks
501 //===---------------------------------------------------------------------===//
503 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
504 const SmallVectorImpl<ISD::InputArg> &Ins) const {
506 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
509 SDValue AMDGPUTargetLowering::LowerReturn(
511 CallingConv::ID CallConv,
513 const SmallVectorImpl<ISD::OutputArg> &Outs,
514 const SmallVectorImpl<SDValue> &OutVals,
515 SDLoc DL, SelectionDAG &DAG) const {
516 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
519 //===---------------------------------------------------------------------===//
520 // Target specific lowering
521 //===---------------------------------------------------------------------===//
523 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
524 SmallVectorImpl<SDValue> &InVals) const {
525 SDValue Callee = CLI.Callee;
526 SelectionDAG &DAG = CLI.DAG;
528 const Function &Fn = *DAG.getMachineFunction().getFunction();
530 StringRef FuncName("<unknown>");
532 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
533 FuncName = G->getSymbol();
534 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
535 FuncName = G->getGlobal()->getName();
537 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
538 DAG.getContext()->diagnose(NoCalls);
542 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
543 SelectionDAG &DAG) const {
544 switch (Op.getOpcode()) {
546 Op.getNode()->dump();
547 llvm_unreachable("Custom lowering code for this"
548 "instruction is not implemented yet!");
550 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
551 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
552 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
553 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
554 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
555 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
556 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
557 case ISD::FREM: return LowerFREM(Op, DAG);
558 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
559 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
560 case ISD::FRINT: return LowerFRINT(Op, DAG);
561 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
562 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
563 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
564 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
565 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
566 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
571 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
572 SmallVectorImpl<SDValue> &Results,
573 SelectionDAG &DAG) const {
574 switch (N->getOpcode()) {
575 case ISD::SIGN_EXTEND_INREG:
576 // Different parts of legalization seem to interpret which type of
577 // sign_extend_inreg is the one to check for custom lowering. The extended
578 // from type is what really matters, but some places check for custom
579 // lowering of the result type. This results in trying to use
580 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
581 // nothing here and let the illegal result integer be handled normally.
584 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
588 Results.push_back(SDValue(Node, 0));
589 Results.push_back(SDValue(Node, 1));
590 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
592 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
596 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
597 if (Lowered.getNode())
598 Results.push_back(Lowered);
606 // FIXME: This implements accesses to initialized globals in the constant
607 // address space by copying them to private and accessing that. It does not
608 // properly handle illegal types or vectors. The private vector loads are not
609 // scalarized, and the illegal scalars hit an assertion. This technique will not
610 // work well with large initializers, and this should eventually be
611 // removed. Initialized globals should be placed into a data section that the
612 // runtime will load into a buffer before the kernel is executed. Uses of the
613 // global need to be replaced with a pointer loaded from an implicit kernel
614 // argument into this buffer holding the copy of the data, which will remove the
615 // need for any of this.
616 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
617 const GlobalValue *GV,
618 const SDValue &InitPtr,
620 SelectionDAG &DAG) const {
621 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
623 Type *InitTy = Init->getType();
625 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
626 EVT VT = EVT::getEVT(InitTy);
627 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
628 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
629 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
630 TD->getPrefTypeAlignment(InitTy));
633 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
634 EVT VT = EVT::getEVT(CFP->getType());
635 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
636 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
637 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
638 TD->getPrefTypeAlignment(CFP->getType()));
641 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
642 const StructLayout *SL = TD->getStructLayout(ST);
644 EVT PtrVT = InitPtr.getValueType();
645 SmallVector<SDValue, 8> Chains;
647 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
648 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
649 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
651 Constant *Elt = Init->getAggregateElement(I);
652 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
655 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
658 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
659 EVT PtrVT = InitPtr.getValueType();
661 unsigned NumElements;
662 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
663 NumElements = AT->getNumElements();
664 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
665 NumElements = VT->getNumElements();
667 llvm_unreachable("Unexpected type");
669 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
670 SmallVector<SDValue, 8> Chains;
671 for (unsigned i = 0; i < NumElements; ++i) {
672 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
673 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
675 Constant *Elt = Init->getAggregateElement(i);
676 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
679 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
682 if (isa<UndefValue>(Init)) {
683 EVT VT = EVT::getEVT(InitTy);
684 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
685 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
686 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
687 TD->getPrefTypeAlignment(InitTy));
691 llvm_unreachable("Unhandled constant initializer");
694 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
696 SelectionDAG &DAG) const {
698 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
699 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
700 const GlobalValue *GV = G->getGlobal();
702 switch (G->getAddressSpace()) {
703 default: llvm_unreachable("Global Address lowering not implemented for this "
705 case AMDGPUAS::LOCAL_ADDRESS: {
706 // XXX: What does the value of G->getOffset() mean?
707 assert(G->getOffset() == 0 &&
708 "Do not know what to do with an non-zero offset");
711 if (MFI->LocalMemoryObjects.count(GV) == 0) {
712 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
713 Offset = MFI->LDSSize;
714 MFI->LocalMemoryObjects[GV] = Offset;
715 // XXX: Account for alignment?
716 MFI->LDSSize += Size;
718 Offset = MFI->LocalMemoryObjects[GV];
721 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
723 case AMDGPUAS::CONSTANT_ADDRESS: {
724 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
725 Type *EltType = GV->getType()->getElementType();
726 unsigned Size = TD->getTypeAllocSize(EltType);
727 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
729 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
730 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
732 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
733 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
735 const GlobalVariable *Var = cast<GlobalVariable>(GV);
736 if (!Var->hasInitializer()) {
737 // This has no use, but bugpoint will hit it.
738 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
741 const Constant *Init = Var->getInitializer();
742 SmallVector<SDNode*, 8> WorkList;
744 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
745 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
746 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
748 WorkList.push_back(*I);
750 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
751 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
752 E = WorkList.end(); I != E; ++I) {
753 SmallVector<SDValue, 8> Ops;
754 Ops.push_back(Chain);
755 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
756 Ops.push_back((*I)->getOperand(i));
758 DAG.UpdateNodeOperands(*I, Ops);
760 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
765 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
766 SelectionDAG &DAG) const {
767 SmallVector<SDValue, 8> Args;
768 SDValue A = Op.getOperand(0);
769 SDValue B = Op.getOperand(1);
771 DAG.ExtractVectorElements(A, Args);
772 DAG.ExtractVectorElements(B, Args);
774 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
777 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
778 SelectionDAG &DAG) const {
780 SmallVector<SDValue, 8> Args;
781 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
782 EVT VT = Op.getValueType();
783 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
784 VT.getVectorNumElements());
786 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
789 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
790 SelectionDAG &DAG) const {
792 MachineFunction &MF = DAG.getMachineFunction();
793 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
794 getTargetMachine().getSubtargetImpl()->getFrameLowering());
796 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
798 unsigned FrameIndex = FIN->getIndex();
799 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
800 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
804 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
805 SelectionDAG &DAG) const {
806 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
808 EVT VT = Op.getValueType();
810 switch (IntrinsicID) {
812 case AMDGPUIntrinsic::AMDGPU_abs:
813 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
814 return LowerIntrinsicIABS(Op, DAG);
815 case AMDGPUIntrinsic::AMDGPU_lrp:
816 return LowerIntrinsicLRP(Op, DAG);
817 case AMDGPUIntrinsic::AMDGPU_fract:
818 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
819 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
821 case AMDGPUIntrinsic::AMDGPU_clamp:
822 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
823 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
824 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
826 case Intrinsic::AMDGPU_div_scale: {
827 // 3rd parameter required to be a constant.
828 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
830 return DAG.getUNDEF(VT);
832 // Translate to the operands expected by the machine instruction. The
833 // first parameter must be the same as the first instruction.
834 SDValue Numerator = Op.getOperand(1);
835 SDValue Denominator = Op.getOperand(2);
837 // Note this order is opposite of the machine instruction's operations,
838 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
839 // intrinsic has the numerator as the first operand to match a normal
840 // division operation.
842 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
844 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
845 Denominator, Numerator);
848 case Intrinsic::AMDGPU_div_fmas:
849 // FIXME: Dropping bool parameter. Work is needed to support the implicit
851 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
852 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
854 case Intrinsic::AMDGPU_div_fixup:
855 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
856 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
858 case Intrinsic::AMDGPU_trig_preop:
859 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
860 Op.getOperand(1), Op.getOperand(2));
862 case Intrinsic::AMDGPU_rcp:
863 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
865 case Intrinsic::AMDGPU_rsq:
866 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
868 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
869 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
871 case Intrinsic::AMDGPU_rsq_clamped:
872 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
874 case Intrinsic::AMDGPU_ldexp:
875 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
878 case AMDGPUIntrinsic::AMDGPU_imax:
879 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
881 case AMDGPUIntrinsic::AMDGPU_umax:
882 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
884 case AMDGPUIntrinsic::AMDGPU_imin:
885 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
887 case AMDGPUIntrinsic::AMDGPU_umin:
888 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
891 case AMDGPUIntrinsic::AMDGPU_umul24:
892 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
893 Op.getOperand(1), Op.getOperand(2));
895 case AMDGPUIntrinsic::AMDGPU_imul24:
896 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
897 Op.getOperand(1), Op.getOperand(2));
899 case AMDGPUIntrinsic::AMDGPU_umad24:
900 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
901 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
903 case AMDGPUIntrinsic::AMDGPU_imad24:
904 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
905 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
907 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
908 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
910 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
911 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
913 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
914 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
916 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
917 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
919 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
920 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
925 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
926 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
931 case AMDGPUIntrinsic::AMDGPU_bfi:
932 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
937 case AMDGPUIntrinsic::AMDGPU_bfm:
938 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
942 case AMDGPUIntrinsic::AMDGPU_brev:
943 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
945 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
946 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
948 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
949 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
950 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
951 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
955 ///IABS(a) = SMAX(sub(0, a), a)
956 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
957 SelectionDAG &DAG) const {
959 EVT VT = Op.getValueType();
960 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
963 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
966 /// Linear Interpolation
967 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
968 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
969 SelectionDAG &DAG) const {
971 EVT VT = Op.getValueType();
972 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
973 DAG.getConstantFP(1.0f, MVT::f32),
975 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
977 return DAG.getNode(ISD::FADD, DL, VT,
978 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
982 /// \brief Generate Min/Max node
983 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
984 SelectionDAG &DAG) const {
986 EVT VT = N->getValueType(0);
988 SDValue LHS = N->getOperand(0);
989 SDValue RHS = N->getOperand(1);
990 SDValue True = N->getOperand(2);
991 SDValue False = N->getOperand(3);
992 SDValue CC = N->getOperand(4);
994 if (VT != MVT::f32 ||
995 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
999 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1008 case ISD::SETFALSE2:
1013 llvm_unreachable("Operation should already be optimised!");
1020 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
1021 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1029 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
1030 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1032 case ISD::SETCC_INVALID:
1033 llvm_unreachable("Invalid setcc condcode!");
1038 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1039 SelectionDAG &DAG) const {
1040 LoadSDNode *Load = cast<LoadSDNode>(Op);
1041 EVT MemVT = Load->getMemoryVT();
1042 EVT MemEltVT = MemVT.getVectorElementType();
1044 EVT LoadVT = Op.getValueType();
1045 EVT EltVT = LoadVT.getVectorElementType();
1046 EVT PtrVT = Load->getBasePtr().getValueType();
1048 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1049 SmallVector<SDValue, 8> Loads;
1050 SmallVector<SDValue, 8> Chains;
1053 unsigned MemEltSize = MemEltVT.getStoreSize();
1054 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1056 for (unsigned i = 0; i < NumElts; ++i) {
1057 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1058 DAG.getConstant(i * MemEltSize, PtrVT));
1061 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1062 Load->getChain(), Ptr,
1063 SrcValue.getWithOffset(i * MemEltSize),
1064 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1065 Load->isInvariant(), Load->getAlignment());
1066 Loads.push_back(NewLoad.getValue(0));
1067 Chains.push_back(NewLoad.getValue(1));
1071 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1072 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1075 return DAG.getMergeValues(Ops, SL);
1078 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1079 SelectionDAG &DAG) const {
1080 EVT VT = Op.getValueType();
1082 // If this is a 2 element vector, we really want to scalarize and not create
1083 // weird 1 element vectors.
1084 if (VT.getVectorNumElements() == 2)
1085 return ScalarizeVectorLoad(Op, DAG);
1087 LoadSDNode *Load = cast<LoadSDNode>(Op);
1088 SDValue BasePtr = Load->getBasePtr();
1089 EVT PtrVT = BasePtr.getValueType();
1090 EVT MemVT = Load->getMemoryVT();
1092 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1095 EVT LoMemVT, HiMemVT;
1098 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1099 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1100 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1102 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1103 Load->getChain(), BasePtr,
1105 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1106 Load->isInvariant(), Load->getAlignment());
1108 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1109 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1112 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1113 Load->getChain(), HiPtr,
1114 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1115 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1116 Load->isInvariant(), Load->getAlignment());
1119 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1120 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1121 LoLoad.getValue(1), HiLoad.getValue(1))
1124 return DAG.getMergeValues(Ops, SL);
1127 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1128 SelectionDAG &DAG) const {
1129 StoreSDNode *Store = cast<StoreSDNode>(Op);
1130 EVT MemVT = Store->getMemoryVT();
1131 unsigned MemBits = MemVT.getSizeInBits();
1133 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1134 // truncating store into an i32 store.
1135 // XXX: We could also handle optimize other vector bitwidths.
1136 if (!MemVT.isVector() || MemBits > 32) {
1141 SDValue Value = Store->getValue();
1142 EVT VT = Value.getValueType();
1143 EVT ElemVT = VT.getVectorElementType();
1144 SDValue Ptr = Store->getBasePtr();
1145 EVT MemEltVT = MemVT.getVectorElementType();
1146 unsigned MemEltBits = MemEltVT.getSizeInBits();
1147 unsigned MemNumElements = MemVT.getVectorNumElements();
1148 unsigned PackedSize = MemVT.getStoreSizeInBits();
1149 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1151 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1153 SDValue PackedValue;
1154 for (unsigned i = 0; i < MemNumElements; ++i) {
1155 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1156 DAG.getConstant(i, MVT::i32));
1157 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1158 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1160 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1161 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1166 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1170 if (PackedSize < 32) {
1171 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1172 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1173 Store->getMemOperand()->getPointerInfo(),
1175 Store->isNonTemporal(), Store->isVolatile(),
1176 Store->getAlignment());
1179 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1180 Store->getMemOperand()->getPointerInfo(),
1181 Store->isVolatile(), Store->isNonTemporal(),
1182 Store->getAlignment());
1185 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1186 SelectionDAG &DAG) const {
1187 StoreSDNode *Store = cast<StoreSDNode>(Op);
1188 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1189 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1190 EVT PtrVT = Store->getBasePtr().getValueType();
1191 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1194 SmallVector<SDValue, 8> Chains;
1196 unsigned EltSize = MemEltVT.getStoreSize();
1197 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1199 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1200 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1202 DAG.getConstant(i, MVT::i32));
1204 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1205 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1207 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1208 SrcValue.getWithOffset(i * EltSize),
1209 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1210 Store->getAlignment());
1211 Chains.push_back(NewStore);
1214 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1217 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1218 SelectionDAG &DAG) const {
1219 StoreSDNode *Store = cast<StoreSDNode>(Op);
1220 SDValue Val = Store->getValue();
1221 EVT VT = Val.getValueType();
1223 // If this is a 2 element vector, we really want to scalarize and not create
1224 // weird 1 element vectors.
1225 if (VT.getVectorNumElements() == 2)
1226 return ScalarizeVectorStore(Op, DAG);
1228 EVT MemVT = Store->getMemoryVT();
1229 SDValue Chain = Store->getChain();
1230 SDValue BasePtr = Store->getBasePtr();
1234 EVT LoMemVT, HiMemVT;
1237 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1238 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1239 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1241 EVT PtrVT = BasePtr.getValueType();
1242 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1243 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1245 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1247 = DAG.getTruncStore(Chain, SL, Lo,
1251 Store->isNonTemporal(),
1252 Store->isVolatile(),
1253 Store->getAlignment());
1255 = DAG.getTruncStore(Chain, SL, Hi,
1257 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1259 Store->isNonTemporal(),
1260 Store->isVolatile(),
1261 Store->getAlignment());
1263 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1267 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1269 LoadSDNode *Load = cast<LoadSDNode>(Op);
1270 ISD::LoadExtType ExtType = Load->getExtensionType();
1271 EVT VT = Op.getValueType();
1272 EVT MemVT = Load->getMemoryVT();
1274 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1275 // We can do the extload to 32-bits, and then need to separately extend to
1278 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1282 Load->getMemOperand());
1285 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1286 ExtLoad32.getValue(1)
1289 return DAG.getMergeValues(Ops, DL);
1292 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1293 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1294 // FIXME: Copied from PPC
1295 // First, load into 32 bits, then truncate to 1 bit.
1297 SDValue Chain = Load->getChain();
1298 SDValue BasePtr = Load->getBasePtr();
1299 MachineMemOperand *MMO = Load->getMemOperand();
1301 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1302 BasePtr, MVT::i8, MMO);
1305 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1309 return DAG.getMergeValues(Ops, DL);
1312 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1313 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1314 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1318 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1319 DAG.getConstant(2, MVT::i32));
1320 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1321 Load->getChain(), Ptr,
1322 DAG.getTargetConstant(0, MVT::i32),
1324 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1326 DAG.getConstant(0x3, MVT::i32));
1327 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1328 DAG.getConstant(3, MVT::i32));
1330 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1332 EVT MemEltVT = MemVT.getScalarType();
1333 if (ExtType == ISD::SEXTLOAD) {
1334 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1337 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1341 return DAG.getMergeValues(Ops, DL);
1345 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1349 return DAG.getMergeValues(Ops, DL);
1352 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1354 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1355 if (Result.getNode()) {
1359 StoreSDNode *Store = cast<StoreSDNode>(Op);
1360 SDValue Chain = Store->getChain();
1361 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1362 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1363 Store->getValue().getValueType().isVector()) {
1364 return ScalarizeVectorStore(Op, DAG);
1367 EVT MemVT = Store->getMemoryVT();
1368 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1369 MemVT.bitsLT(MVT::i32)) {
1371 if (Store->getMemoryVT() == MVT::i8) {
1373 } else if (Store->getMemoryVT() == MVT::i16) {
1376 SDValue BasePtr = Store->getBasePtr();
1377 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1378 DAG.getConstant(2, MVT::i32));
1379 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1380 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1382 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1383 DAG.getConstant(0x3, MVT::i32));
1385 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1386 DAG.getConstant(3, MVT::i32));
1388 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1391 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1393 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1394 MaskedValue, ShiftAmt);
1396 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1398 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1399 DAG.getConstant(0xffffffff, MVT::i32));
1400 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1402 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1403 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1404 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1409 // This is a shortcut for integer division because we have fast i32<->f32
1410 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1411 // float is enough to accurately represent up to a 24-bit integer.
1412 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1414 EVT VT = Op.getValueType();
1415 SDValue LHS = Op.getOperand(0);
1416 SDValue RHS = Op.getOperand(1);
1417 MVT IntVT = MVT::i32;
1418 MVT FltVT = MVT::f32;
1420 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1421 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1423 if (VT.isVector()) {
1424 unsigned NElts = VT.getVectorNumElements();
1425 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1426 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1429 unsigned BitSize = VT.getScalarType().getSizeInBits();
1431 SDValue jq = DAG.getConstant(1, IntVT);
1434 // char|short jq = ia ^ ib;
1435 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1437 // jq = jq >> (bitsize - 2)
1438 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1441 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1444 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1447 // int ia = (int)LHS;
1449 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1451 // int ib, (int)RHS;
1453 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1455 // float fa = (float)ia;
1456 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1458 // float fb = (float)ib;
1459 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1461 // float fq = native_divide(fa, fb);
1462 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1463 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1466 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1468 // float fqneg = -fq;
1469 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1471 // float fr = mad(fqneg, fb, fa);
1472 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1473 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1475 // int iq = (int)fq;
1476 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1479 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1482 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1484 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1486 // int cv = fr >= fb;
1487 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1489 // jq = (cv ? jq : 0);
1490 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1492 // dst = trunc/extend to legal type
1493 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1496 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1498 // Rem needs compensation, it's easier to recompute it
1499 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1500 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1506 return DAG.getMergeValues(Res, DL);
1509 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1510 SelectionDAG &DAG) const {
1512 EVT VT = Op.getValueType();
1514 SDValue Num = Op.getOperand(0);
1515 SDValue Den = Op.getOperand(1);
1517 if (VT == MVT::i32) {
1518 if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
1519 DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
1520 // TODO: We technically could do this for i64, but shouldn't that just be
1521 // handled by something generally reducing 64-bit division on 32-bit
1522 // values to 32-bit?
1523 return LowerDIVREM24(Op, DAG, false);
1527 // RCP = URECIP(Den) = 2^32 / Den + e
1528 // e is rounding error.
1529 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1531 // RCP_LO = mul(RCP, Den) */
1532 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1534 // RCP_HI = mulhu (RCP, Den) */
1535 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1537 // NEG_RCP_LO = -RCP_LO
1538 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1541 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1542 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1545 // Calculate the rounding error from the URECIP instruction
1546 // E = mulhu(ABS_RCP_LO, RCP)
1547 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1549 // RCP_A_E = RCP + E
1550 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1552 // RCP_S_E = RCP - E
1553 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1555 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1556 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1559 // Quotient = mulhu(Tmp0, Num)
1560 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1562 // Num_S_Remainder = Quotient * Den
1563 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1565 // Remainder = Num - Num_S_Remainder
1566 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1568 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1569 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1570 DAG.getConstant(-1, VT),
1571 DAG.getConstant(0, VT),
1573 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1574 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1576 DAG.getConstant(-1, VT),
1577 DAG.getConstant(0, VT),
1579 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1580 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1583 // Calculate Division result:
1585 // Quotient_A_One = Quotient + 1
1586 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1587 DAG.getConstant(1, VT));
1589 // Quotient_S_One = Quotient - 1
1590 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1591 DAG.getConstant(1, VT));
1593 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1594 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1595 Quotient, Quotient_A_One, ISD::SETEQ);
1597 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1598 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1599 Quotient_S_One, Div, ISD::SETEQ);
1601 // Calculate Rem result:
1603 // Remainder_S_Den = Remainder - Den
1604 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1606 // Remainder_A_Den = Remainder + Den
1607 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1609 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1610 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1611 Remainder, Remainder_S_Den, ISD::SETEQ);
1613 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1614 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1615 Remainder_A_Den, Rem, ISD::SETEQ);
1620 return DAG.getMergeValues(Ops, DL);
1623 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1624 SelectionDAG &DAG) const {
1626 EVT VT = Op.getValueType();
1628 SDValue LHS = Op.getOperand(0);
1629 SDValue RHS = Op.getOperand(1);
1631 if (VT == MVT::i32) {
1632 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1633 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1634 // TODO: We technically could do this for i64, but shouldn't that just be
1635 // handled by something generally reducing 64-bit division on 32-bit
1636 // values to 32-bit?
1637 return LowerDIVREM24(Op, DAG, true);
1641 SDValue Zero = DAG.getConstant(0, VT);
1642 SDValue NegOne = DAG.getConstant(-1, VT);
1644 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1645 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1646 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1647 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1649 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1650 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1652 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1653 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1655 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1656 SDValue Rem = Div.getValue(1);
1658 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1659 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1661 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1662 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1668 return DAG.getMergeValues(Res, DL);
1671 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1672 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1674 EVT VT = Op.getValueType();
1675 SDValue X = Op.getOperand(0);
1676 SDValue Y = Op.getOperand(1);
1678 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1679 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1680 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1682 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1685 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1687 SDValue Src = Op.getOperand(0);
1689 // result = trunc(src)
1690 // if (src > 0.0 && src != result)
1693 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1695 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1696 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1698 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1700 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1701 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1702 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1704 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1705 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1708 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1710 SDValue Src = Op.getOperand(0);
1712 assert(Op.getValueType() == MVT::f64);
1714 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1715 const SDValue One = DAG.getConstant(1, MVT::i32);
1717 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1719 // Extract the upper half, since this is where we will find the sign and
1721 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1723 const unsigned FractBits = 52;
1724 const unsigned ExpBits = 11;
1726 // Extract the exponent.
1727 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1729 DAG.getConstant(FractBits - 32, MVT::i32),
1730 DAG.getConstant(ExpBits, MVT::i32));
1731 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1732 DAG.getConstant(1023, MVT::i32));
1734 // Extract the sign bit.
1735 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1736 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1738 // Extend back to to 64-bits.
1739 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1741 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1743 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1744 const SDValue FractMask
1745 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1747 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1748 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1749 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1751 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1753 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1755 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1756 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1758 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1759 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1761 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1764 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1766 SDValue Src = Op.getOperand(0);
1768 assert(Op.getValueType() == MVT::f64);
1770 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1771 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1772 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1774 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1775 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1777 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1779 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1780 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1782 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1783 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1785 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1788 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1789 // FNEARBYINT and FRINT are the same, except in their handling of FP
1790 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1791 // rint, so just treat them as equivalent.
1792 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1795 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1797 SDValue Src = Op.getOperand(0);
1799 // result = trunc(src);
1800 // if (src < 0.0 && src != result)
1803 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1805 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1806 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1808 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1810 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1811 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1812 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1814 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1815 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1818 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
1819 bool Signed) const {
1821 SDValue Src = Op.getOperand(0);
1823 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1825 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1826 DAG.getConstant(0, MVT::i32));
1827 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1828 DAG.getConstant(1, MVT::i32));
1830 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
1833 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
1835 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
1836 DAG.getConstant(32, MVT::i32));
1838 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
1841 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1842 SelectionDAG &DAG) const {
1843 SDValue S0 = Op.getOperand(0);
1844 if (S0.getValueType() != MVT::i64)
1847 EVT DestVT = Op.getValueType();
1848 if (DestVT == MVT::f64)
1849 return LowerINT_TO_FP64(Op, DAG, false);
1851 assert(DestVT == MVT::f32);
1855 // f32 uint_to_fp i64
1856 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1857 DAG.getConstant(0, MVT::i32));
1858 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1859 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1860 DAG.getConstant(1, MVT::i32));
1861 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1862 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1863 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1864 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1867 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
1868 SelectionDAG &DAG) const {
1869 SDValue Src = Op.getOperand(0);
1870 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
1871 return LowerINT_TO_FP64(Op, DAG, true);
1876 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
1877 bool Signed) const {
1880 SDValue Src = Op.getOperand(0);
1882 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1885 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
1887 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
1889 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
1891 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
1894 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
1896 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
1897 MVT::i32, FloorMul);
1898 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
1900 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
1902 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
1905 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
1906 SelectionDAG &DAG) const {
1907 SDValue Src = Op.getOperand(0);
1909 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
1910 return LowerFP64_TO_INT(Op, DAG, true);
1915 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
1916 SelectionDAG &DAG) const {
1917 SDValue Src = Op.getOperand(0);
1919 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
1920 return LowerFP64_TO_INT(Op, DAG, false);
1925 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1926 SelectionDAG &DAG) const {
1927 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1928 MVT VT = Op.getSimpleValueType();
1929 MVT ScalarVT = VT.getScalarType();
1934 SDValue Src = Op.getOperand(0);
1937 // TODO: Don't scalarize on Evergreen?
1938 unsigned NElts = VT.getVectorNumElements();
1939 SmallVector<SDValue, 8> Args;
1940 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1942 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1943 for (unsigned I = 0; I < NElts; ++I)
1944 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1946 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1949 //===----------------------------------------------------------------------===//
1950 // Custom DAG optimizations
1951 //===----------------------------------------------------------------------===//
1953 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1954 APInt KnownZero, KnownOne;
1955 EVT VT = Op.getValueType();
1956 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1958 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1961 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1962 EVT VT = Op.getValueType();
1964 // In order for this to be a signed 24-bit value, bit 23, must
1966 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1967 // as unsigned 24-bit values.
1968 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1971 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1973 SelectionDAG &DAG = DCI.DAG;
1974 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1975 EVT VT = Op.getValueType();
1977 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1978 APInt KnownZero, KnownOne;
1979 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1980 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1981 DCI.CommitTargetLoweringOpt(TLO);
1984 template <typename IntTy>
1985 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1986 uint32_t Offset, uint32_t Width) {
1987 if (Width + Offset < 32) {
1988 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
1989 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
1990 return DAG.getConstant(Result, MVT::i32);
1993 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1996 static bool usesAllNormalStores(SDNode *LoadVal) {
1997 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
1998 if (!ISD::isNormalStore(*I))
2005 // If we have a copy of an illegal type, replace it with a load / store of an
2006 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2007 // instructions emitted when handling extloads and truncstores. Ideally we could
2008 // recognize the pack / unpack pattern to eliminate it.
2009 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2010 DAGCombinerInfo &DCI) const {
2011 if (!DCI.isBeforeLegalize())
2014 StoreSDNode *SN = cast<StoreSDNode>(N);
2015 SDValue Value = SN->getValue();
2016 EVT VT = Value.getValueType();
2018 if (isTypeLegal(VT) || SN->isVolatile() || !ISD::isNormalLoad(Value.getNode()))
2021 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2022 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2025 EVT MemVT = LoadVal->getMemoryVT();
2028 SelectionDAG &DAG = DCI.DAG;
2029 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2031 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2033 LoadVal->getChain(),
2034 LoadVal->getBasePtr(),
2035 LoadVal->getOffset(),
2037 LoadVal->getMemOperand());
2039 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2040 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2042 return DAG.getStore(SN->getChain(), SL, NewLoad,
2043 SN->getBasePtr(), SN->getMemOperand());
2046 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2047 DAGCombinerInfo &DCI) const {
2048 EVT VT = N->getValueType(0);
2050 if (VT.isVector() || VT.getSizeInBits() > 32)
2053 SelectionDAG &DAG = DCI.DAG;
2056 SDValue N0 = N->getOperand(0);
2057 SDValue N1 = N->getOperand(1);
2060 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2061 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2062 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2063 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2064 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2065 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2066 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2067 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2072 // We need to use sext even for MUL_U24, because MUL_U24 is used
2073 // for signed multiply of 8 and 16-bit types.
2074 return DAG.getSExtOrTrunc(Mul, DL, VT);
2077 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2078 DAGCombinerInfo &DCI) const {
2079 SelectionDAG &DAG = DCI.DAG;
2082 switch(N->getOpcode()) {
2085 return performMulCombine(N, DCI);
2086 case AMDGPUISD::MUL_I24:
2087 case AMDGPUISD::MUL_U24: {
2088 SDValue N0 = N->getOperand(0);
2089 SDValue N1 = N->getOperand(1);
2090 simplifyI24(N0, DCI);
2091 simplifyI24(N1, DCI);
2094 case ISD::SELECT_CC: {
2095 return CombineMinMax(N, DAG);
2097 case AMDGPUISD::BFE_I32:
2098 case AMDGPUISD::BFE_U32: {
2099 assert(!N->getValueType(0).isVector() &&
2100 "Vector handling of BFE not implemented");
2101 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2105 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2107 return DAG.getConstant(0, MVT::i32);
2109 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2113 SDValue BitsFrom = N->getOperand(0);
2114 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2116 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2118 if (OffsetVal == 0) {
2119 // This is already sign / zero extended, so try to fold away extra BFEs.
2120 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2122 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2123 if (OpSignBits >= SignBits)
2126 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2128 // This is a sign_extend_inreg. Replace it to take advantage of existing
2129 // DAG Combines. If not eliminated, we will match back to BFE during
2132 // TODO: The sext_inreg of extended types ends, although we can could
2133 // handle them in a single BFE.
2134 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2135 DAG.getValueType(SmallVT));
2138 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2141 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2143 return constantFoldBFE<int32_t>(DAG,
2144 CVal->getSExtValue(),
2149 return constantFoldBFE<uint32_t>(DAG,
2150 CVal->getZExtValue(),
2155 if ((OffsetVal + WidthVal) >= 32) {
2156 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2157 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2158 BitsFrom, ShiftVal);
2161 if (BitsFrom.hasOneUse()) {
2162 APInt Demanded = APInt::getBitsSet(32,
2164 OffsetVal + WidthVal);
2166 APInt KnownZero, KnownOne;
2167 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2168 !DCI.isBeforeLegalizeOps());
2169 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2170 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2171 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2172 KnownZero, KnownOne, TLO)) {
2173 DCI.CommitTargetLoweringOpt(TLO);
2181 return performStoreCombine(N, DCI);
2186 //===----------------------------------------------------------------------===//
2188 //===----------------------------------------------------------------------===//
2190 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2193 const SmallVectorImpl<ISD::InputArg> &Ins,
2194 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2196 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2197 if (Ins[i].ArgVT == Ins[i].VT) {
2198 OrigIns.push_back(Ins[i]);
2203 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2204 // Vector has been split into scalars.
2205 VT = Ins[i].ArgVT.getVectorElementType();
2206 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2207 Ins[i].ArgVT.getVectorElementType() !=
2208 Ins[i].VT.getVectorElementType()) {
2209 // Vector elements have been promoted
2212 // Vector has been spilt into smaller vectors.
2216 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2217 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2218 OrigIns.push_back(Arg);
2222 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2223 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2224 return CFP->isExactlyValue(1.0);
2226 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2227 return C->isAllOnesValue();
2232 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2233 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2234 return CFP->getValueAPF().isZero();
2236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2237 return C->isNullValue();
2242 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2243 const TargetRegisterClass *RC,
2244 unsigned Reg, EVT VT) const {
2245 MachineFunction &MF = DAG.getMachineFunction();
2246 MachineRegisterInfo &MRI = MF.getRegInfo();
2247 unsigned VirtualRegister;
2248 if (!MRI.isLiveIn(Reg)) {
2249 VirtualRegister = MRI.createVirtualRegister(RC);
2250 MRI.addLiveIn(Reg, VirtualRegister);
2252 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2254 return DAG.getRegister(VirtualRegister, VT);
2257 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2259 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2261 default: return nullptr;
2263 NODE_NAME_CASE(CALL);
2264 NODE_NAME_CASE(UMUL);
2265 NODE_NAME_CASE(RET_FLAG);
2266 NODE_NAME_CASE(BRANCH_COND);
2269 NODE_NAME_CASE(DWORDADDR)
2270 NODE_NAME_CASE(FRACT)
2271 NODE_NAME_CASE(CLAMP)
2273 NODE_NAME_CASE(FMAX)
2274 NODE_NAME_CASE(SMAX)
2275 NODE_NAME_CASE(UMAX)
2276 NODE_NAME_CASE(FMIN)
2277 NODE_NAME_CASE(SMIN)
2278 NODE_NAME_CASE(UMIN)
2279 NODE_NAME_CASE(URECIP)
2280 NODE_NAME_CASE(DIV_SCALE)
2281 NODE_NAME_CASE(DIV_FMAS)
2282 NODE_NAME_CASE(DIV_FIXUP)
2283 NODE_NAME_CASE(TRIG_PREOP)
2286 NODE_NAME_CASE(RSQ_LEGACY)
2287 NODE_NAME_CASE(RSQ_CLAMPED)
2288 NODE_NAME_CASE(LDEXP)
2289 NODE_NAME_CASE(DOT4)
2290 NODE_NAME_CASE(BFE_U32)
2291 NODE_NAME_CASE(BFE_I32)
2294 NODE_NAME_CASE(BREV)
2295 NODE_NAME_CASE(MUL_U24)
2296 NODE_NAME_CASE(MUL_I24)
2297 NODE_NAME_CASE(MAD_U24)
2298 NODE_NAME_CASE(MAD_I24)
2299 NODE_NAME_CASE(EXPORT)
2300 NODE_NAME_CASE(CONST_ADDRESS)
2301 NODE_NAME_CASE(REGISTER_LOAD)
2302 NODE_NAME_CASE(REGISTER_STORE)
2303 NODE_NAME_CASE(LOAD_CONSTANT)
2304 NODE_NAME_CASE(LOAD_INPUT)
2305 NODE_NAME_CASE(SAMPLE)
2306 NODE_NAME_CASE(SAMPLEB)
2307 NODE_NAME_CASE(SAMPLED)
2308 NODE_NAME_CASE(SAMPLEL)
2309 NODE_NAME_CASE(CVT_F32_UBYTE0)
2310 NODE_NAME_CASE(CVT_F32_UBYTE1)
2311 NODE_NAME_CASE(CVT_F32_UBYTE2)
2312 NODE_NAME_CASE(CVT_F32_UBYTE3)
2313 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2314 NODE_NAME_CASE(CONST_DATA_PTR)
2315 NODE_NAME_CASE(STORE_MSKOR)
2316 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2320 static void computeKnownBitsForMinMax(const SDValue Op0,
2324 const SelectionDAG &DAG,
2326 APInt Op0Zero, Op0One;
2327 APInt Op1Zero, Op1One;
2328 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2329 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2331 KnownZero = Op0Zero & Op1Zero;
2332 KnownOne = Op0One & Op1One;
2335 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2339 const SelectionDAG &DAG,
2340 unsigned Depth) const {
2342 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2346 unsigned Opc = Op.getOpcode();
2351 case ISD::INTRINSIC_WO_CHAIN: {
2352 // FIXME: The intrinsic should just use the node.
2353 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2354 case AMDGPUIntrinsic::AMDGPU_imax:
2355 case AMDGPUIntrinsic::AMDGPU_umax:
2356 case AMDGPUIntrinsic::AMDGPU_imin:
2357 case AMDGPUIntrinsic::AMDGPU_umin:
2358 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2359 KnownZero, KnownOne, DAG, Depth);
2367 case AMDGPUISD::SMAX:
2368 case AMDGPUISD::UMAX:
2369 case AMDGPUISD::SMIN:
2370 case AMDGPUISD::UMIN:
2371 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2372 KnownZero, KnownOne, DAG, Depth);
2375 case AMDGPUISD::BFE_I32:
2376 case AMDGPUISD::BFE_U32: {
2377 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2381 unsigned BitWidth = 32;
2382 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2384 if (Opc == AMDGPUISD::BFE_U32)
2385 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2392 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2394 const SelectionDAG &DAG,
2395 unsigned Depth) const {
2396 switch (Op.getOpcode()) {
2397 case AMDGPUISD::BFE_I32: {
2398 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2402 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2403 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2404 if (!Offset || !Offset->isNullValue())
2407 // TODO: Could probably figure something out with non-0 offsets.
2408 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2409 return std::max(SignBits, Op0SignBits);
2412 case AMDGPUISD::BFE_U32: {
2413 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2414 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;