lib/Target/R600/AMDGPU.td

   1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9
  10 include "llvm/Target/Target.td"
  11
  12 //===----------------------------------------------------------------------===//
  13 // Subtarget Features
  14 //===----------------------------------------------------------------------===//
  15
  16 // Debugging Features
  17
  18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
  19         "DumpCode",
  20         "true",
  21         "Dump MachineInstrs in the CodeEmitter">;
  22
  23 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
  24         "DumpCode",
  25         "true",
  26         "Dump MachineInstrs in the CodeEmitter">;
  27
  28 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
  29         "EnableIRStructurizer",
  30         "false",
  31         "Disable IR Structurizer">;
  32
  33 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
  34         "EnablePromoteAlloca",
  35         "true",
  36         "Enable promote alloca pass">;
  37
  38 // Target features
  39
  40 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
  41         "EnableIfCvt",
  42         "false",
  43         "Disable the if conversion pass">;
  44
  45 def FeatureFP64 : SubtargetFeature<"fp64",
  46         "FP64",
  47         "true",
  48         "Enable double precision operations">;
  49
  50 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
  51         "FP64Denormals",
  52         "true",
  53         "Enable double precision denormal handling",
  54         [FeatureFP64]>;
  55
  56 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  57         "FastFMAF32",
  58         "true",
  59         "Assuming f32 fma is at least as fast as mul + add",
  60         []>;
  61
  62 // Some instructions do not support denormals despite this flag. Using
  63 // fp32 denormals also causes instructions to run at the double
  64 // precision rate for the device.
  65 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
  66         "FP32Denormals",
  67         "true",
  68         "Enable single precision denormal handling">;
  69
  70 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
  71         "Is64bit",
  72         "true",
  73         "Specify if 64-bit addressing should be used">;
  74
  75 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
  76         "R600ALUInst",
  77         "false",
  78         "Older version of ALU instructions encoding">;
  79
  80 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
  81         "HasVertexCache",
  82         "true",
  83         "Specify use of dedicated vertex cache">;
  84
  85 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
  86         "CaymanISA",
  87         "true",
  88         "Use Cayman ISA">;
  89
  90 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
  91         "CFALUBug",
  92         "true",
  93         "GPU has CF_ALU bug">;
  94
  95 // XXX - This should probably be removed once enabled by default
  96 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
  97         "EnableLoadStoreOpt",
  98         "true",
  99         "Enable SI load/store optimizer pass">;
 100
 101 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
 102         "FlatAddressSpace",
 103         "true",
 104         "Support flat address space">;
 105
 106 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
 107         "EnableVGPRSpilling",
 108         "true",
 109         "Enable spilling of VGPRs to scratch memory">;
 110
 111 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 112         "SGPRInitBug",
 113         "true",
 114         "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
 115
 116 class SubtargetFeatureFetchLimit <string Value> :
 117                           SubtargetFeature <"fetch"#Value,
 118         "TexVTXClauseSize",
 119         Value,
 120         "Limit the maximum number of fetches in a clause to "#Value>;
 121
 122 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
 123 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
 124
 125 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
 126         "wavefrontsize"#Value,
 127         "WavefrontSize",
 128         !cast<string>(Value),
 129         "The number of threads per wavefront">;
 130
 131 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
 132 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
 133 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
 134
 135 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
 136         "localmemorysize"#Value,
 137         "LocalMemorySize",
 138         !cast<string>(Value),
 139         "The size of local memory in bytes">;
 140
 141 def FeatureGCN : SubtargetFeature<"gcn",
 142         "IsGCN",
 143         "true",
 144         "GCN or newer GPU">;
 145
 146 def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
 147         "GCN1Encoding",
 148         "true",
 149         "Encoding format for SI and CI">;
 150
 151 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
 152         "GCN3Encoding",
 153         "true",
 154         "Encoding format for VI">;
 155
 156 def FeatureCIInsts : SubtargetFeature<"ci-insts",
 157         "CIInsts",
 158         "true",
 159         "Additional intstructions for CI+">;
 160
 161 // Dummy feature used to disable assembler instructions.
 162 def FeatureDisable : SubtargetFeature<"",
 163                                       "FeatureDisable","true",
 164                                       "Dummy feature to disable assembler"
 165                                       " instructions">;
 166
 167 class SubtargetFeatureGeneration <string Value,
 168                                   list<SubtargetFeature> Implies> :
 169         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
 170                           Value#" GPU generation", Implies>;
 171
 172 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
 173 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
 174 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
 175
 176 def FeatureR600 : SubtargetFeatureGeneration<"R600",
 177         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
 178
 179 def FeatureR700 : SubtargetFeatureGeneration<"R700",
 180         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
 181
 182 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
 183         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
 184
 185 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
 186         [FeatureFetchLimit16, FeatureWavefrontSize64,
 187          FeatureLocalMemorySize32768]
 188 >;
 189
 190 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 191         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
 192          FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding]>;
 193
 194 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
 195         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 196          FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
 197          FeatureGCN1Encoding, FeatureCIInsts]>;
 198
 199 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 200         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 201          FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
 202          FeatureGCN3Encoding, FeatureCIInsts]>;
 203
 204 //===----------------------------------------------------------------------===//
 205
 206 def AMDGPUInstrInfo : InstrInfo {
 207   let guessInstructionProperties = 1;
 208   let noNamedPositionallyEncodedOperands = 1;
 209 }
 210
 211 def AMDGPUAsmParser : AsmParser {
 212   // Some of the R600 registers have the same name, so this crashes.
 213   // For example T0_XYZW and T0_XY both have the asm name T0.
 214   let ShouldEmitMatchRegisterName = 0;
 215 }
 216
 217 def AMDGPU : Target {
 218   // Pull in Instruction Info:
 219   let InstructionSet = AMDGPUInstrInfo;
 220   let AssemblyParsers = [AMDGPUAsmParser];
 221 }
 222
 223 // Dummy Instruction itineraries for pseudo instructions
 224 def ALU_NULL : FuncUnit;
 225 def NullALU : InstrItinClass;
 226
 227 //===----------------------------------------------------------------------===//
 228 // Predicate helper class
 229 //===----------------------------------------------------------------------===//
 230
 231 def TruePredicate : Predicate<"true">;
 232 def isSICI : Predicate<
 233   "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
 234   "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
 235 >, AssemblerPredicate<"FeatureGCN1Encoding">;
 236
 237 class PredicateControl {
 238   Predicate SubtargetPredicate;
 239   Predicate SIAssemblerPredicate = isSICI;
 240   list<Predicate> AssemblerPredicates = [];
 241   Predicate AssemblerPredicate = TruePredicate;
 242   list<Predicate> OtherPredicates = [];
 243   list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
 244                                             AssemblerPredicates,
 245                                             OtherPredicates);
 246 }
 247
 248 // Include AMDGPU TD files
 249 include "R600Schedule.td"
 250 include "SISchedule.td"
 251 include "Processors.td"
 252 include "AMDGPUInstrInfo.td"
 253 include "AMDGPUIntrinsics.td"
 254 include "AMDGPURegisterInfo.td"
 255 include "AMDGPUInstructions.td"
 256 include "AMDGPUCallingConv.td"