1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// PPC target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "ppctti"
19 #include "PPCTargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/CostTable.h"
23 #include "llvm/Target/TargetLowering.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializePPCTTIPass(PassRegistry &);
35 class PPCTTI final : public ImmutablePass, public TargetTransformInfo {
36 const PPCTargetMachine *TM;
37 const PPCSubtarget *ST;
38 const PPCTargetLowering *TLI;
41 PPCTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
42 llvm_unreachable("This pass cannot be directly constructed");
45 PPCTTI(const PPCTargetMachine *TM)
46 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
47 TLI(TM->getTargetLowering()) {
48 initializePPCTTIPass(*PassRegistry::getPassRegistry());
51 virtual void initializePass() override {
55 virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
56 TargetTransformInfo::getAnalysisUsage(AU);
59 /// Pass identification.
62 /// Provide necessary pointer adjustments for the two base classes.
63 virtual void *getAdjustedAnalysisPointer(const void *ID) override {
64 if (ID == &TargetTransformInfo::ID)
65 return (TargetTransformInfo*)this;
69 /// \name Scalar TTI Implementations
71 virtual PopcntSupportKind
72 getPopcntSupport(unsigned TyWidth) const override;
73 virtual void getUnrollingPreferences(
74 Loop *L, UnrollingPreferences &UP) const override;
78 /// \name Vector TTI Implementations
81 virtual unsigned getNumberOfRegisters(bool Vector) const override;
82 virtual unsigned getRegisterBitWidth(bool Vector) const override;
83 virtual unsigned getMaximumUnrollFactor() const override;
84 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
86 OperandValueKind) const override;
87 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
88 int Index, Type *SubTp) const override;
89 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
90 Type *Src) const override;
91 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
92 Type *CondTy) const override;
93 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
94 unsigned Index) const override;
95 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
97 unsigned AddressSpace) const override;
102 } // end anonymous namespace
104 INITIALIZE_AG_PASS(PPCTTI, TargetTransformInfo, "ppctti",
105 "PPC Target Transform Info", true, true, false)
109 llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) {
110 return new PPCTTI(TM);
114 //===----------------------------------------------------------------------===//
118 //===----------------------------------------------------------------------===//
120 PPCTTI::PopcntSupportKind PPCTTI::getPopcntSupport(unsigned TyWidth) const {
121 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
122 if (ST->hasPOPCNTD() && TyWidth <= 64)
123 return PSK_FastHardware;
127 void PPCTTI::getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const {
128 if (ST->getDarwinDirective() == PPC::DIR_A2) {
129 // The A2 is in-order with a deep pipeline, and concatenation unrolling
130 // helps expose latency-hiding opportunities to the instruction scheduler.
131 UP.Partial = UP.Runtime = true;
135 unsigned PPCTTI::getNumberOfRegisters(bool Vector) const {
136 if (Vector && !ST->hasAltivec())
138 return ST->hasVSX() ? 64 : 32;
141 unsigned PPCTTI::getRegisterBitWidth(bool Vector) const {
143 if (ST->hasAltivec()) return 128;
153 unsigned PPCTTI::getMaximumUnrollFactor() const {
154 unsigned Directive = ST->getDarwinDirective();
155 // The 440 has no SIMD support, but floating-point instructions
156 // have a 5-cycle latency, so unroll by 5x for latency hiding.
157 if (Directive == PPC::DIR_440)
160 // The A2 has no SIMD support, but floating-point instructions
161 // have a 6-cycle latency, so unroll by 6x for latency hiding.
162 if (Directive == PPC::DIR_A2)
165 // FIXME: For lack of any better information, do no harm...
166 if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
169 // For most things, modern systems have two execution units (and
170 // out-of-order execution).
174 unsigned PPCTTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
175 OperandValueKind Op1Info,
176 OperandValueKind Op2Info) const {
177 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
179 // Fallback to the default implementation.
180 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
184 unsigned PPCTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
186 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
189 unsigned PPCTTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
190 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
192 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
195 unsigned PPCTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
196 Type *CondTy) const {
197 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
200 unsigned PPCTTI::getVectorInstrCost(unsigned Opcode, Type *Val,
201 unsigned Index) const {
202 assert(Val->isVectorTy() && "This must be a vector type");
204 int ISD = TLI->InstructionOpcodeToISD(Opcode);
205 assert(ISD && "Invalid opcode");
207 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
208 // Double-precision scalars are already located in index #0.
212 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
215 // Estimated cost of a load-hit-store delay. This was obtained
216 // experimentally as a minimum needed to prevent unprofitable
217 // vectorization for the paq8p benchmark. It may need to be
218 // raised further if other unprofitable cases remain.
219 unsigned LHSPenalty = 2;
220 if (ISD == ISD::INSERT_VECTOR_ELT)
223 // Vector element insert/extract with Altivec is very expensive,
224 // because they require store and reload with the attendant
225 // processor stall for load-hit-store. Until VSX is available,
226 // these need to be estimated as very costly.
227 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
228 ISD == ISD::INSERT_VECTOR_ELT)
230 TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
232 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
235 unsigned PPCTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
236 unsigned AddressSpace) const {
237 // Legalize the type.
238 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
239 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
243 TargetTransformInfo::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
245 // VSX loads/stores support unaligned access.
247 if (LT.second == MVT::v2f64 || LT.second == MVT::v2i64)
251 bool UnalignedAltivec =
253 Src->getPrimitiveSizeInBits() >= LT.second.getSizeInBits() &&
254 LT.second.getSizeInBits() == 128 &&
255 Opcode == Instruction::Load;
257 // PPC in general does not support unaligned loads and stores. They'll need
258 // to be decomposed based on the alignment factor.
259 unsigned SrcBytes = LT.second.getStoreSize();
260 if (SrcBytes && Alignment && Alignment < SrcBytes && !UnalignedAltivec) {
261 Cost += LT.first*(SrcBytes/Alignment-1);
263 // For a vector type, there is also scalarization overhead (only for
264 // stores, loads are expanded using the vector-load + permutation sequence,
265 // which is much less expensive).
266 if (Src->isVectorTy() && Opcode == Instruction::Store)
267 for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
268 Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);