1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
17 #include "PPCFrameLowering.h"
18 #include "PPCISelLowering.h"
19 #include "PPCInstrInfo.h"
20 #include "PPCSelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "PPCGenSubtargetInfo.inc"
30 // GCC #defines PPC on Linux but we use it as our namespace name
37 // -m directive values.
66 class PPCSubtarget : public PPCGenSubtargetInfo {
68 /// TargetTriple - What processor and OS we're targeting.
71 // Calculates type size & alignment
74 /// stackAlignment - The minimum alignment known to hold of the stack frame on
75 /// entry to the function and which must be maintained by every function.
76 unsigned StackAlignment;
78 /// Selected instruction itineraries (one entry per itinerary class.)
79 InstrItineraryData InstrItins;
81 /// Which cpu directive was used.
82 unsigned DarwinDirective;
84 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
97 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
114 bool HasLazyResolverStubs;
117 bool HasInvariantFunctionDescriptors;
125 PPCFrameLowering FrameLowering;
126 PPCInstrInfo InstrInfo;
127 PPCTargetLowering TLInfo;
128 PPCSelectionDAGInfo TSInfo;
131 /// This constructor initializes the data members to match that
132 /// of the specified triple.
134 PPCSubtarget(const std::string &TT, const std::string &CPU,
135 const std::string &FS, const PPCTargetMachine &TM);
137 /// ParseSubtargetFeatures - Parses features string setting specified
138 /// subtarget options. Definition of function is auto generated by tblgen.
139 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
141 /// getStackAlignment - Returns the minimum alignment known to hold of the
142 /// stack frame on entry to the function and which must be maintained by every
143 /// function for this subtarget.
144 unsigned getStackAlignment() const { return StackAlignment; }
146 /// getDarwinDirective - Returns the -m directive specified for the cpu.
148 unsigned getDarwinDirective() const { return DarwinDirective; }
150 /// getInstrItins - Return the instruction itineraries based on subtarget
152 const InstrItineraryData *getInstrItineraryData() const override {
156 const PPCFrameLowering *getFrameLowering() const override {
157 return &FrameLowering;
159 const DataLayout *getDataLayout() const override { return &DL; }
160 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
161 const PPCTargetLowering *getTargetLowering() const override {
164 const PPCSelectionDAGInfo *getSelectionDAGInfo() const override {
167 const PPCRegisterInfo *getRegisterInfo() const override {
168 return &getInstrInfo()->getRegisterInfo();
171 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
172 /// so that we can use initializer lists for subtarget initialization.
173 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
176 void initializeEnvironment();
177 void initSubtargetFeatures(StringRef CPU, StringRef FS);
180 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
182 bool isPPC64() const { return IsPPC64; }
184 /// has64BitSupport - Return true if the selected CPU supports 64-bit
185 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
186 bool has64BitSupport() const { return Has64BitSupport; }
188 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
189 /// registers in 32-bit mode when possible. This can only true if
190 /// has64BitSupport() returns true.
191 bool use64BitRegs() const { return Use64BitRegs; }
193 /// useCRBits - Return true if we should store and manipulate i1 values in
194 /// the individual condition register bits.
195 bool useCRBits() const { return UseCRBits; }
197 /// hasLazyResolverStub - Return true if accesses to the specified global have
198 /// to go through a dyld lazy resolution stub. This means that an extra load
199 /// is required to get the address of the global.
200 bool hasLazyResolverStub(const GlobalValue *GV,
201 const TargetMachine &TM) const;
203 // isLittleEndian - True if generating little-endian code
204 bool isLittleEndian() const { return IsLittleEndian; }
206 // Specific obvious features.
207 bool hasFCPSGN() const { return HasFCPSGN; }
208 bool hasFSQRT() const { return HasFSQRT; }
209 bool hasFRE() const { return HasFRE; }
210 bool hasFRES() const { return HasFRES; }
211 bool hasFRSQRTE() const { return HasFRSQRTE; }
212 bool hasFRSQRTES() const { return HasFRSQRTES; }
213 bool hasRecipPrec() const { return HasRecipPrec; }
214 bool hasSTFIWX() const { return HasSTFIWX; }
215 bool hasLFIWAX() const { return HasLFIWAX; }
216 bool hasFPRND() const { return HasFPRND; }
217 bool hasFPCVT() const { return HasFPCVT; }
218 bool hasAltivec() const { return HasAltivec; }
219 bool hasSPE() const { return HasSPE; }
220 bool hasQPX() const { return HasQPX; }
221 bool hasVSX() const { return HasVSX; }
222 bool hasP8Vector() const { return HasP8Vector; }
223 bool hasMFOCRF() const { return HasMFOCRF; }
224 bool hasISEL() const { return HasISEL; }
225 bool hasPOPCNTD() const { return HasPOPCNTD; }
226 bool hasCMPB() const { return HasCMPB; }
227 bool hasLDBRX() const { return HasLDBRX; }
228 bool isBookE() const { return IsBookE; }
229 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
230 bool isPPC4xx() const { return IsPPC4xx; }
231 bool isPPC6xx() const { return IsPPC6xx; }
232 bool isE500() const { return IsE500; }
233 bool isDeprecatedMFTB() const { return DeprecatedMFTB; }
234 bool isDeprecatedDST() const { return DeprecatedDST; }
235 bool hasICBT() const { return HasICBT; }
236 bool hasInvariantFunctionDescriptors() const {
237 return HasInvariantFunctionDescriptors;
240 const Triple &getTargetTriple() const { return TargetTriple; }
242 /// isDarwin - True if this is any darwin platform.
243 bool isDarwin() const { return TargetTriple.isMacOSX(); }
244 /// isBGQ - True if this is a BG/Q platform.
245 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
247 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
248 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
250 bool isDarwinABI() const { return isDarwin(); }
251 bool isSVR4ABI() const { return !isDarwin(); }
252 bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
254 bool enableEarlyIfConversion() const override { return hasISEL(); }
256 // Scheduling customization.
257 bool enableMachineScheduler() const override;
258 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
259 bool enablePostMachineScheduler() const override;
260 AntiDepBreakMode getAntiDepBreakMode() const override;
261 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
263 void overrideSchedPolicy(MachineSchedPolicy &Policy,
266 unsigned NumRegionInstrs) const override;
267 bool useAA() const override;
269 bool enableSubRegLiveness() const override;
271 } // End llvm namespace