1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetMachine.h"
29 #define DEBUG_TYPE "ppc-subtarget"
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "PPCGenSubtargetInfo.inc"
35 /// Return the datalayout string of a subtarget.
36 static std::string getDataLayoutString(const PPCSubtarget &ST) {
37 const Triple &T = ST.getTargetTriple();
41 // Most PPC* platforms are big endian, PPC64LE is little endian.
42 if (ST.isLittleEndian())
47 Ret += DataLayout::getManglingComponent(T);
49 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
51 if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
54 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
55 // documentation are wrong; these are correct (i.e. "what gcc does").
56 if (ST.isPPC64() || ST.isSVR4ABI())
61 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
70 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
72 initializeEnvironment();
73 resetSubtargetFeatures(CPU, FS);
77 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
78 const std::string &FS, bool is64Bit,
79 CodeGenOpt::Level OptLevel)
80 : PPCGenSubtargetInfo(TT, CPU, FS), IsPPC64(is64Bit), TargetTriple(TT),
82 FrameLowering(initializeSubtargetDependencies(CPU, FS)),
83 DL(getDataLayoutString(*this)), InstrInfo(*this), JITInfo(*this) {}
85 /// SetJITMode - This is called to inform the subtarget info that we are
86 /// producing code for the JIT.
87 void PPCSubtarget::SetJITMode() {
88 // JIT mode doesn't want lazy resolver stubs, it knows exactly where
89 // everything is. This matters for PPC64, which codegens in PIC mode without
91 HasLazyResolverStubs = false;
93 // Calls to external functions need to use indirect calls
94 IsJITCodeModel = true;
97 void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
98 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
99 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
101 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
104 !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
106 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
108 initializeEnvironment();
109 resetSubtargetFeatures(CPU, FS);
113 void PPCSubtarget::initializeEnvironment() {
115 DarwinDirective = PPC::DIR_NONE;
117 Has64BitSupport = false;
118 Use64BitRegs = false;
129 HasRecipPrec = false;
138 DeprecatedMFTB = false;
139 DeprecatedDST = false;
140 HasLazyResolverStubs = false;
141 IsJITCodeModel = false;
144 void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
145 // Determine default and user specified characteristics
146 std::string CPUName = CPU;
149 #if (defined(__APPLE__) || defined(__linux__)) && \
150 (defined(__ppc__) || defined(__powerpc__))
151 if (CPUName == "generic")
152 CPUName = sys::getHostCPUName();
155 // Initialize scheduling itinerary for the specified CPU.
156 InstrItins = getInstrItineraryForCPU(CPUName);
158 // Make sure 64-bit features are available when CPUname is generic
159 std::string FullFS = FS;
161 // If we are generating code for ppc64, verify that options make sense.
163 Has64BitSupport = true;
164 // Silently force 64-bit register use on ppc64.
167 FullFS = "+64bit," + FullFS;
172 // At -O2 and above, track CR bits as individual registers.
173 if (OptLevel >= CodeGenOpt::Default) {
175 FullFS = "+crbits," + FullFS;
180 // Parse features string.
181 ParseSubtargetFeatures(CPUName, FullFS);
183 // If the user requested use of 64-bit regs, but the cpu selected doesn't
184 // support it, ignore.
185 if (use64BitRegs() && !has64BitSupport())
186 Use64BitRegs = false;
188 // Set up darwin-specific properties.
190 HasLazyResolverStubs = true;
192 // QPX requires a 32-byte aligned stack. Note that we need to do this if
193 // we're compiling for a BG/Q system regardless of whether or not QPX
194 // is enabled because external functions will assume this alignment.
195 if (hasQPX() || isBGQ())
198 // Determine endianness.
199 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
201 // FIXME: For now, we disable VSX in little-endian mode until endian
202 // issues in those instructions can be addressed.
207 /// hasLazyResolverStub - Return true if accesses to the specified global have
208 /// to go through a dyld lazy resolution stub. This means that an extra load
209 /// is required to get the address of the global.
210 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
211 const TargetMachine &TM) const {
212 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
213 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
215 // If symbol visibility is hidden, the extra load is not needed if
216 // the symbol is definitely defined in the current translation unit.
217 bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
218 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
220 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
221 GV->hasCommonLinkage() || isDecl;
224 bool PPCSubtarget::enablePostRAScheduler(
225 CodeGenOpt::Level OptLevel,
226 TargetSubtargetInfo::AntiDepBreakMode& Mode,
227 RegClassVector& CriticalPathRCs) const {
228 Mode = TargetSubtargetInfo::ANTIDEP_ALL;
230 CriticalPathRCs.clear();
233 CriticalPathRCs.push_back(&PPC::G8RCRegClass);
235 CriticalPathRCs.push_back(&PPC::GPRCRegClass);
237 return OptLevel >= CodeGenOpt::Default;
240 // Embedded cores need aggressive scheduling (and some others also benefit).
241 static bool needsAggressiveScheduling(unsigned Directive) {
243 default: return false;
246 case PPC::DIR_E500mc:
253 bool PPCSubtarget::enableMachineScheduler() const {
254 // Enable MI scheduling for the embedded cores.
255 // FIXME: Enable this for all cores (some additional modeling
256 // may be necessary).
257 return needsAggressiveScheduling(DarwinDirective);
260 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
263 unsigned NumRegionInstrs) const {
264 if (needsAggressiveScheduling(DarwinDirective)) {
265 Policy.OnlyTopDown = false;
266 Policy.OnlyBottomUp = false;
269 // Spilling is generally expensive on all PPC cores, so always enable
270 // register-pressure tracking.
271 Policy.ShouldTrackPressure = true;
274 bool PPCSubtarget::useAA() const {
275 // Use AA during code generation for the embedded cores.
276 return needsAggressiveScheduling(DarwinDirective);