1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/CodeGen/ScheduleDAG.h"
31 #include "llvm/CodeGen/SlotIndexes.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Support/raw_ostream.h"
43 #define DEBUG_TYPE "ppc-instr-info"
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
50 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
51 cl::desc("Disable analysis for CTR loops"));
53 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
54 cl::desc("Disable compare instruction optimization"), cl::Hidden);
56 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
57 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
61 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
62 cl::desc("Use the old (incorrect) instruction latency calculation"));
64 // Pin the vtable to this file.
65 void PPCInstrInfo::anchor() {}
67 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
68 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
69 Subtarget(STI), RI(STI.getTargetMachine()) {}
71 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
72 /// this target when scheduling the DAG.
73 ScheduleHazardRecognizer *
74 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
75 const ScheduleDAG *DAG) const {
77 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
78 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
79 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
80 const InstrItineraryData *II =
81 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
82 return new ScoreboardHazardRecognizer(II, DAG);
85 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
88 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
89 /// to use for this target when scheduling the DAG.
90 ScheduleHazardRecognizer *
91 PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
92 const ScheduleDAG *DAG) const {
94 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
96 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
97 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
99 // Most subtargets use a PPC970 recognizer.
100 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
101 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
102 assert(DAG->TII && "No InstrInfo?");
104 return new PPCHazardRecognizer970(*DAG);
107 return new ScoreboardHazardRecognizer(II, DAG);
110 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
111 const MachineInstr *MI,
112 unsigned *PredCost) const {
113 if (!ItinData || UseOldLatencyCalc)
114 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
116 // The default implementation of getInstrLatency calls getStageLatency, but
117 // getStageLatency does not do the right thing for us. While we have
118 // itinerary, most cores are fully pipelined, and so the itineraries only
119 // express the first part of the pipeline, not every stage. Instead, we need
120 // to use the listed output operand cycle number (using operand 0 here, which
123 unsigned Latency = 1;
124 unsigned DefClass = MI->getDesc().getSchedClass();
125 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
126 const MachineOperand &MO = MI->getOperand(i);
127 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
130 int Cycle = ItinData->getOperandCycle(DefClass, i);
134 Latency = std::max(Latency, (unsigned) Cycle);
140 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
141 const MachineInstr *DefMI, unsigned DefIdx,
142 const MachineInstr *UseMI,
143 unsigned UseIdx) const {
144 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
147 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
148 unsigned Reg = DefMO.getReg();
151 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
152 const MachineRegisterInfo *MRI =
153 &DefMI->getParent()->getParent()->getRegInfo();
154 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
155 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
157 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
158 PPC::CRBITRCRegClass.contains(Reg);
161 if (UseMI->isBranch() && IsRegCR) {
163 Latency = getInstrLatency(ItinData, DefMI);
165 // On some cores, there is an additional delay between writing to a condition
166 // register, and using it from a branch.
167 unsigned Directive = Subtarget.getDarwinDirective();
189 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
190 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
191 unsigned &SrcReg, unsigned &DstReg,
192 unsigned &SubIdx) const {
193 switch (MI.getOpcode()) {
194 default: return false;
196 case PPC::EXTSW_32_64:
197 SrcReg = MI.getOperand(1).getReg();
198 DstReg = MI.getOperand(0).getReg();
199 SubIdx = PPC::sub_32;
204 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
205 int &FrameIndex) const {
206 // Note: This list must be kept consistent with LoadRegFromStackSlot.
207 switch (MI->getOpcode()) {
213 case PPC::RESTORE_CR:
214 case PPC::RESTORE_CRBIT:
220 case PPC::RESTORE_VRSAVE:
221 // Check for the operands added by addFrameReference (the immediate is the
222 // offset which defaults to 0).
223 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
224 MI->getOperand(2).isFI()) {
225 FrameIndex = MI->getOperand(2).getIndex();
226 return MI->getOperand(0).getReg();
233 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
234 int &FrameIndex) const {
235 // Note: This list must be kept consistent with StoreRegToStackSlot.
236 switch (MI->getOpcode()) {
243 case PPC::SPILL_CRBIT:
249 case PPC::SPILL_VRSAVE:
250 // Check for the operands added by addFrameReference (the immediate is the
251 // offset which defaults to 0).
252 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
253 MI->getOperand(2).isFI()) {
254 FrameIndex = MI->getOperand(2).getIndex();
255 return MI->getOperand(0).getReg();
262 // commuteInstruction - We can commute rlwimi instructions, but only if the
263 // rotate amt is zero. We also have to munge the immediates a bit.
265 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
266 MachineFunction &MF = *MI->getParent()->getParent();
268 // Normal instructions can be commuted the obvious way.
269 if (MI->getOpcode() != PPC::RLWIMI &&
270 MI->getOpcode() != PPC::RLWIMIo)
271 return TargetInstrInfo::commuteInstruction(MI, NewMI);
272 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
273 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
274 // changing the relative order of the mask operands might change what happens
275 // to the high-bits of the mask (and, thus, the result).
277 // Cannot commute if it has a non-zero rotate count.
278 if (MI->getOperand(3).getImm() != 0)
281 // If we have a zero rotate count, we have:
283 // Op0 = (Op1 & ~M) | (Op2 & M)
285 // M = mask((ME+1)&31, (MB-1)&31)
286 // Op0 = (Op2 & ~M) | (Op1 & M)
289 unsigned Reg0 = MI->getOperand(0).getReg();
290 unsigned Reg1 = MI->getOperand(1).getReg();
291 unsigned Reg2 = MI->getOperand(2).getReg();
292 unsigned SubReg1 = MI->getOperand(1).getSubReg();
293 unsigned SubReg2 = MI->getOperand(2).getSubReg();
294 bool Reg1IsKill = MI->getOperand(1).isKill();
295 bool Reg2IsKill = MI->getOperand(2).isKill();
296 bool ChangeReg0 = false;
297 // If machine instrs are no longer in two-address forms, update
298 // destination register as well.
300 // Must be two address instruction!
301 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
302 "Expecting a two-address instruction!");
303 assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
309 unsigned MB = MI->getOperand(4).getImm();
310 unsigned ME = MI->getOperand(5).getImm();
313 // Create a new instruction.
314 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
315 bool Reg0IsDead = MI->getOperand(0).isDead();
316 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
317 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
318 .addReg(Reg2, getKillRegState(Reg2IsKill))
319 .addReg(Reg1, getKillRegState(Reg1IsKill))
321 .addImm((MB-1) & 31);
325 MI->getOperand(0).setReg(Reg2);
326 MI->getOperand(0).setSubReg(SubReg2);
328 MI->getOperand(2).setReg(Reg1);
329 MI->getOperand(1).setReg(Reg2);
330 MI->getOperand(2).setSubReg(SubReg1);
331 MI->getOperand(1).setSubReg(SubReg2);
332 MI->getOperand(2).setIsKill(Reg1IsKill);
333 MI->getOperand(1).setIsKill(Reg2IsKill);
335 // Swap the mask around.
336 MI->getOperand(4).setImm((ME+1) & 31);
337 MI->getOperand(5).setImm((MB-1) & 31);
341 bool PPCInstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
342 unsigned &SrcOpIdx2) const {
343 // For VSX A-Type FMA instructions, it is the first two operands that can be
344 // commuted, however, because the non-encoded tied input operand is listed
345 // first, the operands to swap are actually the second and third.
347 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
349 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
356 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
357 MachineBasicBlock::iterator MI) const {
358 // This function is used for scheduling, and the nop wanted here is the type
359 // that terminates dispatch groups on the POWER cores.
360 unsigned Directive = Subtarget.getDarwinDirective();
363 default: Opcode = PPC::NOP; break;
364 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
365 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
366 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
370 BuildMI(MBB, MI, DL, get(Opcode));
373 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
374 void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
375 NopInst.setOpcode(PPC::NOP);
379 // Note: If the condition register is set to CTR or CTR8 then this is a
380 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
381 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
382 MachineBasicBlock *&FBB,
383 SmallVectorImpl<MachineOperand> &Cond,
384 bool AllowModify) const {
385 bool isPPC64 = Subtarget.isPPC64();
387 // If the block has no terminators, it just falls into the block after it.
388 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
392 if (!isUnpredicatedTerminator(I))
395 // Get the last instruction in the block.
396 MachineInstr *LastInst = I;
398 // If there is only one terminator instruction, process it.
399 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
400 if (LastInst->getOpcode() == PPC::B) {
401 if (!LastInst->getOperand(0).isMBB())
403 TBB = LastInst->getOperand(0).getMBB();
405 } else if (LastInst->getOpcode() == PPC::BCC) {
406 if (!LastInst->getOperand(2).isMBB())
408 // Block ends with fall-through condbranch.
409 TBB = LastInst->getOperand(2).getMBB();
410 Cond.push_back(LastInst->getOperand(0));
411 Cond.push_back(LastInst->getOperand(1));
413 } else if (LastInst->getOpcode() == PPC::BC) {
414 if (!LastInst->getOperand(1).isMBB())
416 // Block ends with fall-through condbranch.
417 TBB = LastInst->getOperand(1).getMBB();
418 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
419 Cond.push_back(LastInst->getOperand(0));
421 } else if (LastInst->getOpcode() == PPC::BCn) {
422 if (!LastInst->getOperand(1).isMBB())
424 // Block ends with fall-through condbranch.
425 TBB = LastInst->getOperand(1).getMBB();
426 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
427 Cond.push_back(LastInst->getOperand(0));
429 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
430 LastInst->getOpcode() == PPC::BDNZ) {
431 if (!LastInst->getOperand(0).isMBB())
433 if (DisableCTRLoopAnal)
435 TBB = LastInst->getOperand(0).getMBB();
436 Cond.push_back(MachineOperand::CreateImm(1));
437 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
440 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
441 LastInst->getOpcode() == PPC::BDZ) {
442 if (!LastInst->getOperand(0).isMBB())
444 if (DisableCTRLoopAnal)
446 TBB = LastInst->getOperand(0).getMBB();
447 Cond.push_back(MachineOperand::CreateImm(0));
448 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
453 // Otherwise, don't know what this is.
457 // Get the instruction before it if it's a terminator.
458 MachineInstr *SecondLastInst = I;
460 // If there are three terminators, we don't know what sort of block this is.
461 if (SecondLastInst && I != MBB.begin() &&
462 isUnpredicatedTerminator(--I))
465 // If the block ends with PPC::B and PPC:BCC, handle it.
466 if (SecondLastInst->getOpcode() == PPC::BCC &&
467 LastInst->getOpcode() == PPC::B) {
468 if (!SecondLastInst->getOperand(2).isMBB() ||
469 !LastInst->getOperand(0).isMBB())
471 TBB = SecondLastInst->getOperand(2).getMBB();
472 Cond.push_back(SecondLastInst->getOperand(0));
473 Cond.push_back(SecondLastInst->getOperand(1));
474 FBB = LastInst->getOperand(0).getMBB();
476 } else if (SecondLastInst->getOpcode() == PPC::BC &&
477 LastInst->getOpcode() == PPC::B) {
478 if (!SecondLastInst->getOperand(1).isMBB() ||
479 !LastInst->getOperand(0).isMBB())
481 TBB = SecondLastInst->getOperand(1).getMBB();
482 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
483 Cond.push_back(SecondLastInst->getOperand(0));
484 FBB = LastInst->getOperand(0).getMBB();
486 } else if (SecondLastInst->getOpcode() == PPC::BCn &&
487 LastInst->getOpcode() == PPC::B) {
488 if (!SecondLastInst->getOperand(1).isMBB() ||
489 !LastInst->getOperand(0).isMBB())
491 TBB = SecondLastInst->getOperand(1).getMBB();
492 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
493 Cond.push_back(SecondLastInst->getOperand(0));
494 FBB = LastInst->getOperand(0).getMBB();
496 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
497 SecondLastInst->getOpcode() == PPC::BDNZ) &&
498 LastInst->getOpcode() == PPC::B) {
499 if (!SecondLastInst->getOperand(0).isMBB() ||
500 !LastInst->getOperand(0).isMBB())
502 if (DisableCTRLoopAnal)
504 TBB = SecondLastInst->getOperand(0).getMBB();
505 Cond.push_back(MachineOperand::CreateImm(1));
506 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
508 FBB = LastInst->getOperand(0).getMBB();
510 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
511 SecondLastInst->getOpcode() == PPC::BDZ) &&
512 LastInst->getOpcode() == PPC::B) {
513 if (!SecondLastInst->getOperand(0).isMBB() ||
514 !LastInst->getOperand(0).isMBB())
516 if (DisableCTRLoopAnal)
518 TBB = SecondLastInst->getOperand(0).getMBB();
519 Cond.push_back(MachineOperand::CreateImm(0));
520 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
522 FBB = LastInst->getOperand(0).getMBB();
526 // If the block ends with two PPC:Bs, handle it. The second one is not
527 // executed, so remove it.
528 if (SecondLastInst->getOpcode() == PPC::B &&
529 LastInst->getOpcode() == PPC::B) {
530 if (!SecondLastInst->getOperand(0).isMBB())
532 TBB = SecondLastInst->getOperand(0).getMBB();
535 I->eraseFromParent();
539 // Otherwise, can't handle this.
543 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
544 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
548 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
549 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
550 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
551 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
554 // Remove the branch.
555 I->eraseFromParent();
559 if (I == MBB.begin()) return 1;
561 if (I->getOpcode() != PPC::BCC &&
562 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
563 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
564 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
567 // Remove the branch.
568 I->eraseFromParent();
573 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
574 MachineBasicBlock *FBB,
575 ArrayRef<MachineOperand> Cond,
577 // Shouldn't be a fall through.
578 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
579 assert((Cond.size() == 2 || Cond.size() == 0) &&
580 "PPC branch conditions have two components!");
582 bool isPPC64 = Subtarget.isPPC64();
586 if (Cond.empty()) // Unconditional branch
587 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
588 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
589 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
590 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
591 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
592 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
593 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
594 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
595 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
596 else // Conditional branch
597 BuildMI(&MBB, DL, get(PPC::BCC))
598 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
602 // Two-way Conditional Branch.
603 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
604 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
605 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
606 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
607 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
608 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
609 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
610 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
612 BuildMI(&MBB, DL, get(PPC::BCC))
613 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
614 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
619 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
620 ArrayRef<MachineOperand> Cond,
621 unsigned TrueReg, unsigned FalseReg,
622 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
623 if (!Subtarget.hasISEL())
626 if (Cond.size() != 2)
629 // If this is really a bdnz-like condition, then it cannot be turned into a
631 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
634 // Check register classes.
635 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
636 const TargetRegisterClass *RC =
637 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
641 // isel is for regular integer GPRs only.
642 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
643 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
644 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
645 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
648 // FIXME: These numbers are for the A2, how well they work for other cores is
649 // an open question. On the A2, the isel instruction has a 2-cycle latency
650 // but single-cycle throughput. These numbers are used in combination with
651 // the MispredictPenalty setting from the active SchedMachineModel.
659 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
660 MachineBasicBlock::iterator MI, DebugLoc dl,
661 unsigned DestReg, ArrayRef<MachineOperand> Cond,
662 unsigned TrueReg, unsigned FalseReg) const {
663 assert(Cond.size() == 2 &&
664 "PPC branch conditions have two components!");
666 assert(Subtarget.hasISEL() &&
667 "Cannot insert select on target without ISEL support");
669 // Get the register classes.
670 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
671 const TargetRegisterClass *RC =
672 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
673 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
675 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
676 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
678 PPC::GPRCRegClass.hasSubClassEq(RC) ||
679 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
680 "isel is for regular integer GPRs only");
682 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
683 unsigned SelectPred = Cond[0].getImm();
687 switch (SelectPred) {
688 default: llvm_unreachable("invalid predicate for isel");
689 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
690 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
691 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
692 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
693 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
694 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
695 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
696 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
697 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
698 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
701 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
702 SecondReg = SwapOps ? TrueReg : FalseReg;
704 // The first input register of isel cannot be r0. If it is a member
705 // of a register class that can be r0, then copy it first (the
706 // register allocator should eliminate the copy).
707 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
708 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
709 const TargetRegisterClass *FirstRC =
710 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
711 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
712 unsigned OldFirstReg = FirstReg;
713 FirstReg = MRI.createVirtualRegister(FirstRC);
714 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
715 .addReg(OldFirstReg);
718 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
719 .addReg(FirstReg).addReg(SecondReg)
720 .addReg(Cond[1].getReg(), 0, SubIdx);
723 static unsigned getCRBitValue(unsigned CRBit) {
725 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
726 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
727 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
728 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
730 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
731 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
732 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
733 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
735 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
736 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
737 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
738 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
740 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
741 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
742 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
743 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
746 assert(Ret != 4 && "Invalid CR bit register");
750 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
751 MachineBasicBlock::iterator I, DebugLoc DL,
752 unsigned DestReg, unsigned SrcReg,
753 bool KillSrc) const {
754 // We can end up with self copies and similar things as a result of VSX copy
755 // legalization. Promote them here.
756 const TargetRegisterInfo *TRI = &getRegisterInfo();
757 if (PPC::F8RCRegClass.contains(DestReg) &&
758 PPC::VSRCRegClass.contains(SrcReg)) {
760 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
762 if (VSXSelfCopyCrash && SrcReg == SuperReg)
763 llvm_unreachable("nop VSX copy");
766 } else if (PPC::VRRCRegClass.contains(DestReg) &&
767 PPC::VSRCRegClass.contains(SrcReg)) {
769 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
771 if (VSXSelfCopyCrash && SrcReg == SuperReg)
772 llvm_unreachable("nop VSX copy");
775 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
776 PPC::VSRCRegClass.contains(DestReg)) {
778 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
780 if (VSXSelfCopyCrash && DestReg == SuperReg)
781 llvm_unreachable("nop VSX copy");
784 } else if (PPC::VRRCRegClass.contains(SrcReg) &&
785 PPC::VSRCRegClass.contains(DestReg)) {
787 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
789 if (VSXSelfCopyCrash && DestReg == SuperReg)
790 llvm_unreachable("nop VSX copy");
795 // Different class register copy
796 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
797 PPC::GPRCRegClass.contains(DestReg)) {
798 unsigned CRReg = getCRFromCRBit(SrcReg);
799 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
800 .addReg(CRReg), getKillRegState(KillSrc);
801 // Rotate the CR bit in the CR fields to be the least significant bit and
802 // then mask with 0x1 (MB = ME = 31).
803 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
804 .addReg(DestReg, RegState::Kill)
805 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
809 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
810 PPC::G8RCRegClass.contains(DestReg)) {
811 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg)
812 .addReg(SrcReg), getKillRegState(KillSrc);
814 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
815 PPC::GPRCRegClass.contains(DestReg)) {
816 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
817 .addReg(SrcReg), getKillRegState(KillSrc);
822 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
824 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
826 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
828 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
830 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
832 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
833 // There are two different ways this can be done:
834 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
835 // issue in VSU pipeline 0.
836 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
837 // can go to either pipeline.
838 // We'll always use xxlor here, because in practically all cases where
839 // copies are generated, they are close enough to some use that the
840 // lower-latency form is preferable.
842 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
843 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
845 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
847 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
849 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
851 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
854 llvm_unreachable("Impossible reg-to-reg copy");
856 const MCInstrDesc &MCID = get(Opc);
857 if (MCID.getNumOperands() == 3)
858 BuildMI(MBB, I, DL, MCID, DestReg)
859 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
861 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
864 // This function returns true if a CR spill is necessary and false otherwise.
866 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
867 unsigned SrcReg, bool isKill,
869 const TargetRegisterClass *RC,
870 SmallVectorImpl<MachineInstr*> &NewMIs,
871 bool &NonRI, bool &SpillsVRS) const{
872 // Note: If additional store instructions are added here,
873 // update isStoreToStackSlot.
876 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
877 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
878 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
880 getKillRegState(isKill)),
882 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
883 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
884 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
886 getKillRegState(isKill)),
888 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
889 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
891 getKillRegState(isKill)),
893 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
894 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
896 getKillRegState(isKill)),
898 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
899 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
901 getKillRegState(isKill)),
904 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
905 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
907 getKillRegState(isKill)),
910 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
911 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
913 getKillRegState(isKill)),
916 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
917 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
919 getKillRegState(isKill)),
922 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
923 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX))
925 getKillRegState(isKill)),
928 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
929 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX))
931 getKillRegState(isKill)),
934 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
935 assert(Subtarget.isDarwin() &&
936 "VRSAVE only needs spill/restore on Darwin");
937 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
939 getKillRegState(isKill)),
942 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
943 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
945 getKillRegState(isKill)),
948 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
949 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
951 getKillRegState(isKill)),
954 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
955 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
957 getKillRegState(isKill)),
961 llvm_unreachable("Unknown regclass!");
968 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
969 MachineBasicBlock::iterator MI,
970 unsigned SrcReg, bool isKill, int FrameIdx,
971 const TargetRegisterClass *RC,
972 const TargetRegisterInfo *TRI) const {
973 MachineFunction &MF = *MBB.getParent();
974 SmallVector<MachineInstr*, 4> NewMIs;
976 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
977 FuncInfo->setHasSpills();
979 bool NonRI = false, SpillsVRS = false;
980 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
982 FuncInfo->setSpillsCR();
985 FuncInfo->setSpillsVRSAVE();
988 FuncInfo->setHasNonRISpills();
990 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
991 MBB.insert(MI, NewMIs[i]);
993 const MachineFrameInfo &MFI = *MF.getFrameInfo();
994 MachineMemOperand *MMO =
995 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
996 MachineMemOperand::MOStore,
997 MFI.getObjectSize(FrameIdx),
998 MFI.getObjectAlignment(FrameIdx));
999 NewMIs.back()->addMemOperand(MF, MMO);
1003 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
1004 unsigned DestReg, int FrameIdx,
1005 const TargetRegisterClass *RC,
1006 SmallVectorImpl<MachineInstr*> &NewMIs,
1007 bool &NonRI, bool &SpillsVRS) const{
1008 // Note: If additional load instructions are added here,
1009 // update isLoadFromStackSlot.
1011 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1012 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1013 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1014 DestReg), FrameIdx));
1015 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1016 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1017 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1019 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1020 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1022 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1023 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1025 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1026 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1027 get(PPC::RESTORE_CR), DestReg),
1030 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1031 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1032 get(PPC::RESTORE_CRBIT), DestReg),
1035 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1036 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1039 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1040 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg),
1043 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1044 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg),
1047 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1048 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg),
1051 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1052 assert(Subtarget.isDarwin() &&
1053 "VRSAVE only needs spill/restore on Darwin");
1054 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1055 get(PPC::RESTORE_VRSAVE),
1059 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1060 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1063 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1064 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1067 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1068 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1072 llvm_unreachable("Unknown regclass!");
1079 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1080 MachineBasicBlock::iterator MI,
1081 unsigned DestReg, int FrameIdx,
1082 const TargetRegisterClass *RC,
1083 const TargetRegisterInfo *TRI) const {
1084 MachineFunction &MF = *MBB.getParent();
1085 SmallVector<MachineInstr*, 4> NewMIs;
1087 if (MI != MBB.end()) DL = MI->getDebugLoc();
1089 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1090 FuncInfo->setHasSpills();
1092 bool NonRI = false, SpillsVRS = false;
1093 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1095 FuncInfo->setSpillsCR();
1098 FuncInfo->setSpillsVRSAVE();
1101 FuncInfo->setHasNonRISpills();
1103 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1104 MBB.insert(MI, NewMIs[i]);
1106 const MachineFrameInfo &MFI = *MF.getFrameInfo();
1107 MachineMemOperand *MMO =
1108 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
1109 MachineMemOperand::MOLoad,
1110 MFI.getObjectSize(FrameIdx),
1111 MFI.getObjectAlignment(FrameIdx));
1112 NewMIs.back()->addMemOperand(MF, MMO);
1116 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1117 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1118 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1119 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1121 // Leave the CR# the same, but invert the condition.
1122 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1126 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1127 unsigned Reg, MachineRegisterInfo *MRI) const {
1128 // For some instructions, it is legal to fold ZERO into the RA register field.
1129 // A zero immediate should always be loaded with a single li.
1130 unsigned DefOpc = DefMI->getOpcode();
1131 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1133 if (!DefMI->getOperand(1).isImm())
1135 if (DefMI->getOperand(1).getImm() != 0)
1138 // Note that we cannot here invert the arguments of an isel in order to fold
1139 // a ZERO into what is presented as the second argument. All we have here
1140 // is the condition bit, and that might come from a CR-logical bit operation.
1142 const MCInstrDesc &UseMCID = UseMI->getDesc();
1144 // Only fold into real machine instructions.
1145 if (UseMCID.isPseudo())
1149 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
1150 if (UseMI->getOperand(UseIdx).isReg() &&
1151 UseMI->getOperand(UseIdx).getReg() == Reg)
1154 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
1155 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1157 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1159 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1160 // register (which might also be specified as a pointer class kind).
1161 if (UseInfo->isLookupPtrRegClass()) {
1162 if (UseInfo->RegClass /* Kind */ != 1)
1165 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1166 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1170 // Make sure this is not tied to an output register (or otherwise
1171 // constrained). This is true for ST?UX registers, for example, which
1172 // are tied to their output registers.
1173 if (UseInfo->Constraints != 0)
1177 if (UseInfo->isLookupPtrRegClass()) {
1178 bool isPPC64 = Subtarget.isPPC64();
1179 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1181 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1182 PPC::ZERO8 : PPC::ZERO;
1185 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1186 UseMI->getOperand(UseIdx).setReg(ZeroReg);
1189 DefMI->eraseFromParent();
1194 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1195 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1197 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1202 // We should make sure that, if we're going to predicate both sides of a
1203 // condition (a diamond), that both sides don't define the counter register. We
1204 // can predicate counter-decrement-based branches, but while that predicates
1205 // the branching, it does not predicate the counter decrement. If we tried to
1206 // merge the triangle into one predicated block, we'd decrement the counter
1208 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1209 unsigned NumT, unsigned ExtraT,
1210 MachineBasicBlock &FMBB,
1211 unsigned NumF, unsigned ExtraF,
1212 const BranchProbability &Probability) const {
1213 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1217 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
1218 // The predicated branches are identified by their type, not really by the
1219 // explicit presence of a predicate. Furthermore, some of them can be
1220 // predicated more than once. Because if conversion won't try to predicate
1221 // any instruction which already claims to be predicated (by returning true
1222 // here), always return false. In doing so, we let isPredicable() be the
1223 // final word on whether not the instruction can be (further) predicated.
1228 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1229 if (!MI->isTerminator())
1232 // Conditional branch is a special case.
1233 if (MI->isBranch() && !MI->isBarrier())
1236 return !isPredicated(MI);
1239 bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
1240 ArrayRef<MachineOperand> Pred) const {
1241 unsigned OpC = MI->getOpcode();
1242 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1243 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1244 bool isPPC64 = Subtarget.isPPC64();
1245 MI->setDesc(get(Pred[0].getImm() ?
1246 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1247 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1248 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1249 MI->setDesc(get(PPC::BCLR));
1250 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1251 .addReg(Pred[1].getReg());
1252 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1253 MI->setDesc(get(PPC::BCLRn));
1254 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1255 .addReg(Pred[1].getReg());
1257 MI->setDesc(get(PPC::BCCLR));
1258 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1259 .addImm(Pred[0].getImm())
1260 .addReg(Pred[1].getReg());
1264 } else if (OpC == PPC::B) {
1265 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1266 bool isPPC64 = Subtarget.isPPC64();
1267 MI->setDesc(get(Pred[0].getImm() ?
1268 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1269 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1270 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1271 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1272 MI->RemoveOperand(0);
1274 MI->setDesc(get(PPC::BC));
1275 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1276 .addReg(Pred[1].getReg())
1278 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1279 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1280 MI->RemoveOperand(0);
1282 MI->setDesc(get(PPC::BCn));
1283 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1284 .addReg(Pred[1].getReg())
1287 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1288 MI->RemoveOperand(0);
1290 MI->setDesc(get(PPC::BCC));
1291 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1292 .addImm(Pred[0].getImm())
1293 .addReg(Pred[1].getReg())
1298 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1299 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1300 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1301 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1303 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1304 bool isPPC64 = Subtarget.isPPC64();
1306 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1307 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1308 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1309 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1310 .addReg(Pred[1].getReg());
1312 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1313 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1314 (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1315 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1316 .addReg(Pred[1].getReg());
1320 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1321 (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1322 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1323 .addImm(Pred[0].getImm())
1324 .addReg(Pred[1].getReg());
1331 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1332 ArrayRef<MachineOperand> Pred2) const {
1333 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1334 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1336 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1338 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1341 // P1 can only subsume P2 if they test the same condition register.
1342 if (Pred1[1].getReg() != Pred2[1].getReg())
1345 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1346 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1351 // Does P1 subsume P2, e.g. GE subsumes GT.
1352 if (P1 == PPC::PRED_LE &&
1353 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1355 if (P1 == PPC::PRED_GE &&
1356 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1362 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1363 std::vector<MachineOperand> &Pred) const {
1364 // Note: At the present time, the contents of Pred from this function is
1365 // unused by IfConversion. This implementation follows ARM by pushing the
1366 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1367 // predicate, instructions defining CTR or CTR8 are also included as
1368 // predicate-defining instructions.
1370 const TargetRegisterClass *RCs[] =
1371 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1372 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1375 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1376 const MachineOperand &MO = MI->getOperand(i);
1377 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1378 const TargetRegisterClass *RC = RCs[c];
1380 if (MO.isDef() && RC->contains(MO.getReg())) {
1384 } else if (MO.isRegMask()) {
1385 for (TargetRegisterClass::iterator I = RC->begin(),
1386 IE = RC->end(); I != IE; ++I)
1387 if (MO.clobbersPhysReg(*I)) {
1398 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1399 unsigned OpC = MI->getOpcode();
1414 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1415 unsigned &SrcReg, unsigned &SrcReg2,
1416 int &Mask, int &Value) const {
1417 unsigned Opc = MI->getOpcode();
1420 default: return false;
1425 SrcReg = MI->getOperand(1).getReg();
1427 Value = MI->getOperand(2).getImm();
1436 SrcReg = MI->getOperand(1).getReg();
1437 SrcReg2 = MI->getOperand(2).getReg();
1442 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
1443 unsigned SrcReg, unsigned SrcReg2,
1444 int Mask, int Value,
1445 const MachineRegisterInfo *MRI) const {
1449 int OpC = CmpInstr->getOpcode();
1450 unsigned CRReg = CmpInstr->getOperand(0).getReg();
1452 // FP record forms set CR1 based on the execption status bits, not a
1453 // comparison with zero.
1454 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1457 // The record forms set the condition register based on a signed comparison
1458 // with zero (so says the ISA manual). This is not as straightforward as it
1459 // seems, however, because this is always a 64-bit comparison on PPC64, even
1460 // for instructions that are 32-bit in nature (like slw for example).
1461 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1462 // for equality checks (as those don't depend on the sign). On PPC64,
1463 // we are restricted to equality for unsigned 64-bit comparisons and for
1464 // signed 32-bit comparisons the applicability is more restricted.
1465 bool isPPC64 = Subtarget.isPPC64();
1466 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1467 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1468 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1470 // Get the unique definition of SrcReg.
1471 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1472 if (!MI) return false;
1473 int MIOpC = MI->getOpcode();
1475 bool equalityOnly = false;
1478 if (is32BitSignedCompare) {
1479 // We can perform this optimization only if MI is sign-extending.
1480 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1481 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1482 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1483 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1484 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1488 } else if (is32BitUnsignedCompare) {
1489 // We can perform this optimization, equality only, if MI is
1491 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1492 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1493 MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1495 equalityOnly = true;
1499 equalityOnly = is64BitUnsignedCompare;
1501 equalityOnly = is32BitUnsignedCompare;
1504 // We need to check the uses of the condition register in order to reject
1505 // non-equality comparisons.
1506 for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg),
1507 IE = MRI->use_instr_end(); I != IE; ++I) {
1508 MachineInstr *UseMI = &*I;
1509 if (UseMI->getOpcode() == PPC::BCC) {
1510 unsigned Pred = UseMI->getOperand(0).getImm();
1511 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1513 } else if (UseMI->getOpcode() == PPC::ISEL ||
1514 UseMI->getOpcode() == PPC::ISEL8) {
1515 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1516 if (SubIdx != PPC::sub_eq)
1523 MachineBasicBlock::iterator I = CmpInstr;
1525 // Scan forward to find the first use of the compare.
1526 for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1528 bool FoundUse = false;
1529 for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg),
1530 JE = MRI->use_instr_end(); J != JE; ++J)
1540 // There are two possible candidates which can be changed to set CR[01].
1541 // One is MI, the other is a SUB instruction.
1542 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1543 MachineInstr *Sub = nullptr;
1545 // MI is not a candidate for CMPrr.
1547 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1548 // same BB as the comparison. This is to allow the check below to avoid calls
1549 // (and other explicit clobbers); instead we should really check for these
1550 // more explicitly (in at least a few predecessors).
1551 else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1552 // PPC does not have a record-form SUBri.
1557 const TargetRegisterInfo *TRI = &getRegisterInfo();
1560 // Get ready to iterate backward from CmpInstr.
1561 MachineBasicBlock::iterator E = MI,
1562 B = CmpInstr->getParent()->begin();
1564 for (; I != E && !noSub; --I) {
1565 const MachineInstr &Instr = *I;
1566 unsigned IOpC = Instr.getOpcode();
1568 if (&*I != CmpInstr && (
1569 Instr.modifiesRegister(PPC::CR0, TRI) ||
1570 Instr.readsRegister(PPC::CR0, TRI)))
1571 // This instruction modifies or uses the record condition register after
1572 // the one we want to change. While we could do this transformation, it
1573 // would likely not be profitable. This transformation removes one
1574 // instruction, and so even forcing RA to generate one move probably
1575 // makes it unprofitable.
1578 // Check whether CmpInstr can be made redundant by the current instruction.
1579 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1580 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1581 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1582 ((Instr.getOperand(1).getReg() == SrcReg &&
1583 Instr.getOperand(2).getReg() == SrcReg2) ||
1584 (Instr.getOperand(1).getReg() == SrcReg2 &&
1585 Instr.getOperand(2).getReg() == SrcReg))) {
1591 // The 'and' is below the comparison instruction.
1595 // Return false if no candidates exist.
1599 // The single candidate is called MI.
1603 MIOpC = MI->getOpcode();
1604 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1607 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1608 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1612 // FIXME: On the non-embedded POWER architectures, only some of the record
1613 // forms are fast, and we should use only the fast ones.
1615 // The defining instruction has a record form (or is already a record
1616 // form). It is possible, however, that we'll need to reverse the condition
1617 // code of the users.
1621 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1622 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1624 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1625 // needs to be updated to be based on SUB. Push the condition code
1626 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1627 // condition code of these operands will be modified.
1628 bool ShouldSwap = false;
1630 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1631 Sub->getOperand(2).getReg() == SrcReg;
1633 // The operands to subf are the opposite of sub, so only in the fixed-point
1634 // case, invert the order.
1635 ShouldSwap = !ShouldSwap;
1639 for (MachineRegisterInfo::use_instr_iterator
1640 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1642 MachineInstr *UseMI = &*I;
1643 if (UseMI->getOpcode() == PPC::BCC) {
1644 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1645 assert((!equalityOnly ||
1646 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1647 "Invalid predicate for equality-only optimization");
1648 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1649 PPC::getSwappedPredicate(Pred)));
1650 } else if (UseMI->getOpcode() == PPC::ISEL ||
1651 UseMI->getOpcode() == PPC::ISEL8) {
1652 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1653 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1654 "Invalid CR bit for equality-only optimization");
1656 if (NewSubReg == PPC::sub_lt)
1657 NewSubReg = PPC::sub_gt;
1658 else if (NewSubReg == PPC::sub_gt)
1659 NewSubReg = PPC::sub_lt;
1661 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1663 } else // We need to abort on a user we don't understand.
1667 // Create a new virtual register to hold the value of the CR set by the
1668 // record-form instruction. If the instruction was not previously in
1669 // record form, then set the kill flag on the CR.
1670 CmpInstr->eraseFromParent();
1672 MachineBasicBlock::iterator MII = MI;
1673 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1674 get(TargetOpcode::COPY), CRReg)
1675 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1677 if (MIOpC != NewOpC) {
1678 // We need to be careful here: we're replacing one instruction with
1679 // another, and we need to make sure that we get all of the right
1680 // implicit uses and defs. On the other hand, the caller may be holding
1681 // an iterator to this instruction, and so we can't delete it (this is
1682 // specifically the case if this is the instruction directly after the
1685 const MCInstrDesc &NewDesc = get(NewOpC);
1686 MI->setDesc(NewDesc);
1688 if (NewDesc.ImplicitDefs)
1689 for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
1690 *ImpDefs; ++ImpDefs)
1691 if (!MI->definesRegister(*ImpDefs))
1692 MI->addOperand(*MI->getParent()->getParent(),
1693 MachineOperand::CreateReg(*ImpDefs, true, true));
1694 if (NewDesc.ImplicitUses)
1695 for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
1696 *ImpUses; ++ImpUses)
1697 if (!MI->readsRegister(*ImpUses))
1698 MI->addOperand(*MI->getParent()->getParent(),
1699 MachineOperand::CreateReg(*ImpUses, false, true));
1702 // Modify the condition code of operands in OperandsToUpdate.
1703 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1704 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1705 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1706 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1708 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1709 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1714 /// GetInstSize - Return the number of bytes of code the specified
1715 /// instruction may be. This returns the maximum number of bytes.
1717 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1718 unsigned Opcode = MI->getOpcode();
1720 if (Opcode == PPC::INLINEASM) {
1721 const MachineFunction *MF = MI->getParent()->getParent();
1722 const char *AsmStr = MI->getOperand(0).getSymbolName();
1723 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1724 } else if (Opcode == TargetOpcode::STACKMAP) {
1725 return MI->getOperand(1).getImm();
1726 } else if (Opcode == TargetOpcode::PATCHPOINT) {
1727 PatchPointOpers Opers(MI);
1728 return Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
1730 const MCInstrDesc &Desc = get(Opcode);
1731 return Desc.getSize();