1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 /// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid
19 /// shuffle mask for the VPKUHUM or VPKUWUM instructions.
20 def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{
21 return PPC::isVPKUHUMShuffleMask(N, false);
23 def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
24 return PPC::isVPKUWUMShuffleMask(N, false);
27 def VPKUHUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
28 return PPC::isVPKUHUMShuffleMask(N, true);
30 def VPKUWUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
31 return PPC::isVPKUWUMShuffleMask(N, true);
35 def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{
36 return PPC::isVMRGLShuffleMask(N, 1, false);
38 def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{
39 return PPC::isVMRGLShuffleMask(N, 2, false);
41 def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{
42 return PPC::isVMRGLShuffleMask(N, 4, false);
44 def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{
45 return PPC::isVMRGHShuffleMask(N, 1, false);
47 def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{
48 return PPC::isVMRGHShuffleMask(N, 2, false);
50 def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{
51 return PPC::isVMRGHShuffleMask(N, 4, false);
54 def VMRGLB_unary_shuffle_mask : PatLeaf<(build_vector), [{
55 return PPC::isVMRGLShuffleMask(N, 1, true);
57 def VMRGLH_unary_shuffle_mask : PatLeaf<(build_vector), [{
58 return PPC::isVMRGLShuffleMask(N, 2, true);
60 def VMRGLW_unary_shuffle_mask : PatLeaf<(build_vector), [{
61 return PPC::isVMRGLShuffleMask(N, 4, true);
63 def VMRGHB_unary_shuffle_mask : PatLeaf<(build_vector), [{
64 return PPC::isVMRGHShuffleMask(N, 1, true);
66 def VMRGHH_unary_shuffle_mask : PatLeaf<(build_vector), [{
67 return PPC::isVMRGHShuffleMask(N, 2, true);
69 def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{
70 return PPC::isVMRGHShuffleMask(N, 4, true);
74 def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
75 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
77 def VSLDOI_shuffle_mask : PatLeaf<(build_vector), [{
78 return PPC::isVSLDOIShuffleMask(N, false) != -1;
81 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
82 /// vector_shuffle(X,undef,mask) by the dag combiner.
83 def VSLDOI_unary_get_imm : SDNodeXForm<build_vector, [{
84 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
86 def VSLDOI_unary_shuffle_mask : PatLeaf<(build_vector), [{
87 return PPC::isVSLDOIShuffleMask(N, true) != -1;
88 }], VSLDOI_unary_get_imm>;
91 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
92 def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
93 return getI32Imm(PPC::getVSPLTImmediate(N, 1));
95 def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
96 return PPC::isSplatShuffleMask(N, 1);
98 def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
99 return getI32Imm(PPC::getVSPLTImmediate(N, 2));
101 def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
102 return PPC::isSplatShuffleMask(N, 2);
104 def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
105 return getI32Imm(PPC::getVSPLTImmediate(N, 4));
107 def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
108 return PPC::isSplatShuffleMask(N, 4);
112 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
113 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
114 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
116 def vecspltisb : PatLeaf<(build_vector), [{
117 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).Val != 0;
118 }], VSPLTISB_get_imm>;
120 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
121 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
122 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
124 def vecspltish : PatLeaf<(build_vector), [{
125 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).Val != 0;
126 }], VSPLTISH_get_imm>;
128 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
129 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
130 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
132 def vecspltisw : PatLeaf<(build_vector), [{
133 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0;
134 }], VSPLTISW_get_imm>;
136 //===----------------------------------------------------------------------===//
137 // Helpers for defining instructions that directly correspond to intrinsics.
139 // VA1a_Int - A VAForm_1a intrinsic definition.
140 class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
141 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC),
142 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
143 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
145 // VX1_Int - A VXForm_1 intrinsic definition.
146 class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
147 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
148 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
149 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
151 // VX2_Int - A VXForm_2 intrinsic definition.
152 class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
153 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB),
154 !strconcat(opc, " $vD, $vB"), VecFP,
155 [(set VRRC:$vD, (IntID VRRC:$vB))]>;
157 //===----------------------------------------------------------------------===//
158 // Instruction Definitions.
160 def IMPLICIT_DEF_VRRC : Pseudo<(outs VRRC:$rD), (ins),"; IMPLICIT_DEF_VRRC $rD",
161 [(set VRRC:$rD, (v4i32 (undef)))]>;
163 def DSS : DSS_Form<822, (outs), (ins u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
164 "dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
165 def DST : DSS_Form<342, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
166 "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
167 def DSTST : DSS_Form<374, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
168 "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
170 def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins),
171 "mfvcr $vD", LdStGeneral,
172 [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>;
173 def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB),
174 "mtvcr $vB", LdStGeneral,
175 [(int_ppc_altivec_mtvscr VRRC:$vB)]>;
177 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
178 def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src),
179 "lvebx $vD, $src", LdStGeneral,
180 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
181 def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src),
182 "lvehx $vD, $src", LdStGeneral,
183 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
184 def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src),
185 "lvewx $vD, $src", LdStGeneral,
186 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
187 def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src),
188 "lvx $vD, $src", LdStGeneral,
189 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
190 def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src),
191 "lvxl $vD, $src", LdStGeneral,
192 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
195 def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src),
196 "lvsl $vD, $src", LdStGeneral,
197 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
199 def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src),
200 "lvsr $vD, $src", LdStGeneral,
201 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
204 let isStore = 1, PPC970_Unit = 2 in { // Stores.
205 def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst),
206 "stvebx $rS, $dst", LdStGeneral,
207 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
208 def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst),
209 "stvehx $rS, $dst", LdStGeneral,
210 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
211 def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst),
212 "stvewx $rS, $dst", LdStGeneral,
213 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
214 def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst),
215 "stvx $rS, $dst", LdStGeneral,
216 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
217 def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst),
218 "stvxl $rS, $dst", LdStGeneral,
219 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
222 let PPC970_Unit = 5 in { // VALU Operations.
223 // VA-Form instructions. 3-input AltiVec ops.
224 def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
225 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
226 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
228 Requires<[FPContractions]>;
229 def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
230 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
231 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
233 Requires<[FPContractions]>;
235 def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
236 def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
237 def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>;
238 def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>;
239 def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
242 def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH),
243 "vsldoi $vD, $vA, $vB, $SH", VecFP,
245 (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB,
246 VSLDOI_shuffle_mask:$SH))]>;
248 // VX-Form instructions. AltiVec arithmetic ops.
249 def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
250 "vaddfp $vD, $vA, $vB", VecFP,
251 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
253 def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
254 "vaddubm $vD, $vA, $vB", VecGeneral,
255 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
256 def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
257 "vadduhm $vD, $vA, $vB", VecGeneral,
258 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
259 def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
260 "vadduwm $vD, $vA, $vB", VecGeneral,
261 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
263 def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
264 def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
265 def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
266 def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
267 def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
268 def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
269 def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
272 def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
273 "vand $vD, $vA, $vB", VecFP,
274 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
275 def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
276 "vandc $vD, $vA, $vB", VecFP,
277 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
279 def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
280 "vcfsx $vD, $vB, $UIMM", VecFP,
282 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
283 def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
284 "vcfux $vD, $vB, $UIMM", VecFP,
286 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
287 def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
288 "vctsxs $vD, $vB, $UIMM", VecFP,
290 (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>;
291 def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
292 "vctuxs $vD, $vB, $UIMM", VecFP,
294 (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>;
295 def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
296 def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>;
298 def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>;
299 def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>;
300 def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>;
301 def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>;
302 def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>;
303 def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>;
305 def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>;
306 def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>;
307 def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>;
308 def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>;
309 def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>;
310 def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>;
311 def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>;
312 def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>;
313 def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>;
314 def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>;
315 def VMINSW : VX1_Int< 898, "vminsw", int_ppc_altivec_vminsw>;
316 def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>;
317 def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>;
318 def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
320 def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
321 "vmrghb $vD, $vA, $vB", VecFP,
322 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
323 VRRC:$vB, VMRGHB_shuffle_mask))]>;
324 def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
325 "vmrghh $vD, $vA, $vB", VecFP,
326 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
327 VRRC:$vB, VMRGHH_shuffle_mask))]>;
328 def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
329 "vmrghw $vD, $vA, $vB", VecFP,
330 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
331 VRRC:$vB, VMRGHW_shuffle_mask))]>;
332 def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
333 "vmrglb $vD, $vA, $vB", VecFP,
334 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
335 VRRC:$vB, VMRGLB_shuffle_mask))]>;
336 def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
337 "vmrglh $vD, $vA, $vB", VecFP,
338 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
339 VRRC:$vB, VMRGLH_shuffle_mask))]>;
340 def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
341 "vmrglw $vD, $vA, $vB", VecFP,
342 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
343 VRRC:$vB, VMRGLW_shuffle_mask))]>;
345 def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
346 def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
347 def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
348 def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
349 def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
350 def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
352 def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
353 def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
354 def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
355 def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
356 def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
357 def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
358 def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>;
359 def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
361 def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>;
362 def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>;
363 def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>;
364 def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>;
365 def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>;
366 def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
368 def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
370 def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
371 "vsubfp $vD, $vA, $vB", VecGeneral,
372 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
373 def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
374 "vsububm $vD, $vA, $vB", VecGeneral,
375 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
376 def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
377 "vsubuhm $vD, $vA, $vB", VecGeneral,
378 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
379 def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
380 "vsubuwm $vD, $vA, $vB", VecGeneral,
381 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
383 def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
384 def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
385 def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
386 def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
387 def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
388 def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
389 def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
390 def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
391 def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
392 def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
393 def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
395 def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
396 "vnor $vD, $vA, $vB", VecFP,
397 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
398 def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
399 "vor $vD, $vA, $vB", VecFP,
400 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
401 def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
402 "vxor $vD, $vA, $vB", VecFP,
403 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
405 def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>;
406 def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
407 def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
409 def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >;
410 def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
411 def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
412 def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
413 def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
415 def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
416 "vspltb $vD, $vB, $UIMM", VecPerm,
417 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
418 VSPLTB_shuffle_mask:$UIMM))]>;
419 def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
420 "vsplth $vD, $vB, $UIMM", VecPerm,
421 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
422 VSPLTH_shuffle_mask:$UIMM))]>;
423 def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
424 "vspltw $vD, $vB, $UIMM", VecPerm,
425 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
426 VSPLTW_shuffle_mask:$UIMM))]>;
428 def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
429 def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
430 def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
431 def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
432 def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
433 def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
434 def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
435 def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
438 def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM),
439 "vspltisb $vD, $SIMM", VecPerm,
440 [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>;
441 def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM),
442 "vspltish $vD, $SIMM", VecPerm,
443 [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>;
444 def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM),
445 "vspltisw $vD, $SIMM", VecPerm,
446 [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>;
449 def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
450 def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
451 def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
452 def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
453 def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
454 def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
455 "vpkuhum $vD, $vA, $vB", VecFP,
456 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
457 VRRC:$vB, VPKUHUM_shuffle_mask))]>;
458 def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
459 def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
460 "vpkuwum $vD, $vA, $vB", VecFP,
461 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
462 VRRC:$vB, VPKUWUM_shuffle_mask))]>;
463 def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
466 def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
467 def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
468 def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
469 def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
470 def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
471 def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
474 // Altivec Comparisons.
476 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
477 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare,
478 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
479 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
480 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare,
481 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> {
486 // f32 element comparisons.0
487 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
488 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
489 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
490 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
491 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
492 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
493 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
494 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
496 // i8 element comparisons.
497 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
498 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
499 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
500 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
501 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
502 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
504 // i16 element comparisons.
505 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
506 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
507 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
508 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
509 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
510 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
512 // i32 element comparisons.
513 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
514 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
515 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
516 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
517 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
518 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
520 def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins),
521 "vxor $vD, $vD, $vD", VecFP,
522 [(set VRRC:$vD, (v4i32 immAllZerosV))]>;
525 //===----------------------------------------------------------------------===//
526 // Additional Altivec Patterns
530 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
531 def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>;
532 def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
533 (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
534 def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
535 (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
536 def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
537 (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
538 def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
539 (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
542 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VRRC)>;
543 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VRRC)>;
544 def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VRRC)>;
547 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
550 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
551 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
554 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
555 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
556 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
558 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
559 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
560 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
562 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
563 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
564 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
566 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
567 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
568 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
572 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
573 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VSLDOI_unary_shuffle_mask:$in),
574 (VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_unary_shuffle_mask:$in)>;
575 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUWUM_unary_shuffle_mask:$in),
576 (VPKUWUM VRRC:$vA, VRRC:$vA)>;
577 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUHUM_unary_shuffle_mask:$in),
578 (VPKUHUM VRRC:$vA, VRRC:$vA)>;
581 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in),
582 (VMRGLB VRRC:$vA, VRRC:$vA)>;
583 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLH_unary_shuffle_mask:$in),
584 (VMRGLH VRRC:$vA, VRRC:$vA)>;
585 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLW_unary_shuffle_mask:$in),
586 (VMRGLW VRRC:$vA, VRRC:$vA)>;
587 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHB_unary_shuffle_mask:$in),
588 (VMRGHB VRRC:$vA, VRRC:$vA)>;
589 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHH_unary_shuffle_mask:$in),
590 (VMRGHH VRRC:$vA, VRRC:$vA)>;
591 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in),
592 (VMRGHW VRRC:$vA, VRRC:$vA)>;
594 // Logical Operations
595 def : Pat<(v4i32 (vnot VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>;
596 def : Pat<(v4i32 (vnot_conv VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>;
598 def : Pat<(v4i32 (vnot_conv (or VRRC:$A, VRRC:$B))),
599 (VNOR VRRC:$A, VRRC:$B)>;
600 def : Pat<(v4i32 (and VRRC:$A, (vnot_conv VRRC:$B))),
601 (VANDC VRRC:$A, VRRC:$B)>;
603 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
604 (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>;
606 // Fused multiply add and multiply sub for packed float. These are represented
607 // separately from the real instructions above, for operations that must have
608 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
609 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
610 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
611 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
612 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
614 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
615 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
616 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
617 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
619 def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
620 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>;