1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
19 def VSPLT_get_imm : SDNodeXForm<build_vector, [{
20 return getI32Imm(PPC::getVSPLTImmediate(N));
23 def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
24 return PPC::isSplatShuffleMask(N);
28 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
29 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
31 PPC::isVecSplatImm(N, 1, &Val);
32 return getI32Imm(Val);
34 def vecspltisb : PatLeaf<(build_vector), [{
35 return PPC::isVecSplatImm(N, 1);
36 }], VSPLTISB_get_imm>;
38 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
39 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
41 PPC::isVecSplatImm(N, 2, &Val);
42 return getI32Imm(Val);
44 def vecspltish : PatLeaf<(build_vector), [{
45 return PPC::isVecSplatImm(N, 2);
46 }], VSPLTISH_get_imm>;
48 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
49 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
51 PPC::isVecSplatImm(N, 4, &Val);
52 return getI32Imm(Val);
54 def vecspltisw : PatLeaf<(build_vector), [{
55 return PPC::isVecSplatImm(N, 4);
56 }], VSPLTISW_get_imm>;
58 class isVDOT { // vector dot instruction.
59 list<Register> Defs = [CR6];
63 //===----------------------------------------------------------------------===//
64 // Instruction Definitions.
66 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
67 [(set VRRC:$rD, (v4f32 (undef)))]>;
69 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
70 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
71 "lvebx $vD, $src", LdStGeneral,
72 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
73 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
74 "lvehx $vD, $src", LdStGeneral,
75 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
76 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
77 "lvewx $vD, $src", LdStGeneral,
78 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
79 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
80 "lvx $vD, $src", LdStGeneral,
81 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
82 def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
83 "lvxl $vD, $src", LdStGeneral,
84 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
87 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
88 "lvsl $vD, $base, $rA", LdStGeneral,
90 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
91 "lvsl $vD, $base, $rA", LdStGeneral,
94 let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
95 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
96 "stvebx $rS, $dst", LdStGeneral,
97 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
98 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
99 "stvehx $rS, $dst", LdStGeneral,
100 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
101 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
102 "stvewx $rS, $dst", LdStGeneral,
103 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
104 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
105 "stvx $rS, $dst", LdStGeneral,
106 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
107 def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
108 "stvxl $rS, $dst", LdStGeneral,
109 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
112 let PPC970_Unit = 5 in { // VALU Operations.
113 // VA-Form instructions. 3-input AltiVec ops.
114 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
115 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
116 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
118 Requires<[FPContractions]>;
119 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
120 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
121 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
123 Requires<[FPContractions]>;
124 def VMHADDSHS : VAForm_1a<32, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
125 "vmhaddshs $vD, $vA, $vB, $vC", VecFP,
127 (int_ppc_altivec_vmhaddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
128 def VMHRADDSHS : VAForm_1a<33, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
129 "vmhraddshs $vD, $vA, $vB, $vC", VecFP,
131 (int_ppc_altivec_vmhraddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
132 def VPERM : VAForm_1a<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
133 "vperm $vD, $vA, $vB, $vC", VecPerm,
135 (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
136 def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
137 "vsldoi $vD, $vA, $vB, $SH", VecFP,
139 (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
141 def VSEL : VAForm_1a<42, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
142 "vsel $vD, $vA, $vB, $vC", VecFP,
144 (int_ppc_altivec_vsel VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
146 // VX-Form instructions. AltiVec arithmetic ops.
147 def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
148 "vaddcuw $vD, $vA, $vB", VecFP,
150 (int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>;
151 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
152 "vaddfp $vD, $vA, $vB", VecFP,
153 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
155 def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
156 "vaddubm $vD, $vA, $vB", VecGeneral,
157 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
158 def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
159 "vadduhm $vD, $vA, $vB", VecGeneral,
160 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
161 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
162 "vadduwm $vD, $vA, $vB", VecGeneral,
163 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
165 def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
166 "vaddsbs $vD, $vA, $vB", VecFP,
168 (int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>;
169 def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
170 "vaddshs $vD, $vA, $vB", VecFP,
172 (int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>;
173 def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
174 "vaddsws $vD, $vA, $vB", VecFP,
176 (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>;
178 def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
179 "vaddubs $vD, $vA, $vB", VecFP,
181 (int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>;
182 def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
183 "vadduhs $vD, $vA, $vB", VecFP,
185 (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>;
186 def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
187 "vadduws $vD, $vA, $vB", VecFP,
189 (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>;
190 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
191 "vand $vD, $vA, $vB", VecFP,
192 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
193 def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
194 "vandc $vD, $vA, $vB", VecFP,
195 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
197 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
198 "vcfsx $vD, $vB, $UIMM", VecFP,
200 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
201 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
202 "vcfux $vD, $vB, $UIMM", VecFP,
204 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
205 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
206 "vctsxs $vD, $vB, $UIMM", VecFP,
208 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
209 "vctuxs $vD, $vB, $UIMM", VecFP,
211 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
212 "vexptefp $vD, $vB", VecFP,
213 [(set VRRC:$vD, (int_ppc_altivec_vexptefp VRRC:$vB))]>;
214 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
215 "vlogefp $vD, $vB", VecFP,
216 [(set VRRC:$vD, (int_ppc_altivec_vlogefp VRRC:$vB))]>;
217 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
218 "vmaxfp $vD, $vA, $vB", VecFP,
220 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
221 "vminfp $vD, $vA, $vB", VecFP,
223 def VMRGHH : VXForm_1<76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
224 "vmrghh $vD, $vA, $vB", VecFP,
226 (int_ppc_altivec_vmrghh VRRC:$vA, VRRC:$vB))]>;
227 def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
228 "vmrghh $vD, $vA, $vB", VecFP,
230 (int_ppc_altivec_vmrghw VRRC:$vA, VRRC:$vB))]>;
231 def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
232 "vmrglh $vD, $vA, $vB", VecFP,
234 (int_ppc_altivec_vmrglh VRRC:$vA, VRRC:$vB))]>;
235 def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
236 "vmrglh $vD, $vA, $vB", VecFP,
238 (int_ppc_altivec_vmrglw VRRC:$vA, VRRC:$vB))]>;
239 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
240 "vrefp $vD, $vB", VecFP,
241 [(set VRRC:$vD, (int_ppc_altivec_vrefp VRRC:$vB))]>;
242 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
243 "vrfim $vD, $vB", VecFP,
244 [(set VRRC:$vD, (int_ppc_altivec_vrfim VRRC:$vB))]>;
245 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
246 "vrfin $vD, $vB", VecFP,
247 [(set VRRC:$vD, (int_ppc_altivec_vrfin VRRC:$vB))]>;
248 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
249 "vrfip $vD, $vB", VecFP,
250 [(set VRRC:$vD, (int_ppc_altivec_vrfip VRRC:$vB))]>;
251 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
252 "vrfiz $vD, $vB", VecFP,
253 [(set VRRC:$vD, (int_ppc_altivec_vrfiz VRRC:$vB))]>;
254 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
255 "vrsqrtefp $vD, $vB", VecFP,
256 [(set VRRC:$vD,(int_ppc_altivec_vrsqrtefp VRRC:$vB))]>;
257 def VSUBCUW : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
258 "vsubcuw $vD, $vA, $vB", VecFP,
260 (int_ppc_altivec_vsubcuw VRRC:$vA, VRRC:$vB))]>;
261 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
262 "vsubfp $vD, $vA, $vB", VecFP,
263 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
265 def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
266 "vsububm $vD, $vA, $vB", VecGeneral,
267 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
268 def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
269 "vsubuhm $vD, $vA, $vB", VecGeneral,
270 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
271 def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
272 "vsubuwm $vD, $vA, $vB", VecGeneral,
273 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
275 def VSUBSBS : VXForm_1<1792, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
276 "vsubsbs $vD, $vA, $vB", VecFP,
278 (int_ppc_altivec_vsubsbs VRRC:$vA, VRRC:$vB))]>;
279 def VSUBSHS : VXForm_1<1856, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
280 "vsubshs $vD, $vA, $vB", VecFP,
282 (int_ppc_altivec_vsubshs VRRC:$vA, VRRC:$vB))]>;
283 def VSUBSWS : VXForm_1<1920, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
284 "vsubsws $vD, $vA, $vB", VecFP,
286 (int_ppc_altivec_vsubsws VRRC:$vA, VRRC:$vB))]>;
288 def VSUBUBS : VXForm_1<1536, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
289 "vsububs $vD, $vA, $vB", VecFP,
291 (int_ppc_altivec_vsububs VRRC:$vA, VRRC:$vB))]>;
292 def VSUBUHS : VXForm_1<1600, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
293 "vsubuhs $vD, $vA, $vB", VecFP,
295 (int_ppc_altivec_vsubuhs VRRC:$vA, VRRC:$vB))]>;
296 def VSUBUWS : VXForm_1<1664, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
297 "vsubuws $vD, $vA, $vB", VecFP,
299 (int_ppc_altivec_vsubuws VRRC:$vA, VRRC:$vB))]>;
301 def VSUMSWS : VXForm_1<1928, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
302 "vsumsws $vD, $vA, $vB", VecFP,
304 (int_ppc_altivec_vsumsws VRRC:$vA, VRRC:$vB))]>;
305 def VSUM2SWS: VXForm_1<1672, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
306 "vsum2sws $vD, $vA, $vB", VecFP,
308 (int_ppc_altivec_vsum2sws VRRC:$vA, VRRC:$vB))]>;
309 def VSUM4SBS: VXForm_1<1672, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
310 "vsum4sbs $vD, $vA, $vB", VecFP,
312 (int_ppc_altivec_vsum4sbs VRRC:$vA, VRRC:$vB))]>;
313 def VSUM4SHS: VXForm_1<1608, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
314 "vsum4shs $vD, $vA, $vB", VecFP,
316 (int_ppc_altivec_vsum4shs VRRC:$vA, VRRC:$vB))]>;
317 def VSUM4UBS: VXForm_1<1544, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
318 "vsum4ubs $vD, $vA, $vB", VecFP,
320 (int_ppc_altivec_vsum4ubs VRRC:$vA, VRRC:$vB))]>;
322 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
323 "vnor $vD, $vA, $vB", VecFP,
324 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
325 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
326 "vor $vD, $vA, $vB", VecFP,
327 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
328 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
329 "vxor $vD, $vA, $vB", VecFP,
330 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
332 def VRLB : VXForm_1<4, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
333 "vrlb $vD, $vA, $vB", VecFP,
335 (int_ppc_altivec_vrlb VRRC:$vA, VRRC:$vB))]>;
336 def VRLH : VXForm_1<68, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
337 "vrlh $vD, $vA, $vB", VecFP,
339 (int_ppc_altivec_vrlh VRRC:$vA, VRRC:$vB))]>;
340 def VRLW : VXForm_1<132, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
341 "vrlw $vD, $vA, $vB", VecFP,
343 (int_ppc_altivec_vrlw VRRC:$vA, VRRC:$vB))]>;
345 def VSLO : VXForm_1<1036, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
346 "vslo $vD, $vA, $vB", VecFP,
348 (int_ppc_altivec_vslo VRRC:$vA, VRRC:$vB))]>;
349 def VSLB : VXForm_1<260, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
350 "vslb $vD, $vA, $vB", VecFP,
352 (int_ppc_altivec_vslb VRRC:$vA, VRRC:$vB))]>;
353 def VSLH : VXForm_1<324, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
354 "vslh $vD, $vA, $vB", VecFP,
356 (int_ppc_altivec_vslh VRRC:$vA, VRRC:$vB))]>;
357 def VSLW : VXForm_1<388, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
358 "vslw $vD, $vA, $vB", VecFP,
360 (int_ppc_altivec_vslw VRRC:$vA, VRRC:$vB))]>;
362 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
363 "vspltb $vD, $vB, $UIMM", VecPerm,
365 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
366 "vsplth $vD, $vB, $UIMM", VecPerm,
368 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
369 "vspltw $vD, $vB, $UIMM", VecPerm,
370 [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
371 VSPLT_shuffle_mask:$UIMM))]>;
373 def VSR : VXForm_1<708, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
374 "vsr $vD, $vA, $vB", VecFP,
376 (int_ppc_altivec_vsr VRRC:$vA, VRRC:$vB))]>;
377 def VSRO : VXForm_1<1100, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
378 "vsro $vD, $vA, $vB", VecFP,
380 (int_ppc_altivec_vsro VRRC:$vA, VRRC:$vB))]>;
381 def VSRAB : VXForm_1<772, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
382 "vsrab $vD, $vA, $vB", VecFP,
384 (int_ppc_altivec_vsrab VRRC:$vA, VRRC:$vB))]>;
385 def VSRAH : VXForm_1<836, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
386 "vsrah $vD, $vA, $vB", VecFP,
388 (int_ppc_altivec_vsrah VRRC:$vA, VRRC:$vB))]>;
389 def VSRAW : VXForm_1<900, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
390 "vsraw $vD, $vA, $vB", VecFP,
392 (int_ppc_altivec_vsraw VRRC:$vA, VRRC:$vB))]>;
393 def VSRB : VXForm_1<516, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
394 "vsrb $vD, $vA, $vB", VecFP,
396 (int_ppc_altivec_vsrb VRRC:$vA, VRRC:$vB))]>;
397 def VSRH : VXForm_1<580, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
398 "vsrh $vD, $vA, $vB", VecFP,
400 (int_ppc_altivec_vsrh VRRC:$vA, VRRC:$vB))]>;
401 def VSRW : VXForm_1<644, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
402 "vsrw $vD, $vA, $vB", VecFP,
404 (int_ppc_altivec_vsrw VRRC:$vA, VRRC:$vB))]>;
407 def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
408 "vspltisb $vD, $SIMM", VecPerm,
409 [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
410 def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
411 "vspltish $vD, $SIMM", VecPerm,
412 [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
413 def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
414 "vspltisw $vD, $SIMM", VecPerm,
415 [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
418 // Altivec Comparisons.
420 // f32 element comparisons.
421 def VCMPBFP : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
422 "vcmpbfp $vD, $vA, $vB", VecFPCompare,
424 (int_ppc_altivec_vcmpbfp VRRC:$vA, VRRC:$vB))]>;
425 def VCMPBFPo : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
426 "vcmpbfp. $vD, $vA, $vB", VecFPCompare,
427 [(set VRRC:$vD, (v4f32
428 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 966)))]>, isVDOT;
429 def VCMPEQFP : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
430 "vcmpeqfp $vD, $vA, $vB", VecFPCompare,
432 (int_ppc_altivec_vcmpeqfp VRRC:$vA, VRRC:$vB))]>;
433 def VCMPEQFPo : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
434 "vcmpeqfp. $vD, $vA, $vB", VecFPCompare,
435 [(set VRRC:$vD, (v4f32
436 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 198)))]>, isVDOT;
437 def VCMPGEFP : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
438 "vcmpgefp $vD, $vA, $vB", VecFPCompare,
440 (int_ppc_altivec_vcmpgefp VRRC:$vA, VRRC:$vB))]>;
441 def VCMPGEFPo : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
442 "vcmpgefp. $vD, $vA, $vB", VecFPCompare,
443 [(set VRRC:$vD, (v4f32
444 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 454)))]>, isVDOT;
445 def VCMPGTFP : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
446 "vcmpgtfp $vD, $vA, $vB", VecFPCompare,
448 (int_ppc_altivec_vcmpgtfp VRRC:$vA, VRRC:$vB))]>;
449 def VCMPGTFPo : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
450 "vcmpgtfp. $vD, $vA, $vB", VecFPCompare,
451 [(set VRRC:$vD, (v4f32
452 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 710)))]>, isVDOT;
454 // i8 element comparisons.
455 def VCMPEQUB : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
456 "vcmpequb $vD, $vA, $vB", VecFPCompare,
458 (int_ppc_altivec_vcmpequb VRRC:$vA, VRRC:$vB))]>;
459 def VCMPEQUBo : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
460 "vcmpequb. $vD, $vA, $vB", VecFPCompare,
461 [(set VRRC:$vD, (v16i8
462 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 6)))]>, isVDOT;
463 def VCMPGTSB : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
464 "vcmpgtsb $vD, $vA, $vB", VecFPCompare,
466 (int_ppc_altivec_vcmpgtsb VRRC:$vA, VRRC:$vB))]>;
467 def VCMPGTSBo : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
468 "vcmpgtsb. $vD, $vA, $vB", VecFPCompare,
469 [(set VRRC:$vD, (v16i8
470 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 774)))]>, isVDOT;
471 def VCMPGTUB : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
472 "vcmpgtub $vD, $vA, $vB", VecFPCompare,
474 (int_ppc_altivec_vcmpgtub VRRC:$vA, VRRC:$vB))]>;
475 def VCMPGTUBo : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
476 "vcmpgtub. $vD, $vA, $vB", VecFPCompare,
477 [(set VRRC:$vD, (v16i8
478 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 518)))]>, isVDOT;
480 // i16 element comparisons.
481 def VCMPEQUH : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
482 "vcmpequh $vD, $vA, $vB", VecFPCompare,
484 (int_ppc_altivec_vcmpequh VRRC:$vA, VRRC:$vB))]>;
485 def VCMPEQUHo : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
486 "vcmpequh. $vD, $vA, $vB", VecFPCompare,
487 [(set VRRC:$vD, (v8i16
488 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 70)))]>, isVDOT;
489 def VCMPGTSH : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
490 "vcmpgtsh $vD, $vA, $vB", VecFPCompare,
492 (int_ppc_altivec_vcmpgtsh VRRC:$vA, VRRC:$vB))]>;
493 def VCMPGTSHo : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
494 "vcmpgtsh. $vD, $vA, $vB", VecFPCompare,
495 [(set VRRC:$vD, (v8i16
496 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 838)))]>, isVDOT;
497 def VCMPGTUH : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
498 "vcmpgtuh $vD, $vA, $vB", VecFPCompare,
500 (int_ppc_altivec_vcmpgtuh VRRC:$vA, VRRC:$vB))]>;
501 def VCMPGTUHo : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
502 "vcmpgtuh. $vD, $vA, $vB", VecFPCompare,
503 [(set VRRC:$vD, (v8i16
504 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 582)))]>, isVDOT;
506 // i32 element comparisons.
507 def VCMPEQUW : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
508 "vcmpequw $vD, $vA, $vB", VecFPCompare,
510 (int_ppc_altivec_vcmpequw VRRC:$vA, VRRC:$vB))]>;
511 def VCMPEQUWo : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
512 "vcmpequw. $vD, $vA, $vB", VecFPCompare,
513 [(set VRRC:$vD, (v4i32
514 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 134)))]>, isVDOT;
515 def VCMPGTSW : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
516 "vcmpgtsw $vD, $vA, $vB", VecFPCompare,
518 (int_ppc_altivec_vcmpgtsw VRRC:$vA, VRRC:$vB))]>;
519 def VCMPGTSWo : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
520 "vcmpgtsw. $vD, $vA, $vB", VecFPCompare,
521 [(set VRRC:$vD, (v4i32
522 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 902)))]>, isVDOT;
523 def VCMPGTUW : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
524 "vcmpgtuw $vD, $vA, $vB", VecFPCompare,
526 (int_ppc_altivec_vcmpgtuw VRRC:$vA, VRRC:$vB))]>;
527 def VCMPGTUWo : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
528 "vcmpgtuw. $vD, $vA, $vB", VecFPCompare,
529 [(set VRRC:$vD, (v4i32
530 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 646)))]>, isVDOT;
532 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
533 "vxor $vD, $vD, $vD", VecFP,
534 [(set VRRC:$vD, (v4f32 immAllZerosV))]>;
537 //===----------------------------------------------------------------------===//
538 // Additional Altivec Patterns
542 def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
543 def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
544 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
545 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
546 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
547 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
550 def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
551 def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
552 def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
553 def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
556 def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
557 (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
558 def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
559 (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
560 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
561 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
562 def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
563 (STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
566 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
567 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
568 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
570 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
571 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
572 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
574 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
575 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
576 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
578 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
579 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
580 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
582 // Immediate vector formation with vsplti*.
583 def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
584 def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
585 def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
587 def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
588 def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
589 def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
591 def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
592 def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
593 def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
595 // Logical Operations
596 def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
597 def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
598 def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
599 def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
600 def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
601 def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
602 def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
603 def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
604 def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
605 (v16i8 (VANDC VRRC:$A, VRRC:$B))>;
606 def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
607 (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
609 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
610 (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
612 // Fused multiply add and multiply sub for packed float. These are represented
613 // separately from the real instructions above, for operations that must have
614 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
615 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
616 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
617 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
618 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
620 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
621 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
622 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
623 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
624 def : Pat<(int_ppc_altivec_vperm VRRC:$A, VRRC:$B, VRRC:$C),
625 (VPERM VRRC:$A, VRRC:$B, VRRC:$C)>;
626 def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
627 (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
629 def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
630 (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;