1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
27 enum NodeType : unsigned {
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// The CMPB instruction (takes two operands of i32 or i64).
67 /// Hi/Lo - These represent the high and low 16-bit parts of a global
68 /// address respectively. These nodes have two operands, the first of
69 /// which must be a TargetGlobalAddress, and the second of which must be a
70 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
71 /// though these are usually folded into other nodes.
74 /// The following two target-specific nodes are used for calls through
75 /// function pointers in the 64-bit SVR4 ABI.
77 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
78 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
79 /// compute an allocation on the stack.
82 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
83 /// compute an offset from native SP to the address of the most recent
87 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
88 /// at function entry, used for PIC code.
91 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
92 /// shift amounts. These nodes are generated by the multi-precision shift
96 /// The combination of sra[wd]i and addze used to implemented signed
97 /// integer division by a power of 2. The first operand is the dividend,
98 /// and the second is the constant shift amount (representing the
102 /// CALL - A direct function call.
103 /// CALL_NOP is a call with the special NOP which follows 64-bit
107 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
108 /// MTCTR instruction.
111 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
112 /// BCTRL instruction.
115 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
116 /// instruction and the TOC reload required on SVR4 PPC64.
119 /// Return with a flag operand, matched by 'blr'
122 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
123 /// This copies the bits corresponding to the specified CRREG into the
124 /// resultant GPR. Bits corresponding to other CR regs are undefined.
127 /// Direct move from a VSX register to a GPR
130 /// Direct move from a GPR to a VSX register (algebraic)
133 /// Direct move from a GPR to a VSX register (zero)
136 // FIXME: Remove these once the ANDI glue bug is fixed:
137 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
138 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
139 /// implement truncation of i32 or i64 to i1.
140 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
142 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
143 // target (returns (Lo, Hi)). It takes a chain operand.
146 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
149 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
152 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
153 /// instructions. For lack of better number, we use the opcode number
154 /// encoding for the OPC field to identify the compare. For example, 838
158 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
159 /// altivec VCMP*o instructions. For lack of better number, we use the
160 /// opcode number encoding for the OPC field to identify the compare. For
161 /// example, 838 is VCMPGTSH.
164 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
165 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
166 /// condition register to branch on, OPC is the branch opcode to use (e.g.
167 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
168 /// an optional input flag argument.
171 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
175 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
176 /// towards zero. Used only as part of the long double-to-int
177 /// conversion sequence.
180 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
183 /// TC_RETURN - A tail call return.
185 /// operand #1 callee (register or absolute)
186 /// operand #2 stack adjustment
187 /// operand #3 optional in flag
190 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
194 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
198 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
199 /// local dynamic TLS on PPC32.
202 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
203 /// TLS model, produces an ADDIS8 instruction that adds the GOT
204 /// base to sym\@got\@tprel\@ha.
207 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
208 /// TLS model, produces a LD instruction with base register G8RReg
209 /// and offset sym\@got\@tprel\@l. This completes the addition that
210 /// finds the offset of "sym" relative to the thread pointer.
213 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
214 /// model, produces an ADD instruction that adds the contents of
215 /// G8RReg to the thread pointer. Symbol contains a relocation
216 /// sym\@tls which is to be replaced by the thread pointer and
217 /// identifies to the linker that the instruction is part of a
221 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
222 /// model, produces an ADDIS8 instruction that adds the GOT base
223 /// register to sym\@got\@tlsgd\@ha.
226 /// %X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
227 /// model, produces an ADDI8 instruction that adds G8RReg to
228 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
229 /// ADDIS_TLSGD_L_ADDR until after register assignment.
232 /// %X3 = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
233 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
234 /// ADDIS_TLSGD_L_ADDR until after register assignment.
237 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
238 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
239 /// register assignment.
242 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
243 /// model, produces an ADDIS8 instruction that adds the GOT base
244 /// register to sym\@got\@tlsld\@ha.
247 /// %X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
248 /// model, produces an ADDI8 instruction that adds G8RReg to
249 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
250 /// ADDIS_TLSLD_L_ADDR until after register assignment.
253 /// %X3 = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
254 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
255 /// ADDIS_TLSLD_L_ADDR until after register assignment.
258 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
259 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
260 /// following register assignment.
263 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol - For the local-dynamic TLS
264 /// model, produces an ADDIS8 instruction that adds X3 to
268 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
269 /// model, produces an ADDI8 instruction that adds G8RReg to
270 /// sym\@got\@dtprel\@l.
273 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
274 /// during instruction selection to optimize a BUILD_VECTOR into
275 /// operations on splats. This is necessary to avoid losing these
276 /// optimizations due to constant folding.
279 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
280 /// operand identifies the operating system entry point.
283 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
286 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
287 /// history rolling buffer entry.
290 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
293 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
294 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
295 /// or stxvd2x instruction. The chain is necessary because the
296 /// sequence replaces a load and needs to provide the same number
300 /// QVFPERM = This corresponds to the QPX qvfperm instruction.
303 /// QVGPCI = This corresponds to the QPX qvgpci instruction.
306 /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
309 /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
312 /// QBFLT = Access the underlying QPX floating-point boolean
316 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
317 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
318 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
320 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
322 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
323 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
324 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
328 /// STFIWX - The STFIWX instruction. The first operand is an input token
329 /// chain, then an f64 value to store, then an address to store it to.
332 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
333 /// load which sign-extends from a 32-bit integer value into the
334 /// destination 64-bit register.
337 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
338 /// load which zero-extends from a 32-bit integer value into the
339 /// destination 64-bit register.
342 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
343 /// Maps directly to an lxvd2x instruction that will be followed by
347 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
348 /// Maps directly to an stxvd2x instruction that will be preceded by
352 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
353 /// The 4xf32 load used for v4i1 constants.
356 /// GPRC = TOC_ENTRY GA, TOC
357 /// Loads the entry for GA from the TOC, where the TOC base is given by
358 /// the last operand.
363 /// Define some predicates that are used for node matching.
365 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
366 /// VPKUHUM instruction.
367 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
370 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
371 /// VPKUWUM instruction.
372 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
375 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
376 /// VPKUDUM instruction.
377 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
380 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
381 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
382 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
383 unsigned ShuffleKind, SelectionDAG &DAG);
385 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
386 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
387 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
388 unsigned ShuffleKind, SelectionDAG &DAG);
390 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
391 /// a VMRGEW or VMRGOW instruction
392 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
393 unsigned ShuffleKind, SelectionDAG &DAG);
395 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
396 /// shift amount, otherwise return -1.
397 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
400 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
401 /// specifies a splat of a single element that is suitable for input to
402 /// VSPLTB/VSPLTH/VSPLTW.
403 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
405 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
406 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
407 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
409 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
410 /// formed by using a vspltis[bhw] instruction of the specified element
411 /// size, return the constant being splatted. The ByteSize field indicates
412 /// the number of bytes of each element [124] -> [bhw].
413 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
415 /// If this is a qvaligni shuffle mask, return the shift
416 /// amount, otherwise return -1.
417 int isQVALIGNIShuffleMask(SDNode *N);
420 class PPCTargetLowering : public TargetLowering {
421 const PPCSubtarget &Subtarget;
424 explicit PPCTargetLowering(const PPCTargetMachine &TM,
425 const PPCSubtarget &STI);
427 /// getTargetNodeName() - This method returns the name of a target specific
429 const char *getTargetNodeName(unsigned Opcode) const override;
431 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
435 bool isCheapToSpeculateCttz() const override {
439 bool isCheapToSpeculateCtlz() const override {
443 /// getSetCCResultType - Return the ISD::SETCC ValueType
444 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
445 EVT VT) const override;
447 /// Return true if target always beneficiates from combining into FMA for a
448 /// given value type. This must typically return false on targets where FMA
449 /// takes more cycles to execute than FADD.
450 bool enableAggressiveFMAFusion(EVT VT) const override;
452 /// getPreIndexedAddressParts - returns true by value, base pointer and
453 /// offset pointer and addressing mode by reference if the node's address
454 /// can be legally represented as pre-indexed load / store address.
455 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
457 ISD::MemIndexedMode &AM,
458 SelectionDAG &DAG) const override;
460 /// SelectAddressRegReg - Given the specified addressed, check to see if it
461 /// can be represented as an indexed [r+r] operation. Returns false if it
462 /// can be more efficiently represented with [r+imm].
463 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
464 SelectionDAG &DAG) const;
466 /// SelectAddressRegImm - Returns true if the address N can be represented
467 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
468 /// is not better represented as reg+reg. If Aligned is true, only accept
469 /// displacements suitable for STD and friends, i.e. multiples of 4.
470 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
471 SelectionDAG &DAG, bool Aligned) const;
473 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
474 /// represented as an indexed [r+r] operation.
475 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
476 SelectionDAG &DAG) const;
478 Sched::Preference getSchedulingPreference(SDNode *N) const override;
480 /// LowerOperation - Provide custom lowering hooks for some operations.
482 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
484 /// ReplaceNodeResults - Replace the results of node with an illegal result
485 /// type with new values built out of custom code.
487 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
488 SelectionDAG &DAG) const override;
490 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
491 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
493 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
495 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
496 std::vector<SDNode *> *Created) const override;
498 unsigned getRegisterByName(const char* RegName, EVT VT,
499 SelectionDAG &DAG) const override;
501 void computeKnownBitsForTargetNode(const SDValue Op,
504 const SelectionDAG &DAG,
505 unsigned Depth = 0) const override;
507 unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
509 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
510 bool IsStore, bool IsLoad) const override;
511 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
512 bool IsStore, bool IsLoad) const override;
515 EmitInstrWithCustomInserter(MachineInstr *MI,
516 MachineBasicBlock *MBB) const override;
517 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
518 MachineBasicBlock *MBB,
520 unsigned BinOpcode) const;
521 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
522 MachineBasicBlock *MBB,
523 bool is8bit, unsigned Opcode) const;
525 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
526 MachineBasicBlock *MBB) const;
528 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
529 MachineBasicBlock *MBB) const;
531 ConstraintType getConstraintType(StringRef Constraint) const override;
533 /// Examine constraint string and operand type and determine a weight value.
534 /// The operand object must already have been set up with the operand type.
535 ConstraintWeight getSingleConstraintMatchWeight(
536 AsmOperandInfo &info, const char *constraint) const override;
538 std::pair<unsigned, const TargetRegisterClass *>
539 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
540 StringRef Constraint, MVT VT) const override;
542 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
543 /// function arguments in the caller parameter area. This is the actual
544 /// alignment, not its logarithm.
545 unsigned getByValTypeAlignment(Type *Ty,
546 const DataLayout &DL) const override;
548 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
549 /// vector. If it is invalid, don't add anything to Ops.
550 void LowerAsmOperandForConstraint(SDValue Op,
551 std::string &Constraint,
552 std::vector<SDValue> &Ops,
553 SelectionDAG &DAG) const override;
556 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
557 if (ConstraintCode == "es")
558 return InlineAsm::Constraint_es;
559 else if (ConstraintCode == "o")
560 return InlineAsm::Constraint_o;
561 else if (ConstraintCode == "Q")
562 return InlineAsm::Constraint_Q;
563 else if (ConstraintCode == "Z")
564 return InlineAsm::Constraint_Z;
565 else if (ConstraintCode == "Zy")
566 return InlineAsm::Constraint_Zy;
567 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
570 /// isLegalAddressingMode - Return true if the addressing mode represented
571 /// by AM is legal for this target, for a load/store of the specified type.
572 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
573 Type *Ty, unsigned AS) const override;
575 /// isLegalICmpImmediate - Return true if the specified immediate is legal
576 /// icmp immediate, that is the target has icmp instructions which can
577 /// compare a register against the immediate without having to materialize
578 /// the immediate into a register.
579 bool isLegalICmpImmediate(int64_t Imm) const override;
581 /// isLegalAddImmediate - Return true if the specified immediate is legal
582 /// add immediate, that is the target has add instructions which can
583 /// add a register and the immediate without having to materialize
584 /// the immediate into a register.
585 bool isLegalAddImmediate(int64_t Imm) const override;
587 /// isTruncateFree - Return true if it's free to truncate a value of
588 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
589 /// register X1 to i32 by referencing its sub-register R1.
590 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
591 bool isTruncateFree(EVT VT1, EVT VT2) const override;
593 bool isZExtFree(SDValue Val, EVT VT2) const override;
595 bool isFPExtFree(EVT VT) const override;
597 /// \brief Returns true if it is beneficial to convert a load of a constant
598 /// to just the constant itself.
599 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
600 Type *Ty) const override;
602 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
604 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
606 unsigned Intrinsic) const override;
608 /// getOptimalMemOpType - Returns the target specific optimal type for load
609 /// and store operations as a result of memset, memcpy, and memmove
610 /// lowering. If DstAlign is zero that means it's safe to destination
611 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
612 /// means there isn't a need to check it against alignment requirement,
613 /// probably because the source does not need to be loaded. If 'IsMemset' is
614 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
615 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
616 /// source is constant so it does not need to be loaded.
617 /// It returns EVT::Other if the type should be determined using generic
618 /// target-independent logic.
620 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
621 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
622 MachineFunction &MF) const override;
624 /// Is unaligned memory access allowed for the given type, and is it fast
625 /// relative to software emulation.
626 bool allowsMisalignedMemoryAccesses(EVT VT,
629 bool *Fast = nullptr) const override;
631 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
632 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
633 /// expanded to FMAs when this method returns true, otherwise fmuladd is
634 /// expanded to fmul + fadd.
635 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
637 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
639 // Should we expand the build vector with shuffles?
641 shouldExpandBuildVectorWithShuffles(EVT VT,
642 unsigned DefinedValues) const override;
644 /// createFastISel - This method returns a target-specific FastISel object,
645 /// or null if the target does not support "fast" instruction selection.
646 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
647 const TargetLibraryInfo *LibInfo) const override;
649 /// \brief Returns true if an argument of type Ty needs to be passed in a
650 /// contiguous block of registers in calling convention CallConv.
651 bool functionArgumentNeedsConsecutiveRegisters(
652 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
653 // We support any array type as "consecutive" block in the parameter
654 // save area. The element type defines the alignment requirement and
655 // whether the argument should go in GPRs, FPRs, or VRs if available.
657 // Note that clang uses this capability both to implement the ELFv2
658 // homogeneous float/vector aggregate ABI, and to avoid having to use
659 // "byval" when passing aggregates that might fully fit in registers.
660 return Ty->isArrayTy();
663 /// If a physical register, this returns the register that receives the
664 /// exception address on entry to an EH pad.
666 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
668 /// If a physical register, this returns the register that receives the
669 /// exception typeid on entry to a landing pad.
671 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
674 struct ReuseLoadInfo {
678 MachinePointerInfo MPI;
682 const MDNode *Ranges;
684 ReuseLoadInfo() : IsInvariant(false), Alignment(0), Ranges(nullptr) {}
687 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
689 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
690 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
691 SelectionDAG &DAG) const;
693 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
694 SelectionDAG &DAG, SDLoc dl) const;
695 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
697 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
700 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
701 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
704 IsEligibleForTailCallOptimization(SDValue Callee,
705 CallingConv::ID CalleeCC,
707 const SmallVectorImpl<ISD::InputArg> &Ins,
708 SelectionDAG& DAG) const;
710 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
718 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
719 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
720 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
721 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
722 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
723 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
724 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
725 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
726 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
727 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
728 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
729 const PPCSubtarget &Subtarget) const;
730 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
731 const PPCSubtarget &Subtarget) const;
732 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
733 const PPCSubtarget &Subtarget) const;
734 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
735 const PPCSubtarget &Subtarget) const;
736 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG,
737 const PPCSubtarget &Subtarget) const;
738 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
739 const PPCSubtarget &Subtarget) const;
740 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
741 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
742 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
743 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
744 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
745 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
746 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
747 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
748 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
749 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
750 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
751 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
752 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
753 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
754 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
755 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
756 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
758 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
759 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
761 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
762 CallingConv::ID CallConv, bool isVarArg,
763 const SmallVectorImpl<ISD::InputArg> &Ins,
764 SDLoc dl, SelectionDAG &DAG,
765 SmallVectorImpl<SDValue> &InVals) const;
766 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
767 bool isVarArg, bool IsPatchPoint, bool hasNest,
769 SmallVector<std::pair<unsigned, SDValue>, 8>
771 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
773 int SPDiff, unsigned NumBytes,
774 const SmallVectorImpl<ISD::InputArg> &Ins,
775 SmallVectorImpl<SDValue> &InVals,
776 ImmutableCallSite *CS) const;
779 LowerFormalArguments(SDValue Chain,
780 CallingConv::ID CallConv, bool isVarArg,
781 const SmallVectorImpl<ISD::InputArg> &Ins,
782 SDLoc dl, SelectionDAG &DAG,
783 SmallVectorImpl<SDValue> &InVals) const override;
786 LowerCall(TargetLowering::CallLoweringInfo &CLI,
787 SmallVectorImpl<SDValue> &InVals) const override;
790 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
792 const SmallVectorImpl<ISD::OutputArg> &Outs,
793 LLVMContext &Context) const override;
796 LowerReturn(SDValue Chain,
797 CallingConv::ID CallConv, bool isVarArg,
798 const SmallVectorImpl<ISD::OutputArg> &Outs,
799 const SmallVectorImpl<SDValue> &OutVals,
800 SDLoc dl, SelectionDAG &DAG) const override;
803 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
804 SDValue ArgVal, SDLoc dl) const;
807 LowerFormalArguments_Darwin(SDValue Chain,
808 CallingConv::ID CallConv, bool isVarArg,
809 const SmallVectorImpl<ISD::InputArg> &Ins,
810 SDLoc dl, SelectionDAG &DAG,
811 SmallVectorImpl<SDValue> &InVals) const;
813 LowerFormalArguments_64SVR4(SDValue Chain,
814 CallingConv::ID CallConv, bool isVarArg,
815 const SmallVectorImpl<ISD::InputArg> &Ins,
816 SDLoc dl, SelectionDAG &DAG,
817 SmallVectorImpl<SDValue> &InVals) const;
819 LowerFormalArguments_32SVR4(SDValue Chain,
820 CallingConv::ID CallConv, bool isVarArg,
821 const SmallVectorImpl<ISD::InputArg> &Ins,
822 SDLoc dl, SelectionDAG &DAG,
823 SmallVectorImpl<SDValue> &InVals) const;
826 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
827 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
828 SelectionDAG &DAG, SDLoc dl) const;
831 LowerCall_Darwin(SDValue Chain, SDValue Callee,
832 CallingConv::ID CallConv,
833 bool isVarArg, bool isTailCall, bool IsPatchPoint,
834 const SmallVectorImpl<ISD::OutputArg> &Outs,
835 const SmallVectorImpl<SDValue> &OutVals,
836 const SmallVectorImpl<ISD::InputArg> &Ins,
837 SDLoc dl, SelectionDAG &DAG,
838 SmallVectorImpl<SDValue> &InVals,
839 ImmutableCallSite *CS) const;
841 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
842 CallingConv::ID CallConv,
843 bool isVarArg, bool isTailCall, bool IsPatchPoint,
844 const SmallVectorImpl<ISD::OutputArg> &Outs,
845 const SmallVectorImpl<SDValue> &OutVals,
846 const SmallVectorImpl<ISD::InputArg> &Ins,
847 SDLoc dl, SelectionDAG &DAG,
848 SmallVectorImpl<SDValue> &InVals,
849 ImmutableCallSite *CS) const;
851 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
852 bool isVarArg, bool isTailCall, bool IsPatchPoint,
853 const SmallVectorImpl<ISD::OutputArg> &Outs,
854 const SmallVectorImpl<SDValue> &OutVals,
855 const SmallVectorImpl<ISD::InputArg> &Ins,
856 SDLoc dl, SelectionDAG &DAG,
857 SmallVectorImpl<SDValue> &InVals,
858 ImmutableCallSite *CS) const;
860 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
861 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
863 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
864 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
865 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
867 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
868 unsigned &RefinementSteps,
869 bool &UseOneConstNR) const override;
870 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
871 unsigned &RefinementSteps) const override;
872 unsigned combineRepeatedFPDivisors() const override;
874 CCAssignFn *useFastISelCCs(unsigned Flag) const;
878 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
879 const TargetLibraryInfo *LibInfo);
882 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
883 CCValAssign::LocInfo &LocInfo,
884 ISD::ArgFlagsTy &ArgFlags,
887 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
889 CCValAssign::LocInfo &LocInfo,
890 ISD::ArgFlagsTy &ArgFlags,
893 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
895 CCValAssign::LocInfo &LocInfo,
896 ISD::ArgFlagsTy &ArgFlags,
900 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H