1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/DerivedTypes.h"
40 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
41 CCValAssign::LocInfo &LocInfo,
42 ISD::ArgFlagsTy &ArgFlags,
44 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
46 CCValAssign::LocInfo &LocInfo,
47 ISD::ArgFlagsTy &ArgFlags,
49 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
55 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
56 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
59 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
60 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // Set up the register classes.
69 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
70 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
71 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
73 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
74 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
75 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
77 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
79 // PowerPC has pre-inc load and store's.
80 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
81 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
82 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
83 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
84 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
85 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
86 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
87 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
88 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
89 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
91 // This is used in the ppcf128->int sequence. Note it has different semantics
92 // from FP_ROUND: that rounds to nearest, this rounds to zero.
93 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
95 // PowerPC has no SREM/UREM instructions
96 setOperationAction(ISD::SREM, MVT::i32, Expand);
97 setOperationAction(ISD::UREM, MVT::i32, Expand);
98 setOperationAction(ISD::SREM, MVT::i64, Expand);
99 setOperationAction(ISD::UREM, MVT::i64, Expand);
101 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
102 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
103 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
104 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
105 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
106 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
107 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
108 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
109 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
111 // We don't support sin/cos/sqrt/fmod/pow
112 setOperationAction(ISD::FSIN , MVT::f64, Expand);
113 setOperationAction(ISD::FCOS , MVT::f64, Expand);
114 setOperationAction(ISD::FREM , MVT::f64, Expand);
115 setOperationAction(ISD::FPOW , MVT::f64, Expand);
116 setOperationAction(ISD::FSIN , MVT::f32, Expand);
117 setOperationAction(ISD::FCOS , MVT::f32, Expand);
118 setOperationAction(ISD::FREM , MVT::f32, Expand);
119 setOperationAction(ISD::FPOW , MVT::f32, Expand);
121 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
123 // If we're enabling GP optimizations, use hardware square root
124 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
125 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
126 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
129 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
130 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
132 // PowerPC does not have BSWAP, CTPOP or CTTZ
133 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
134 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
135 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
136 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
137 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
138 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
140 // PowerPC does not have ROTR
141 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
142 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
144 // PowerPC does not have Select
145 setOperationAction(ISD::SELECT, MVT::i32, Expand);
146 setOperationAction(ISD::SELECT, MVT::i64, Expand);
147 setOperationAction(ISD::SELECT, MVT::f32, Expand);
148 setOperationAction(ISD::SELECT, MVT::f64, Expand);
150 // PowerPC wants to turn select_cc of FP into fsel when possible.
151 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
152 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
154 // PowerPC wants to optimize integer setcc a bit
155 setOperationAction(ISD::SETCC, MVT::i32, Custom);
157 // PowerPC does not have BRCOND which requires SetCC
158 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
160 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
162 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
163 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
165 // PowerPC does not have [U|S]INT_TO_FP
166 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
167 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
169 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
170 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
171 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
172 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
174 // We cannot sextinreg(i1). Expand to shifts.
175 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
177 // Support label based line numbers.
178 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
179 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
181 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
182 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
183 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
184 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
187 // We want to legalize GlobalAddress and ConstantPool nodes into the
188 // appropriate instructions to materialize the address.
189 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
190 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
191 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
192 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
193 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
194 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
195 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
196 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
198 // RET must be custom lowered, to meet ABI requirements.
199 setOperationAction(ISD::RET , MVT::Other, Custom);
202 setOperationAction(ISD::TRAP, MVT::Other, Legal);
204 // TRAMPOLINE is custom lowered.
205 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
207 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
208 setOperationAction(ISD::VASTART , MVT::Other, Custom);
210 // VAARG is custom lowered with the SVR4 ABI
211 if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI())
212 setOperationAction(ISD::VAARG, MVT::Other, Custom);
214 setOperationAction(ISD::VAARG, MVT::Other, Expand);
216 // Use the default implementation.
217 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
218 setOperationAction(ISD::VAEND , MVT::Other, Expand);
219 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
220 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
221 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
222 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
224 // We want to custom lower some of our intrinsics.
225 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
227 // Comparisons that require checking two conditions.
228 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
229 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
230 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
231 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
232 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
233 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
234 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
241 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
242 // They also have instructions for converting between i64 and fp.
243 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
244 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
245 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
246 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
247 // This is just the low 32 bits of a (signed) fp->i64 conversion.
248 // We cannot do this with Promote because i64 is not a legal type.
249 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
251 // FIXME: disable this lowered code. This generates 64-bit register values,
252 // and we don't model the fact that the top part is clobbered by calls. We
253 // need to flag these together so that the value isn't live across a call.
254 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
256 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
260 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
261 // 64-bit PowerPC implementations can support i64 types directly
262 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
263 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
264 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
265 // 64-bit PowerPC wants to expand i128 shifts itself.
266 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
267 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
268 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
270 // 32-bit PowerPC wants to expand i64 shifts itself.
271 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
272 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
273 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
276 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
277 // First set operation action for all vector types to expand. Then we
278 // will selectively turn on ones that can be effectively codegen'd.
279 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
280 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
281 MVT VT = (MVT::SimpleValueType)i;
283 // add/sub are legal for all supported vector VT's.
284 setOperationAction(ISD::ADD , VT, Legal);
285 setOperationAction(ISD::SUB , VT, Legal);
287 // We promote all shuffles to v16i8.
288 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
289 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
291 // We promote all non-typed operations to v4i32.
292 setOperationAction(ISD::AND , VT, Promote);
293 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
294 setOperationAction(ISD::OR , VT, Promote);
295 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
296 setOperationAction(ISD::XOR , VT, Promote);
297 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
298 setOperationAction(ISD::LOAD , VT, Promote);
299 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
300 setOperationAction(ISD::SELECT, VT, Promote);
301 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
302 setOperationAction(ISD::STORE, VT, Promote);
303 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
305 // No other operations are legal.
306 setOperationAction(ISD::MUL , VT, Expand);
307 setOperationAction(ISD::SDIV, VT, Expand);
308 setOperationAction(ISD::SREM, VT, Expand);
309 setOperationAction(ISD::UDIV, VT, Expand);
310 setOperationAction(ISD::UREM, VT, Expand);
311 setOperationAction(ISD::FDIV, VT, Expand);
312 setOperationAction(ISD::FNEG, VT, Expand);
313 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
314 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
315 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
316 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
317 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
318 setOperationAction(ISD::UDIVREM, VT, Expand);
319 setOperationAction(ISD::SDIVREM, VT, Expand);
320 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
321 setOperationAction(ISD::FPOW, VT, Expand);
322 setOperationAction(ISD::CTPOP, VT, Expand);
323 setOperationAction(ISD::CTLZ, VT, Expand);
324 setOperationAction(ISD::CTTZ, VT, Expand);
327 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
328 // with merges, splats, etc.
329 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
331 setOperationAction(ISD::AND , MVT::v4i32, Legal);
332 setOperationAction(ISD::OR , MVT::v4i32, Legal);
333 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
334 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
335 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
336 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
338 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
339 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
340 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
341 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
343 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
344 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
345 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
346 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
348 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
349 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
351 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
352 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
353 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
354 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
357 setShiftAmountType(MVT::i32);
358 setBooleanContents(ZeroOrOneBooleanContent);
360 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
361 setStackPointerRegisterToSaveRestore(PPC::X1);
362 setExceptionPointerRegister(PPC::X3);
363 setExceptionSelectorRegister(PPC::X4);
365 setStackPointerRegisterToSaveRestore(PPC::R1);
366 setExceptionPointerRegister(PPC::R3);
367 setExceptionSelectorRegister(PPC::R4);
370 // We have target-specific dag combine patterns for the following nodes:
371 setTargetDAGCombine(ISD::SINT_TO_FP);
372 setTargetDAGCombine(ISD::STORE);
373 setTargetDAGCombine(ISD::BR_CC);
374 setTargetDAGCombine(ISD::BSWAP);
376 // Darwin long double math library functions have $LDBL128 appended.
377 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
378 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
379 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
380 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
381 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
382 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
383 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
384 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
385 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
386 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
387 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
390 computeRegisterProperties();
393 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
394 /// function arguments in the caller parameter area.
395 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
396 TargetMachine &TM = getTargetMachine();
397 // Darwin passes everything on 4 byte boundary.
398 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
404 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
407 case PPCISD::FSEL: return "PPCISD::FSEL";
408 case PPCISD::FCFID: return "PPCISD::FCFID";
409 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
410 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
411 case PPCISD::STFIWX: return "PPCISD::STFIWX";
412 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
413 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
414 case PPCISD::VPERM: return "PPCISD::VPERM";
415 case PPCISD::Hi: return "PPCISD::Hi";
416 case PPCISD::Lo: return "PPCISD::Lo";
417 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
418 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
419 case PPCISD::SRL: return "PPCISD::SRL";
420 case PPCISD::SRA: return "PPCISD::SRA";
421 case PPCISD::SHL: return "PPCISD::SHL";
422 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
423 case PPCISD::STD_32: return "PPCISD::STD_32";
424 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
425 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
426 case PPCISD::MTCTR: return "PPCISD::MTCTR";
427 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
428 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
429 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
430 case PPCISD::MFCR: return "PPCISD::MFCR";
431 case PPCISD::VCMP: return "PPCISD::VCMP";
432 case PPCISD::VCMPo: return "PPCISD::VCMPo";
433 case PPCISD::LBRX: return "PPCISD::LBRX";
434 case PPCISD::STBRX: return "PPCISD::STBRX";
435 case PPCISD::LARX: return "PPCISD::LARX";
436 case PPCISD::STCX: return "PPCISD::STCX";
437 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
438 case PPCISD::MFFS: return "PPCISD::MFFS";
439 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
440 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
441 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
442 case PPCISD::MTFSF: return "PPCISD::MTFSF";
443 case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
444 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
448 MVT PPCTargetLowering::getSetCCResultType(MVT VT) const {
452 /// getFunctionAlignment - Return the Log2 alignment of this function.
453 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
454 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
455 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
460 //===----------------------------------------------------------------------===//
461 // Node matching predicates, for use by the tblgen matching code.
462 //===----------------------------------------------------------------------===//
464 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
465 static bool isFloatingPointZero(SDValue Op) {
466 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
467 return CFP->getValueAPF().isZero();
468 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
469 // Maybe this has already been legalized into the constant pool?
470 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
471 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
472 return CFP->getValueAPF().isZero();
477 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
478 /// true if Op is undef or if it matches the specified value.
479 static bool isConstantOrUndef(int Op, int Val) {
480 return Op < 0 || Op == Val;
483 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
484 /// VPKUHUM instruction.
485 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
487 for (unsigned i = 0; i != 16; ++i)
488 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
491 for (unsigned i = 0; i != 8; ++i)
492 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
493 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
499 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
500 /// VPKUWUM instruction.
501 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
503 for (unsigned i = 0; i != 16; i += 2)
504 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
505 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
508 for (unsigned i = 0; i != 8; i += 2)
509 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
510 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
511 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
512 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
518 /// isVMerge - Common function, used to match vmrg* shuffles.
520 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
521 unsigned LHSStart, unsigned RHSStart) {
522 assert(N->getValueType(0) == MVT::v16i8 &&
523 "PPC only supports shuffles by bytes!");
524 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
525 "Unsupported merge size!");
527 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
528 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
529 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
530 LHSStart+j+i*UnitSize) ||
531 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
532 RHSStart+j+i*UnitSize))
538 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
539 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
540 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
543 return isVMerge(N, UnitSize, 8, 24);
544 return isVMerge(N, UnitSize, 8, 8);
547 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
548 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
549 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
552 return isVMerge(N, UnitSize, 0, 16);
553 return isVMerge(N, UnitSize, 0, 0);
557 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
558 /// amount, otherwise return -1.
559 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
560 assert(N->getValueType(0) == MVT::v16i8 &&
561 "PPC only supports shuffles by bytes!");
563 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
565 // Find the first non-undef value in the shuffle mask.
567 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
570 if (i == 16) return -1; // all undef.
572 // Otherwise, check to see if the rest of the elements are consecutively
573 // numbered from this value.
574 unsigned ShiftAmt = SVOp->getMaskElt(i);
575 if (ShiftAmt < i) return -1;
579 // Check the rest of the elements to see if they are consecutive.
580 for (++i; i != 16; ++i)
581 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
584 // Check the rest of the elements to see if they are consecutive.
585 for (++i; i != 16; ++i)
586 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
592 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
593 /// specifies a splat of a single element that is suitable for input to
594 /// VSPLTB/VSPLTH/VSPLTW.
595 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
596 assert(N->getValueType(0) == MVT::v16i8 &&
597 (EltSize == 1 || EltSize == 2 || EltSize == 4));
599 // This is a splat operation if each element of the permute is the same, and
600 // if the value doesn't reference the second vector.
601 unsigned ElementBase = N->getMaskElt(0);
603 // FIXME: Handle UNDEF elements too!
604 if (ElementBase >= 16)
607 // Check that the indices are consecutive, in the case of a multi-byte element
608 // splatted with a v16i8 mask.
609 for (unsigned i = 1; i != EltSize; ++i)
610 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
613 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
614 if (N->getMaskElt(i) < 0) continue;
615 for (unsigned j = 0; j != EltSize; ++j)
616 if (N->getMaskElt(i+j) != N->getMaskElt(j))
622 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
624 bool PPC::isAllNegativeZeroVector(SDNode *N) {
625 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
627 APInt APVal, APUndef;
631 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32))
632 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
633 return CFP->getValueAPF().isNegZero();
638 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
639 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
640 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
641 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
642 assert(isSplatShuffleMask(SVOp, EltSize));
643 return SVOp->getMaskElt(0) / EltSize;
646 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
647 /// by using a vspltis[bhw] instruction of the specified element size, return
648 /// the constant being splatted. The ByteSize field indicates the number of
649 /// bytes of each element [124] -> [bhw].
650 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
653 // If ByteSize of the splat is bigger than the element size of the
654 // build_vector, then we have a case where we are checking for a splat where
655 // multiple elements of the buildvector are folded together into a single
656 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
657 unsigned EltSize = 16/N->getNumOperands();
658 if (EltSize < ByteSize) {
659 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
660 SDValue UniquedVals[4];
661 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
663 // See if all of the elements in the buildvector agree across.
664 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
665 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
666 // If the element isn't a constant, bail fully out.
667 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
670 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
671 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
672 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
673 return SDValue(); // no match.
676 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
677 // either constant or undef values that are identical for each chunk. See
678 // if these chunks can form into a larger vspltis*.
680 // Check to see if all of the leading entries are either 0 or -1. If
681 // neither, then this won't fit into the immediate field.
682 bool LeadingZero = true;
683 bool LeadingOnes = true;
684 for (unsigned i = 0; i != Multiple-1; ++i) {
685 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
687 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
688 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
690 // Finally, check the least significant entry.
692 if (UniquedVals[Multiple-1].getNode() == 0)
693 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
694 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
696 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
699 if (UniquedVals[Multiple-1].getNode() == 0)
700 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
701 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
702 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
703 return DAG.getTargetConstant(Val, MVT::i32);
709 // Check to see if this buildvec has a single non-undef value in its elements.
710 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
711 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
712 if (OpVal.getNode() == 0)
713 OpVal = N->getOperand(i);
714 else if (OpVal != N->getOperand(i))
718 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
720 unsigned ValSizeInBytes = EltSize;
722 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
723 Value = CN->getZExtValue();
724 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
725 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
726 Value = FloatToBits(CN->getValueAPF().convertToFloat());
729 // If the splat value is larger than the element value, then we can never do
730 // this splat. The only case that we could fit the replicated bits into our
731 // immediate field for would be zero, and we prefer to use vxor for it.
732 if (ValSizeInBytes < ByteSize) return SDValue();
734 // If the element value is larger than the splat value, cut it in half and
735 // check to see if the two halves are equal. Continue doing this until we
736 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
737 while (ValSizeInBytes > ByteSize) {
738 ValSizeInBytes >>= 1;
740 // If the top half equals the bottom half, we're still ok.
741 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
742 (Value & ((1 << (8*ValSizeInBytes))-1)))
746 // Properly sign extend the value.
747 int ShAmt = (4-ByteSize)*8;
748 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
750 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
751 if (MaskVal == 0) return SDValue();
753 // Finally, if this value fits in a 5 bit sext field, return it
754 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
755 return DAG.getTargetConstant(MaskVal, MVT::i32);
759 //===----------------------------------------------------------------------===//
760 // Addressing Mode Selection
761 //===----------------------------------------------------------------------===//
763 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
764 /// or 64-bit immediate, and if the value can be accurately represented as a
765 /// sign extension from a 16-bit value. If so, this returns true and the
767 static bool isIntS16Immediate(SDNode *N, short &Imm) {
768 if (N->getOpcode() != ISD::Constant)
771 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
772 if (N->getValueType(0) == MVT::i32)
773 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
775 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
777 static bool isIntS16Immediate(SDValue Op, short &Imm) {
778 return isIntS16Immediate(Op.getNode(), Imm);
782 /// SelectAddressRegReg - Given the specified addressed, check to see if it
783 /// can be represented as an indexed [r+r] operation. Returns false if it
784 /// can be more efficiently represented with [r+imm].
785 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
787 SelectionDAG &DAG) const {
789 if (N.getOpcode() == ISD::ADD) {
790 if (isIntS16Immediate(N.getOperand(1), imm))
792 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
795 Base = N.getOperand(0);
796 Index = N.getOperand(1);
798 } else if (N.getOpcode() == ISD::OR) {
799 if (isIntS16Immediate(N.getOperand(1), imm))
800 return false; // r+i can fold it if we can.
802 // If this is an or of disjoint bitfields, we can codegen this as an add
803 // (for better address arithmetic) if the LHS and RHS of the OR are provably
805 APInt LHSKnownZero, LHSKnownOne;
806 APInt RHSKnownZero, RHSKnownOne;
807 DAG.ComputeMaskedBits(N.getOperand(0),
808 APInt::getAllOnesValue(N.getOperand(0)
809 .getValueSizeInBits()),
810 LHSKnownZero, LHSKnownOne);
812 if (LHSKnownZero.getBoolValue()) {
813 DAG.ComputeMaskedBits(N.getOperand(1),
814 APInt::getAllOnesValue(N.getOperand(1)
815 .getValueSizeInBits()),
816 RHSKnownZero, RHSKnownOne);
817 // If all of the bits are known zero on the LHS or RHS, the add won't
819 if (~(LHSKnownZero | RHSKnownZero) == 0) {
820 Base = N.getOperand(0);
821 Index = N.getOperand(1);
830 /// Returns true if the address N can be represented by a base register plus
831 /// a signed 16-bit displacement [r+imm], and if it is not better
832 /// represented as reg+reg.
833 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
835 SelectionDAG &DAG) const {
836 // FIXME dl should come from parent load or store, not from address
837 DebugLoc dl = N.getDebugLoc();
838 // If this can be more profitably realized as r+r, fail.
839 if (SelectAddressRegReg(N, Disp, Base, DAG))
842 if (N.getOpcode() == ISD::ADD) {
844 if (isIntS16Immediate(N.getOperand(1), imm)) {
845 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
846 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
847 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
849 Base = N.getOperand(0);
851 return true; // [r+i]
852 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
853 // Match LOAD (ADD (X, Lo(G))).
854 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
855 && "Cannot handle constant offsets yet!");
856 Disp = N.getOperand(1).getOperand(0); // The global address.
857 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
858 Disp.getOpcode() == ISD::TargetConstantPool ||
859 Disp.getOpcode() == ISD::TargetJumpTable);
860 Base = N.getOperand(0);
861 return true; // [&g+r]
863 } else if (N.getOpcode() == ISD::OR) {
865 if (isIntS16Immediate(N.getOperand(1), imm)) {
866 // If this is an or of disjoint bitfields, we can codegen this as an add
867 // (for better address arithmetic) if the LHS and RHS of the OR are
868 // provably disjoint.
869 APInt LHSKnownZero, LHSKnownOne;
870 DAG.ComputeMaskedBits(N.getOperand(0),
871 APInt::getAllOnesValue(N.getOperand(0)
872 .getValueSizeInBits()),
873 LHSKnownZero, LHSKnownOne);
875 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
876 // If all of the bits are known zero on the LHS or RHS, the add won't
878 Base = N.getOperand(0);
879 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
883 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
884 // Loading from a constant address.
886 // If this address fits entirely in a 16-bit sext immediate field, codegen
889 if (isIntS16Immediate(CN, Imm)) {
890 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
891 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
895 // Handle 32-bit sext immediates with LIS + addr mode.
896 if (CN->getValueType(0) == MVT::i32 ||
897 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
898 int Addr = (int)CN->getZExtValue();
900 // Otherwise, break this down into an LIS + disp.
901 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
903 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
904 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
905 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
910 Disp = DAG.getTargetConstant(0, getPointerTy());
911 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
912 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
915 return true; // [r+0]
918 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
919 /// represented as an indexed [r+r] operation.
920 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
922 SelectionDAG &DAG) const {
923 // Check to see if we can easily represent this as an [r+r] address. This
924 // will fail if it thinks that the address is more profitably represented as
925 // reg+imm, e.g. where imm = 0.
926 if (SelectAddressRegReg(N, Base, Index, DAG))
929 // If the operand is an addition, always emit this as [r+r], since this is
930 // better (for code size, and execution, as the memop does the add for free)
931 // than emitting an explicit add.
932 if (N.getOpcode() == ISD::ADD) {
933 Base = N.getOperand(0);
934 Index = N.getOperand(1);
938 // Otherwise, do it the hard way, using R0 as the base register.
939 Base = DAG.getRegister(PPC::R0, N.getValueType());
944 /// SelectAddressRegImmShift - Returns true if the address N can be
945 /// represented by a base register plus a signed 14-bit displacement
946 /// [r+imm*4]. Suitable for use by STD and friends.
947 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
949 SelectionDAG &DAG) const {
950 // FIXME dl should come from the parent load or store, not the address
951 DebugLoc dl = N.getDebugLoc();
952 // If this can be more profitably realized as r+r, fail.
953 if (SelectAddressRegReg(N, Disp, Base, DAG))
956 if (N.getOpcode() == ISD::ADD) {
958 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
959 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
960 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
961 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
963 Base = N.getOperand(0);
965 return true; // [r+i]
966 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
967 // Match LOAD (ADD (X, Lo(G))).
968 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
969 && "Cannot handle constant offsets yet!");
970 Disp = N.getOperand(1).getOperand(0); // The global address.
971 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
972 Disp.getOpcode() == ISD::TargetConstantPool ||
973 Disp.getOpcode() == ISD::TargetJumpTable);
974 Base = N.getOperand(0);
975 return true; // [&g+r]
977 } else if (N.getOpcode() == ISD::OR) {
979 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
980 // If this is an or of disjoint bitfields, we can codegen this as an add
981 // (for better address arithmetic) if the LHS and RHS of the OR are
982 // provably disjoint.
983 APInt LHSKnownZero, LHSKnownOne;
984 DAG.ComputeMaskedBits(N.getOperand(0),
985 APInt::getAllOnesValue(N.getOperand(0)
986 .getValueSizeInBits()),
987 LHSKnownZero, LHSKnownOne);
988 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
989 // If all of the bits are known zero on the LHS or RHS, the add won't
991 Base = N.getOperand(0);
992 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
996 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
997 // Loading from a constant address. Verify low two bits are clear.
998 if ((CN->getZExtValue() & 3) == 0) {
999 // If this address fits entirely in a 14-bit sext immediate field, codegen
1002 if (isIntS16Immediate(CN, Imm)) {
1003 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1004 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1008 // Fold the low-part of 32-bit absolute addresses into addr mode.
1009 if (CN->getValueType(0) == MVT::i32 ||
1010 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1011 int Addr = (int)CN->getZExtValue();
1013 // Otherwise, break this down into an LIS + disp.
1014 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1015 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1016 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1017 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0);
1023 Disp = DAG.getTargetConstant(0, getPointerTy());
1024 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1025 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1028 return true; // [r+0]
1032 /// getPreIndexedAddressParts - returns true by value, base pointer and
1033 /// offset pointer and addressing mode by reference if the node's address
1034 /// can be legally represented as pre-indexed load / store address.
1035 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1037 ISD::MemIndexedMode &AM,
1038 SelectionDAG &DAG) const {
1039 // Disabled by default for now.
1040 if (!EnablePPCPreinc) return false;
1044 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1045 Ptr = LD->getBasePtr();
1046 VT = LD->getMemoryVT();
1048 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1050 Ptr = ST->getBasePtr();
1051 VT = ST->getMemoryVT();
1055 // PowerPC doesn't have preinc load/store instructions for vectors.
1059 // TODO: Check reg+reg first.
1061 // LDU/STU use reg+imm*4, others use reg+imm.
1062 if (VT != MVT::i64) {
1064 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1068 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1072 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1073 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1074 // sext i32 to i64 when addr mode is r+i.
1075 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1076 LD->getExtensionType() == ISD::SEXTLOAD &&
1077 isa<ConstantSDNode>(Offset))
1085 //===----------------------------------------------------------------------===//
1086 // LowerOperation implementation
1087 //===----------------------------------------------------------------------===//
1089 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1090 SelectionDAG &DAG) {
1091 MVT PtrVT = Op.getValueType();
1092 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1093 Constant *C = CP->getConstVal();
1094 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1095 SDValue Zero = DAG.getConstant(0, PtrVT);
1096 // FIXME there isn't really any debug info here
1097 DebugLoc dl = Op.getDebugLoc();
1099 const TargetMachine &TM = DAG.getTarget();
1101 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
1102 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
1104 // If this is a non-darwin platform, we don't support non-static relo models
1106 if (TM.getRelocationModel() == Reloc::Static ||
1107 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1108 // Generate non-pic code that has direct accesses to the constant pool.
1109 // The address of the global is just (hi(&g)+lo(&g)).
1110 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1113 if (TM.getRelocationModel() == Reloc::PIC_) {
1114 // With PIC, the first instruction is actually "GR+hi(&G)".
1115 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1116 DAG.getNode(PPCISD::GlobalBaseReg,
1117 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1120 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1124 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1125 MVT PtrVT = Op.getValueType();
1126 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1127 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1128 SDValue Zero = DAG.getConstant(0, PtrVT);
1129 // FIXME there isn't really any debug loc here
1130 DebugLoc dl = Op.getDebugLoc();
1132 const TargetMachine &TM = DAG.getTarget();
1134 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
1135 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
1137 // If this is a non-darwin platform, we don't support non-static relo models
1139 if (TM.getRelocationModel() == Reloc::Static ||
1140 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1141 // Generate non-pic code that has direct accesses to the constant pool.
1142 // The address of the global is just (hi(&g)+lo(&g)).
1143 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1146 if (TM.getRelocationModel() == Reloc::PIC_) {
1147 // With PIC, the first instruction is actually "GR+hi(&G)".
1148 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1149 DAG.getNode(PPCISD::GlobalBaseReg,
1150 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1153 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1157 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1158 SelectionDAG &DAG) {
1159 assert(0 && "TLS not implemented for PPC.");
1160 return SDValue(); // Not reached
1163 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1164 SelectionDAG &DAG) {
1165 MVT PtrVT = Op.getValueType();
1166 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1167 GlobalValue *GV = GSDN->getGlobal();
1168 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1169 SDValue Zero = DAG.getConstant(0, PtrVT);
1170 // FIXME there isn't really any debug info here
1171 DebugLoc dl = GSDN->getDebugLoc();
1173 const TargetMachine &TM = DAG.getTarget();
1175 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1176 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1178 // If this is a non-darwin platform, we don't support non-static relo models
1180 if (TM.getRelocationModel() == Reloc::Static ||
1181 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1182 // Generate non-pic code that has direct accesses to globals.
1183 // The address of the global is just (hi(&g)+lo(&g)).
1184 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1187 if (TM.getRelocationModel() == Reloc::PIC_) {
1188 // With PIC, the first instruction is actually "GR+hi(&G)".
1189 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1190 DAG.getNode(PPCISD::GlobalBaseReg,
1191 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1194 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1196 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1199 // If the global is weak or external, we have to go through the lazy
1201 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
1204 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1205 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1206 DebugLoc dl = Op.getDebugLoc();
1208 // If we're comparing for equality to zero, expose the fact that this is
1209 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1210 // fold the new nodes.
1211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1212 if (C->isNullValue() && CC == ISD::SETEQ) {
1213 MVT VT = Op.getOperand(0).getValueType();
1214 SDValue Zext = Op.getOperand(0);
1215 if (VT.bitsLT(MVT::i32)) {
1217 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1219 unsigned Log2b = Log2_32(VT.getSizeInBits());
1220 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1221 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1222 DAG.getConstant(Log2b, MVT::i32));
1223 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1225 // Leave comparisons against 0 and -1 alone for now, since they're usually
1226 // optimized. FIXME: revisit this when we can custom lower all setcc
1228 if (C->isAllOnesValue() || C->isNullValue())
1232 // If we have an integer seteq/setne, turn it into a compare against zero
1233 // by xor'ing the rhs with the lhs, which is faster than setting a
1234 // condition register, reading it back out, and masking the correct bit. The
1235 // normal approach here uses sub to do this instead of xor. Using xor exposes
1236 // the result to other bit-twiddling opportunities.
1237 MVT LHSVT = Op.getOperand(0).getValueType();
1238 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1239 MVT VT = Op.getValueType();
1240 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1242 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1247 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1248 int VarArgsFrameIndex,
1249 int VarArgsStackOffset,
1250 unsigned VarArgsNumGPR,
1251 unsigned VarArgsNumFPR,
1252 const PPCSubtarget &Subtarget) {
1254 assert(0 && "VAARG not yet implemented for the SVR4 ABI!");
1255 return SDValue(); // Not reached
1258 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1259 SDValue Chain = Op.getOperand(0);
1260 SDValue Trmp = Op.getOperand(1); // trampoline
1261 SDValue FPtr = Op.getOperand(2); // nested function
1262 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1263 DebugLoc dl = Op.getDebugLoc();
1265 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1266 bool isPPC64 = (PtrVT == MVT::i64);
1267 const Type *IntPtrTy =
1268 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType();
1270 TargetLowering::ArgListTy Args;
1271 TargetLowering::ArgListEntry Entry;
1273 Entry.Ty = IntPtrTy;
1274 Entry.Node = Trmp; Args.push_back(Entry);
1276 // TrampSize == (isPPC64 ? 48 : 40);
1277 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1278 isPPC64 ? MVT::i64 : MVT::i32);
1279 Args.push_back(Entry);
1281 Entry.Node = FPtr; Args.push_back(Entry);
1282 Entry.Node = Nest; Args.push_back(Entry);
1284 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1285 std::pair<SDValue, SDValue> CallResult =
1286 LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false,
1287 false, false, 0, CallingConv::C, false,
1288 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1292 { CallResult.first, CallResult.second };
1294 return DAG.getMergeValues(Ops, 2, dl);
1297 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1298 int VarArgsFrameIndex,
1299 int VarArgsStackOffset,
1300 unsigned VarArgsNumGPR,
1301 unsigned VarArgsNumFPR,
1302 const PPCSubtarget &Subtarget) {
1303 DebugLoc dl = Op.getDebugLoc();
1305 if (Subtarget.isDarwinABI()) {
1306 // vastart just stores the address of the VarArgsFrameIndex slot into the
1307 // memory location argument.
1308 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1309 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1310 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1311 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1314 // For the SVR4 ABI we follow the layout of the va_list struct.
1315 // We suppose the given va_list is already allocated.
1318 // char gpr; /* index into the array of 8 GPRs
1319 // * stored in the register save area
1320 // * gpr=0 corresponds to r3,
1321 // * gpr=1 to r4, etc.
1323 // char fpr; /* index into the array of 8 FPRs
1324 // * stored in the register save area
1325 // * fpr=0 corresponds to f1,
1326 // * fpr=1 to f2, etc.
1328 // char *overflow_arg_area;
1329 // /* location on stack that holds
1330 // * the next overflow argument
1332 // char *reg_save_area;
1333 // /* where r3:r10 and f1:f8 (if saved)
1339 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32);
1340 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32);
1343 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1345 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1346 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1348 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1349 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1351 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1352 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1354 uint64_t FPROffset = 1;
1355 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1357 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1359 // Store first byte : number of int regs
1360 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1361 Op.getOperand(1), SV, 0, MVT::i8);
1362 uint64_t nextOffset = FPROffset;
1363 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1366 // Store second byte : number of float regs
1367 SDValue secondStore =
1368 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8);
1369 nextOffset += StackOffset;
1370 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1372 // Store second word : arguments given on stack
1373 SDValue thirdStore =
1374 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
1375 nextOffset += FrameOffset;
1376 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1378 // Store third word : arguments given in registers
1379 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset);
1383 #include "PPCGenCallingConv.inc"
1385 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1386 CCValAssign::LocInfo &LocInfo,
1387 ISD::ArgFlagsTy &ArgFlags,
1392 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1394 CCValAssign::LocInfo &LocInfo,
1395 ISD::ArgFlagsTy &ArgFlags,
1397 static const unsigned ArgRegs[] = {
1398 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1399 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1401 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1403 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1405 // Skip one register if the first unallocated register has an even register
1406 // number and there are still argument registers available which have not been
1407 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1408 // need to skip a register if RegNum is odd.
1409 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1410 State.AllocateReg(ArgRegs[RegNum]);
1413 // Always return false here, as this function only makes sure that the first
1414 // unallocated register has an odd register number and does not actually
1415 // allocate a register for the current argument.
1419 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1421 CCValAssign::LocInfo &LocInfo,
1422 ISD::ArgFlagsTy &ArgFlags,
1424 static const unsigned ArgRegs[] = {
1425 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1429 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1431 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1433 // If there is only one Floating-point register left we need to put both f64
1434 // values of a split ppc_fp128 value on the stack.
1435 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1436 State.AllocateReg(ArgRegs[RegNum]);
1439 // Always return false here, as this function only makes sure that the two f64
1440 // values a ppc_fp128 value is split into are both passed in registers or both
1441 // passed on the stack and does not actually allocate a register for the
1442 // current argument.
1446 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1447 /// depending on which subtarget is selected.
1448 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1449 if (Subtarget.isDarwinABI()) {
1450 static const unsigned FPR[] = {
1451 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1452 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1458 static const unsigned FPR[] = {
1459 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1465 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1467 static unsigned CalculateStackSlotSize(SDValue Arg, ISD::ArgFlagsTy Flags,
1468 unsigned PtrByteSize) {
1469 MVT ArgVT = Arg.getValueType();
1470 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1471 if (Flags.isByVal())
1472 ArgSize = Flags.getByValSize();
1473 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1479 PPCTargetLowering::LowerFORMAL_ARGUMENTS_SVR4(SDValue Op,
1481 int &VarArgsFrameIndex,
1482 int &VarArgsStackOffset,
1483 unsigned &VarArgsNumGPR,
1484 unsigned &VarArgsNumFPR,
1485 const PPCSubtarget &Subtarget) {
1486 // SVR4 ABI Stack Frame Layout:
1487 // +-----------------------------------+
1488 // +--> | Back chain |
1489 // | +-----------------------------------+
1490 // | | Floating-point register save area |
1491 // | +-----------------------------------+
1492 // | | General register save area |
1493 // | +-----------------------------------+
1494 // | | CR save word |
1495 // | +-----------------------------------+
1496 // | | VRSAVE save word |
1497 // | +-----------------------------------+
1498 // | | Alignment padding |
1499 // | +-----------------------------------+
1500 // | | Vector register save area |
1501 // | +-----------------------------------+
1502 // | | Local variable space |
1503 // | +-----------------------------------+
1504 // | | Parameter list area |
1505 // | +-----------------------------------+
1506 // | | LR save word |
1507 // | +-----------------------------------+
1508 // SP--> +--- | Back chain |
1509 // +-----------------------------------+
1512 // System V Application Binary Interface PowerPC Processor Supplement
1513 // AltiVec Technology Programming Interface Manual
1515 MachineFunction &MF = DAG.getMachineFunction();
1516 MachineFrameInfo *MFI = MF.getFrameInfo();
1517 SmallVector<SDValue, 8> ArgValues;
1518 SDValue Root = Op.getOperand(0);
1519 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1520 DebugLoc dl = Op.getDebugLoc();
1522 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1523 // Potential tail calls could cause overwriting of argument stack slots.
1524 unsigned CC = MF.getFunction()->getCallingConv();
1525 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1526 unsigned PtrByteSize = 4;
1528 // Assign locations to all of the incoming arguments.
1529 SmallVector<CCValAssign, 16> ArgLocs;
1530 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1532 // Reserve space for the linkage area on the stack.
1533 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
1535 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_PPC_SVR4);
1537 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1538 CCValAssign &VA = ArgLocs[i];
1540 // Arguments stored in registers.
1541 if (VA.isRegLoc()) {
1542 TargetRegisterClass *RC;
1543 MVT ValVT = VA.getValVT();
1545 switch (ValVT.getSimpleVT()) {
1547 assert(0 && "ValVT not supported by FORMAL_ARGUMENTS Lowering");
1549 RC = PPC::GPRCRegisterClass;
1552 RC = PPC::F4RCRegisterClass;
1555 RC = PPC::F8RCRegisterClass;
1561 RC = PPC::VRRCRegisterClass;
1565 // Transform the arguments stored in physical registers into virtual ones.
1566 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1567 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, ValVT);
1569 ArgValues.push_back(ArgValue);
1571 // Argument stored in memory.
1572 assert(VA.isMemLoc());
1574 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1575 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1578 // Create load nodes to retrieve arguments from the stack.
1579 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1580 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1584 // Assign locations to all of the incoming aggregate by value arguments.
1585 // Aggregates passed by value are stored in the local variable space of the
1586 // caller's stack frame, right above the parameter list area.
1587 SmallVector<CCValAssign, 16> ByValArgLocs;
1588 CCState CCByValInfo(CC, isVarArg, getTargetMachine(), ByValArgLocs);
1590 // Reserve stack space for the allocations in CCInfo.
1591 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1593 CCByValInfo.AnalyzeFormalArguments(Op.getNode(), CC_PPC_SVR4_ByVal);
1595 // Area that is at least reserved in the caller of this function.
1596 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1598 // Set the size that is at least reserved in caller of this function. Tail
1599 // call optimized function's reserved stack space needs to be aligned so that
1600 // taking the difference between two stack areas will result in an aligned
1602 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1605 std::max(MinReservedArea,
1606 PPCFrameInfo::getMinCallFrameSize(false, false));
1608 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1609 getStackAlignment();
1610 unsigned AlignMask = TargetAlign-1;
1611 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1613 FI->setMinReservedArea(MinReservedArea);
1615 SmallVector<SDValue, 8> MemOps;
1617 // If the function takes variable number of arguments, make a frame index for
1618 // the start of the first vararg value... for expansion of llvm.va_start.
1620 static const unsigned GPArgRegs[] = {
1621 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1622 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1624 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1626 static const unsigned FPArgRegs[] = {
1627 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1630 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1632 VarArgsNumGPR = CCInfo.getFirstUnallocated(GPArgRegs, NumGPArgRegs);
1633 VarArgsNumFPR = CCInfo.getFirstUnallocated(FPArgRegs, NumFPArgRegs);
1635 // Make room for NumGPArgRegs and NumFPArgRegs.
1636 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1637 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
1639 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1640 CCInfo.getNextStackOffset());
1642 VarArgsFrameIndex = MFI->CreateStackObject(Depth, 8);
1643 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1645 // The fixed integer arguments of a variadic function are
1646 // stored to the VarArgsFrameIndex on the stack.
1647 unsigned GPRIndex = 0;
1648 for (; GPRIndex != VarArgsNumGPR; ++GPRIndex) {
1649 SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT);
1650 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
1651 MemOps.push_back(Store);
1652 // Increment the address by four for the next argument to store
1653 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1654 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1657 // If this function is vararg, store any remaining integer argument regs
1658 // to their spots on the stack so that they may be loaded by deferencing the
1659 // result of va_next.
1660 for (; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1661 unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1663 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1664 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1665 MemOps.push_back(Store);
1666 // Increment the address by four for the next argument to store
1667 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1668 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1671 // FIXME SVR4: We only need to save FP argument registers if CR bit 6 is
1674 // The double arguments are stored to the VarArgsFrameIndex
1676 unsigned FPRIndex = 0;
1677 for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) {
1678 SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
1679 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
1680 MemOps.push_back(Store);
1681 // Increment the address by eight for the next argument to store
1682 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1684 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1687 for (; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1688 unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1690 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64);
1691 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1692 MemOps.push_back(Store);
1693 // Increment the address by eight for the next argument to store
1694 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1696 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1700 if (!MemOps.empty())
1701 Root = DAG.getNode(ISD::TokenFactor, dl,
1702 MVT::Other, &MemOps[0], MemOps.size());
1705 ArgValues.push_back(Root);
1707 // Return the new list of results.
1708 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1709 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1713 PPCTargetLowering::LowerFORMAL_ARGUMENTS_Darwin(SDValue Op,
1715 int &VarArgsFrameIndex,
1716 const PPCSubtarget &Subtarget) {
1717 // TODO: add description of PPC stack frame format, or at least some docs.
1719 MachineFunction &MF = DAG.getMachineFunction();
1720 MachineFrameInfo *MFI = MF.getFrameInfo();
1721 SmallVector<SDValue, 8> ArgValues;
1722 SDValue Root = Op.getOperand(0);
1723 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1724 DebugLoc dl = Op.getDebugLoc();
1726 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1727 bool isPPC64 = PtrVT == MVT::i64;
1728 // Potential tail calls could cause overwriting of argument stack slots.
1729 unsigned CC = MF.getFunction()->getCallingConv();
1730 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1731 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1733 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
1734 // Area that is at least reserved in caller of this function.
1735 unsigned MinReservedArea = ArgOffset;
1737 static const unsigned GPR_32[] = { // 32-bit registers.
1738 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1739 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1741 static const unsigned GPR_64[] = { // 64-bit registers.
1742 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1743 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1746 static const unsigned *FPR = GetFPR(Subtarget);
1748 static const unsigned VR[] = {
1749 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1750 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1753 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1754 const unsigned Num_FPR_Regs = 13;
1755 const unsigned Num_VR_Regs = array_lengthof( VR);
1757 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1759 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1761 // In 32-bit non-varargs functions, the stack space for vectors is after the
1762 // stack space for non-vectors. We do not use this space unless we have
1763 // too many vectors to fit in registers, something that only occurs in
1764 // constructed examples:), but we have to walk the arglist to figure
1765 // that out...for the pathological case, compute VecArgOffset as the
1766 // start of the vector parameter area. Computing VecArgOffset is the
1767 // entire point of the following loop.
1768 unsigned VecArgOffset = ArgOffset;
1769 if (!isVarArg && !isPPC64) {
1770 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e;
1772 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1773 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1774 ISD::ArgFlagsTy Flags =
1775 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1777 if (Flags.isByVal()) {
1778 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1779 ObjSize = Flags.getByValSize();
1781 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1782 VecArgOffset += ArgSize;
1786 switch(ObjectVT.getSimpleVT()) {
1787 default: assert(0 && "Unhandled argument type!");
1790 VecArgOffset += isPPC64 ? 8 : 4;
1792 case MVT::i64: // PPC64
1800 // Nothing to do, we're only looking at Nonvector args here.
1805 // We've found where the vector parameter area in memory is. Skip the
1806 // first 12 parameters; these don't use that memory.
1807 VecArgOffset = ((VecArgOffset+15)/16)*16;
1808 VecArgOffset += 12*16;
1810 // Add DAG nodes to load the arguments or copy them out of registers. On
1811 // entry to a function on PPC, the arguments start after the linkage area,
1812 // although the first ones are often in registers.
1814 SmallVector<SDValue, 8> MemOps;
1815 unsigned nAltivecParamsAtEnd = 0;
1816 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1;
1817 ArgNo != e; ++ArgNo) {
1819 bool needsLoad = false;
1820 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1821 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1822 unsigned ArgSize = ObjSize;
1823 ISD::ArgFlagsTy Flags =
1824 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1826 unsigned CurArgOffset = ArgOffset;
1828 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1829 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1830 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1831 if (isVarArg || isPPC64) {
1832 MinReservedArea = ((MinReservedArea+15)/16)*16;
1833 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1836 } else nAltivecParamsAtEnd++;
1838 // Calculate min reserved area.
1839 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1843 // FIXME the codegen can be much improved in some cases.
1844 // We do not have to keep everything in memory.
1845 if (Flags.isByVal()) {
1846 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1847 ObjSize = Flags.getByValSize();
1848 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1849 // Objects of size 1 and 2 are right justified, everything else is
1850 // left justified. This means the memory address is adjusted forwards.
1851 if (ObjSize==1 || ObjSize==2) {
1852 CurArgOffset = CurArgOffset + (4 - ObjSize);
1854 // The value of the object is its address.
1855 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1856 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1857 ArgValues.push_back(FIN);
1858 if (ObjSize==1 || ObjSize==2) {
1859 if (GPR_idx != Num_GPR_Regs) {
1860 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1861 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1862 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1863 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1864 MemOps.push_back(Store);
1868 ArgOffset += PtrByteSize;
1872 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1873 // Store whatever pieces of the object are in registers
1874 // to memory. ArgVal will be address of the beginning of
1876 if (GPR_idx != Num_GPR_Regs) {
1877 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1878 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1879 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1880 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1881 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1882 MemOps.push_back(Store);
1884 ArgOffset += PtrByteSize;
1886 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1893 switch (ObjectVT.getSimpleVT()) {
1894 default: assert(0 && "Unhandled argument type!");
1897 if (GPR_idx != Num_GPR_Regs) {
1898 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1899 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1903 ArgSize = PtrByteSize;
1905 // All int arguments reserve stack space in the Darwin ABI.
1906 ArgOffset += PtrByteSize;
1910 case MVT::i64: // PPC64
1911 if (GPR_idx != Num_GPR_Regs) {
1912 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1913 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1915 if (ObjectVT == MVT::i32) {
1916 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1917 // value to MVT::i64 and then truncate to the correct register size.
1919 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1920 DAG.getValueType(ObjectVT));
1921 else if (Flags.isZExt())
1922 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1923 DAG.getValueType(ObjectVT));
1925 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1931 ArgSize = PtrByteSize;
1933 // All int arguments reserve stack space in the Darwin ABI.
1939 // Every 4 bytes of argument space consumes one of the GPRs available for
1940 // argument passing.
1941 if (GPR_idx != Num_GPR_Regs) {
1943 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1946 if (FPR_idx != Num_FPR_Regs) {
1949 if (ObjectVT == MVT::f32)
1950 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1952 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1954 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1960 // All FP arguments reserve stack space in the Darwin ABI.
1961 ArgOffset += isPPC64 ? 8 : ObjSize;
1967 // Note that vector arguments in registers don't reserve stack space,
1968 // except in varargs functions.
1969 if (VR_idx != Num_VR_Regs) {
1970 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
1971 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1973 while ((ArgOffset % 16) != 0) {
1974 ArgOffset += PtrByteSize;
1975 if (GPR_idx != Num_GPR_Regs)
1979 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1983 if (!isVarArg && !isPPC64) {
1984 // Vectors go after all the nonvectors.
1985 CurArgOffset = VecArgOffset;
1988 // Vectors are aligned.
1989 ArgOffset = ((ArgOffset+15)/16)*16;
1990 CurArgOffset = ArgOffset;
1998 // We need to load the argument to a virtual register if we determined above
1999 // that we ran out of physical registers of the appropriate type.
2001 int FI = MFI->CreateFixedObject(ObjSize,
2002 CurArgOffset + (ArgSize - ObjSize),
2004 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2005 ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
2008 ArgValues.push_back(ArgVal);
2011 // Set the size that is at least reserved in caller of this function. Tail
2012 // call optimized function's reserved stack space needs to be aligned so that
2013 // taking the difference between two stack areas will result in an aligned
2015 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2016 // Add the Altivec parameters at the end, if needed.
2017 if (nAltivecParamsAtEnd) {
2018 MinReservedArea = ((MinReservedArea+15)/16)*16;
2019 MinReservedArea += 16*nAltivecParamsAtEnd;
2022 std::max(MinReservedArea,
2023 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2024 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2025 getStackAlignment();
2026 unsigned AlignMask = TargetAlign-1;
2027 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2028 FI->setMinReservedArea(MinReservedArea);
2030 // If the function takes variable number of arguments, make a frame index for
2031 // the start of the first vararg value... for expansion of llvm.va_start.
2033 int Depth = ArgOffset;
2035 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2037 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
2039 // If this function is vararg, store any remaining integer argument regs
2040 // to their spots on the stack so that they may be loaded by deferencing the
2041 // result of va_next.
2042 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2046 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2048 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2050 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
2051 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
2052 MemOps.push_back(Store);
2053 // Increment the address by four for the next argument to store
2054 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2055 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2059 if (!MemOps.empty())
2060 Root = DAG.getNode(ISD::TokenFactor, dl,
2061 MVT::Other, &MemOps[0], MemOps.size());
2063 ArgValues.push_back(Root);
2065 // Return the new list of results.
2066 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
2067 &ArgValues[0], ArgValues.size());
2070 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2071 /// linkage area for the Darwin ABI.
2073 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2077 CallSDNode *TheCall,
2078 unsigned &nAltivecParamsAtEnd) {
2079 // Count how many bytes are to be pushed on the stack, including the linkage
2080 // area, and parameter passing area. We start with 24/48 bytes, which is
2081 // prereserved space for [SP][CR][LR][3 x unused].
2082 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true);
2083 unsigned NumOps = TheCall->getNumArgs();
2084 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2086 // Add up all the space actually used.
2087 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2088 // they all go in registers, but we must reserve stack space for them for
2089 // possible use by the caller. In varargs or 64-bit calls, parameters are
2090 // assigned stack space in order, with padding so Altivec parameters are
2092 nAltivecParamsAtEnd = 0;
2093 for (unsigned i = 0; i != NumOps; ++i) {
2094 SDValue Arg = TheCall->getArg(i);
2095 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2096 MVT ArgVT = Arg.getValueType();
2097 // Varargs Altivec parameters are padded to a 16 byte boundary.
2098 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2099 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2100 if (!isVarArg && !isPPC64) {
2101 // Non-varargs Altivec parameters go after all the non-Altivec
2102 // parameters; handle those later so we know how much padding we need.
2103 nAltivecParamsAtEnd++;
2106 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2107 NumBytes = ((NumBytes+15)/16)*16;
2109 NumBytes += CalculateStackSlotSize(Arg, Flags, PtrByteSize);
2112 // Allow for Altivec parameters at the end, if needed.
2113 if (nAltivecParamsAtEnd) {
2114 NumBytes = ((NumBytes+15)/16)*16;
2115 NumBytes += 16*nAltivecParamsAtEnd;
2118 // The prolog code of the callee may store up to 8 GPR argument registers to
2119 // the stack, allowing va_start to index over them in memory if its varargs.
2120 // Because we cannot tell if this is needed on the caller side, we have to
2121 // conservatively assume that it is needed. As such, make sure we have at
2122 // least enough stack space for the caller to store the 8 GPRs.
2123 NumBytes = std::max(NumBytes,
2124 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2126 // Tail call needs the stack to be aligned.
2127 if (CC==CallingConv::Fast && PerformTailCallOpt) {
2128 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2129 getStackAlignment();
2130 unsigned AlignMask = TargetAlign-1;
2131 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2137 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2138 /// adjusted to accomodate the arguments for the tailcall.
2139 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
2140 unsigned ParamSize) {
2142 if (!IsTailCall) return 0;
2144 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2145 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2146 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2147 // Remember only if the new adjustement is bigger.
2148 if (SPDiff < FI->getTailCallSPDelta())
2149 FI->setTailCallSPDelta(SPDiff);
2154 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
2155 /// following the call is a return. A function is eligible if caller/callee
2156 /// calling conventions match, currently only fastcc supports tail calls, and
2157 /// the function CALL is immediatly followed by a RET.
2159 PPCTargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
2161 SelectionDAG& DAG) const {
2162 // Variable argument functions are not supported.
2163 if (!PerformTailCallOpt || TheCall->isVarArg())
2166 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
2167 MachineFunction &MF = DAG.getMachineFunction();
2168 unsigned CallerCC = MF.getFunction()->getCallingConv();
2169 unsigned CalleeCC = TheCall->getCallingConv();
2170 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2171 // Functions containing by val parameters are not supported.
2172 for (unsigned i = 0; i != TheCall->getNumArgs(); i++) {
2173 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2174 if (Flags.isByVal()) return false;
2177 SDValue Callee = TheCall->getCallee();
2178 // Non PIC/GOT tail calls are supported.
2179 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2182 // At the moment we can only do local tail calls (in same module, hidden
2183 // or protected) if we are generating PIC.
2184 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2185 return G->getGlobal()->hasHiddenVisibility()
2186 || G->getGlobal()->hasProtectedVisibility();
2193 /// isCallCompatibleAddress - Return the immediate to use if the specified
2194 /// 32-bit value is representable in the immediate field of a BxA instruction.
2195 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2196 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2199 int Addr = C->getZExtValue();
2200 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2201 (Addr << 6 >> 6) != Addr)
2202 return 0; // Top 6 bits have to be sext of immediate.
2204 return DAG.getConstant((int)C->getZExtValue() >> 2,
2205 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2210 struct TailCallArgumentInfo {
2215 TailCallArgumentInfo() : FrameIdx(0) {}
2220 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2222 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2224 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2225 SmallVector<SDValue, 8> &MemOpChains,
2227 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2228 SDValue Arg = TailCallArgs[i].Arg;
2229 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2230 int FI = TailCallArgs[i].FrameIdx;
2231 // Store relative to framepointer.
2232 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2233 PseudoSourceValue::getFixedStack(FI),
2238 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2239 /// the appropriate stack slot for the tail call optimized function call.
2240 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2241 MachineFunction &MF,
2250 // Calculate the new stack slot for the return address.
2251 int SlotSize = isPPC64 ? 8 : 4;
2252 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2254 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2256 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2257 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2258 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2259 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
2261 // When using the SVR4 ABI there is no need to move the FP stack slot
2262 // as the FP is never overwritten.
2265 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2266 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
2267 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2268 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2269 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
2275 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2276 /// the position of the argument.
2278 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2279 SDValue Arg, int SPDiff, unsigned ArgOffset,
2280 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2281 int Offset = ArgOffset + SPDiff;
2282 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2283 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
2284 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2285 SDValue FIN = DAG.getFrameIndex(FI, VT);
2286 TailCallArgumentInfo Info;
2288 Info.FrameIdxOp = FIN;
2290 TailCallArguments.push_back(Info);
2293 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2294 /// stack slot. Returns the chain as result and the loaded frame pointers in
2295 /// LROpOut/FPOpout. Used when tail calling.
2296 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2304 // Load the LR and FP stack slot for later adjusting.
2305 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2306 LROpOut = getReturnAddrFrameIndex(DAG);
2307 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
2308 Chain = SDValue(LROpOut.getNode(), 1);
2310 // When using the SVR4 ABI there is no need to load the FP stack slot
2311 // as the FP is never overwritten.
2313 FPOpOut = getFramePointerFrameIndex(DAG);
2314 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
2315 Chain = SDValue(FPOpOut.getNode(), 1);
2321 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2322 /// by "Src" to address "Dst" of size "Size". Alignment information is
2323 /// specified by the specific parameter attribute. The copy will be passed as
2324 /// a byval function parameter.
2325 /// Sometimes what we are copying is the end of a larger object, the part that
2326 /// does not fit in registers.
2328 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2329 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2331 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2332 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2333 false, NULL, 0, NULL, 0);
2336 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2339 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2340 SDValue Arg, SDValue PtrOff, int SPDiff,
2341 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2342 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2343 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2345 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2350 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2352 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2353 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2354 DAG.getConstant(ArgOffset, PtrVT));
2356 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
2357 // Calculate and remember argument location.
2358 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2363 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2364 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2365 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2366 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2367 MachineFunction &MF = DAG.getMachineFunction();
2369 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2370 // might overwrite each other in case of tail call optimization.
2371 SmallVector<SDValue, 8> MemOpChains2;
2372 // Do not flag preceeding copytoreg stuff together with the following stuff.
2374 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2376 if (!MemOpChains2.empty())
2377 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2378 &MemOpChains2[0], MemOpChains2.size());
2380 // Store the return address to the appropriate stack slot.
2381 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2382 isPPC64, isDarwinABI, dl);
2384 // Emit callseq_end just before tailcall node.
2385 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2386 DAG.getIntPtrConstant(0, true), InFlag);
2387 InFlag = Chain.getValue(1);
2391 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2392 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2393 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2394 SmallVector<SDValue, 8> &Ops, std::vector<MVT> &NodeTys,
2396 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2397 NodeTys.push_back(MVT::Other); // Returns a chain
2398 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2400 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2402 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2403 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2404 // node so that legalize doesn't hack it.
2405 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2406 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2407 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2408 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2409 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2410 // If this is an absolute destination address, use the munged value.
2411 Callee = SDValue(Dest, 0);
2413 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2414 // to do the call, we can't use PPCISD::CALL.
2415 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2416 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2417 2 + (InFlag.getNode() != 0));
2418 InFlag = Chain.getValue(1);
2421 NodeTys.push_back(MVT::Other);
2422 NodeTys.push_back(MVT::Flag);
2423 Ops.push_back(Chain);
2424 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2426 // Add CTR register as callee so a bctr can be emitted later.
2428 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2431 // If this is a direct call, pass the chain and the callee.
2432 if (Callee.getNode()) {
2433 Ops.push_back(Chain);
2434 Ops.push_back(Callee);
2436 // If this is a tail call add stack pointer delta.
2438 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2440 // Add argument registers to the end of the list so that they are known live
2442 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2443 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2444 RegsToPass[i].second.getValueType()));
2449 static SDValue LowerCallReturn(SDValue Op, SelectionDAG &DAG, TargetMachine &TM,
2450 CallSDNode *TheCall, SDValue Chain,
2452 bool isVarArg = TheCall->isVarArg();
2453 DebugLoc dl = TheCall->getDebugLoc();
2454 SmallVector<SDValue, 16> ResultVals;
2455 SmallVector<CCValAssign, 16> RVLocs;
2456 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
2457 CCState CCRetInfo(CallerCC, isVarArg, TM, RVLocs);
2458 CCRetInfo.AnalyzeCallResult(TheCall, RetCC_PPC);
2460 // Copy all of the result registers out of their specified physreg.
2461 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2462 CCValAssign &VA = RVLocs[i];
2463 MVT VT = VA.getValVT();
2464 assert(VA.isRegLoc() && "Can only return in registers!");
2465 Chain = DAG.getCopyFromReg(Chain, dl,
2466 VA.getLocReg(), VT, InFlag).getValue(1);
2467 ResultVals.push_back(Chain.getValue(0));
2468 InFlag = Chain.getValue(2);
2471 // If the function returns void, just return the chain.
2475 // Otherwise, merge everything together with a MERGE_VALUES node.
2476 ResultVals.push_back(Chain);
2477 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
2478 &ResultVals[0], ResultVals.size());
2479 return Res.getValue(Op.getResNo());
2483 SDValue FinishCall(SelectionDAG &DAG, CallSDNode *TheCall, TargetMachine &TM,
2484 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2485 SDValue Op, SDValue InFlag, SDValue Chain, SDValue &Callee,
2486 int SPDiff, unsigned NumBytes) {
2487 unsigned CC = TheCall->getCallingConv();
2488 DebugLoc dl = TheCall->getDebugLoc();
2489 bool isTailCall = TheCall->isTailCall()
2490 && CC == CallingConv::Fast && PerformTailCallOpt;
2492 std::vector<MVT> NodeTys;
2493 SmallVector<SDValue, 8> Ops;
2494 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2495 isTailCall, RegsToPass, Ops, NodeTys,
2496 TM.getSubtarget<PPCSubtarget>().isSVR4ABI());
2498 // When performing tail call optimization the callee pops its arguments off
2499 // the stack. Account for this here so these bytes can be pushed back on in
2500 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2501 int BytesCalleePops =
2502 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2504 if (InFlag.getNode())
2505 Ops.push_back(InFlag);
2509 assert(InFlag.getNode() &&
2510 "Flag must be set. Depend on flag being set in LowerRET");
2511 Chain = DAG.getNode(PPCISD::TAILCALL, dl,
2512 TheCall->getVTList(), &Ops[0], Ops.size());
2513 return SDValue(Chain.getNode(), Op.getResNo());
2516 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2517 InFlag = Chain.getValue(1);
2519 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2520 DAG.getIntPtrConstant(BytesCalleePops, true),
2522 if (TheCall->getValueType(0) != MVT::Other)
2523 InFlag = Chain.getValue(1);
2525 return LowerCallReturn(Op, DAG, TM, TheCall, Chain, InFlag);
2528 SDValue PPCTargetLowering::LowerCALL_SVR4(SDValue Op, SelectionDAG &DAG,
2529 const PPCSubtarget &Subtarget,
2530 TargetMachine &TM) {
2531 // See PPCTargetLowering::LowerFORMAL_ARGUMENTS_SVR4() for a description
2532 // of the SVR4 ABI stack frame layout.
2533 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
2534 SDValue Chain = TheCall->getChain();
2535 bool isVarArg = TheCall->isVarArg();
2536 unsigned CC = TheCall->getCallingConv();
2537 assert((CC == CallingConv::C ||
2538 CC == CallingConv::Fast) && "Unknown calling convention!");
2539 bool isTailCall = TheCall->isTailCall()
2540 && CC == CallingConv::Fast && PerformTailCallOpt;
2541 SDValue Callee = TheCall->getCallee();
2542 DebugLoc dl = TheCall->getDebugLoc();
2544 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2545 unsigned PtrByteSize = 4;
2547 MachineFunction &MF = DAG.getMachineFunction();
2549 // Mark this function as potentially containing a function that contains a
2550 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2551 // and restoring the callers stack pointer in this functions epilog. This is
2552 // done because by tail calling the called function might overwrite the value
2553 // in this function's (MF) stack pointer stack slot 0(SP).
2554 if (PerformTailCallOpt && CC==CallingConv::Fast)
2555 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2557 // Count how many bytes are to be pushed on the stack, including the linkage
2558 // area, parameter list area and the part of the local variable space which
2559 // contains copies of aggregates which are passed by value.
2561 // Assign locations to all of the outgoing arguments.
2562 SmallVector<CCValAssign, 16> ArgLocs;
2563 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
2565 // Reserve space for the linkage area on the stack.
2566 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
2569 // Handle fixed and variable vector arguments differently.
2570 // Fixed vector arguments go into registers as long as registers are
2571 // available. Variable vector arguments always go into memory.
2572 unsigned NumArgs = TheCall->getNumArgs();
2573 unsigned NumFixedArgs = TheCall->getNumFixedArgs();
2575 for (unsigned i = 0; i != NumArgs; ++i) {
2576 MVT ArgVT = TheCall->getArg(i).getValueType();
2577 ISD::ArgFlagsTy ArgFlags = TheCall->getArgFlags(i);
2580 if (i < NumFixedArgs) {
2581 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2584 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2590 cerr << "Call operand #" << i << " has unhandled type "
2591 << ArgVT.getMVTString() << "\n";
2597 // All arguments are treated the same.
2598 CCInfo.AnalyzeCallOperands(TheCall, CC_PPC_SVR4);
2601 // Assign locations to all of the outgoing aggregate by value arguments.
2602 SmallVector<CCValAssign, 16> ByValArgLocs;
2603 CCState CCByValInfo(CC, isVarArg, getTargetMachine(), ByValArgLocs);
2605 // Reserve stack space for the allocations in CCInfo.
2606 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2608 CCByValInfo.AnalyzeCallOperands(TheCall, CC_PPC_SVR4_ByVal);
2610 // Size of the linkage area, parameter list area and the part of the local
2611 // space variable where copies of aggregates which are passed by value are
2613 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2615 // Calculate by how many bytes the stack has to be adjusted in case of tail
2616 // call optimization.
2617 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2619 // Adjust the stack pointer for the new arguments...
2620 // These operations are automatically eliminated by the prolog/epilog pass
2621 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2622 SDValue CallSeqStart = Chain;
2624 // Load the return address and frame pointer so it can be moved somewhere else
2627 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2630 // Set up a copy of the stack pointer for use loading and storing any
2631 // arguments that may not fit in the registers available for argument
2633 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2635 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2636 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2637 SmallVector<SDValue, 8> MemOpChains;
2639 // Walk the register/memloc assignments, inserting copies/loads.
2640 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2643 CCValAssign &VA = ArgLocs[i];
2644 SDValue Arg = TheCall->getArg(i);
2645 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2647 if (Flags.isByVal()) {
2648 // Argument is an aggregate which is passed by value, thus we need to
2649 // create a copy of it in the local variable space of the current stack
2650 // frame (which is the stack frame of the caller) and pass the address of
2651 // this copy to the callee.
2652 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2653 CCValAssign &ByValVA = ByValArgLocs[j++];
2654 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2656 // Memory reserved in the local variable space of the callers stack frame.
2657 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2659 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2660 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2662 // Create a copy of the argument in the local area of the current
2664 SDValue MemcpyCall =
2665 CreateCopyOfByValArgument(Arg, PtrOff,
2666 CallSeqStart.getNode()->getOperand(0),
2669 // This must go outside the CALLSEQ_START..END.
2670 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2671 CallSeqStart.getNode()->getOperand(1));
2672 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2673 NewCallSeqStart.getNode());
2674 Chain = CallSeqStart = NewCallSeqStart;
2676 // Pass the address of the aggregate copy on the stack either in a
2677 // physical register or in the parameter list area of the current stack
2678 // frame to the callee.
2682 if (VA.isRegLoc()) {
2683 // Put argument in a physical register.
2684 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2686 // Put argument in the parameter list area of the current stack frame.
2687 assert(VA.isMemLoc());
2688 unsigned LocMemOffset = VA.getLocMemOffset();
2691 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2692 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2694 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2695 PseudoSourceValue::getStack(), LocMemOffset));
2697 // Calculate and remember argument location.
2698 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2704 if (!MemOpChains.empty())
2705 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2706 &MemOpChains[0], MemOpChains.size());
2708 // Build a sequence of copy-to-reg nodes chained together with token chain
2709 // and flag operands which copy the outgoing args into the appropriate regs.
2711 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2712 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2713 RegsToPass[i].second, InFlag);
2714 InFlag = Chain.getValue(1);
2717 // Set CR6 to true if this is a vararg call.
2719 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
2720 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2721 InFlag = Chain.getValue(1);
2725 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2726 false, TailCallArguments);
2729 return FinishCall(DAG, TheCall, TM, RegsToPass, Op, InFlag, Chain, Callee,
2733 SDValue PPCTargetLowering::LowerCALL_Darwin(SDValue Op, SelectionDAG &DAG,
2734 const PPCSubtarget &Subtarget,
2735 TargetMachine &TM) {
2736 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
2737 SDValue Chain = TheCall->getChain();
2738 bool isVarArg = TheCall->isVarArg();
2739 unsigned CC = TheCall->getCallingConv();
2740 bool isTailCall = TheCall->isTailCall()
2741 && CC == CallingConv::Fast && PerformTailCallOpt;
2742 SDValue Callee = TheCall->getCallee();
2743 unsigned NumOps = TheCall->getNumArgs();
2744 DebugLoc dl = TheCall->getDebugLoc();
2746 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2747 bool isPPC64 = PtrVT == MVT::i64;
2748 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2750 MachineFunction &MF = DAG.getMachineFunction();
2752 // Mark this function as potentially containing a function that contains a
2753 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2754 // and restoring the callers stack pointer in this functions epilog. This is
2755 // done because by tail calling the called function might overwrite the value
2756 // in this function's (MF) stack pointer stack slot 0(SP).
2757 if (PerformTailCallOpt && CC==CallingConv::Fast)
2758 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2760 unsigned nAltivecParamsAtEnd = 0;
2762 // Count how many bytes are to be pushed on the stack, including the linkage
2763 // area, and parameter passing area. We start with 24/48 bytes, which is
2764 // prereserved space for [SP][CR][LR][3 x unused].
2766 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CC, TheCall,
2767 nAltivecParamsAtEnd);
2769 // Calculate by how many bytes the stack has to be adjusted in case of tail
2770 // call optimization.
2771 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2773 // Adjust the stack pointer for the new arguments...
2774 // These operations are automatically eliminated by the prolog/epilog pass
2775 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2776 SDValue CallSeqStart = Chain;
2778 // Load the return address and frame pointer so it can be move somewhere else
2781 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2784 // Set up a copy of the stack pointer for use loading and storing any
2785 // arguments that may not fit in the registers available for argument
2789 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2791 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2793 // Figure out which arguments are going to go in registers, and which in
2794 // memory. Also, if this is a vararg function, floating point operations
2795 // must be stored to our stack, and loaded into integer regs as well, if
2796 // any integer regs are available for argument passing.
2797 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
2798 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2800 static const unsigned GPR_32[] = { // 32-bit registers.
2801 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2802 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2804 static const unsigned GPR_64[] = { // 64-bit registers.
2805 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2806 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2808 static const unsigned *FPR = GetFPR(Subtarget);
2810 static const unsigned VR[] = {
2811 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2812 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2814 const unsigned NumGPRs = array_lengthof(GPR_32);
2815 const unsigned NumFPRs = 13;
2816 const unsigned NumVRs = array_lengthof(VR);
2818 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2820 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2821 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2823 SmallVector<SDValue, 8> MemOpChains;
2824 for (unsigned i = 0; i != NumOps; ++i) {
2826 SDValue Arg = TheCall->getArg(i);
2827 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2829 // PtrOff will be used to store the current argument to the stack if a
2830 // register cannot be found for it.
2833 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2835 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
2837 // On PPC64, promote integers to 64-bit values.
2838 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2839 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2840 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2841 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
2844 // FIXME memcpy is used way more than necessary. Correctness first.
2845 if (Flags.isByVal()) {
2846 unsigned Size = Flags.getByValSize();
2847 if (Size==1 || Size==2) {
2848 // Very small objects are passed right-justified.
2849 // Everything else is passed left-justified.
2850 MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2851 if (GPR_idx != NumGPRs) {
2852 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
2854 MemOpChains.push_back(Load.getValue(1));
2855 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2857 ArgOffset += PtrByteSize;
2859 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2860 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
2861 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2862 CallSeqStart.getNode()->getOperand(0),
2864 // This must go outside the CALLSEQ_START..END.
2865 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2866 CallSeqStart.getNode()->getOperand(1));
2867 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2868 NewCallSeqStart.getNode());
2869 Chain = CallSeqStart = NewCallSeqStart;
2870 ArgOffset += PtrByteSize;
2874 // Copy entire object into memory. There are cases where gcc-generated
2875 // code assumes it is there, even if it could be put entirely into
2876 // registers. (This is not what the doc says.)
2877 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2878 CallSeqStart.getNode()->getOperand(0),
2880 // This must go outside the CALLSEQ_START..END.
2881 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2882 CallSeqStart.getNode()->getOperand(1));
2883 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2884 Chain = CallSeqStart = NewCallSeqStart;
2885 // And copy the pieces of it that fit into registers.
2886 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2887 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
2888 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2889 if (GPR_idx != NumGPRs) {
2890 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
2891 MemOpChains.push_back(Load.getValue(1));
2892 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2893 ArgOffset += PtrByteSize;
2895 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2902 switch (Arg.getValueType().getSimpleVT()) {
2903 default: assert(0 && "Unexpected ValueType for argument!");
2906 if (GPR_idx != NumGPRs) {
2907 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2909 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2910 isPPC64, isTailCall, false, MemOpChains,
2911 TailCallArguments, dl);
2914 ArgOffset += PtrByteSize;
2918 if (FPR_idx != NumFPRs) {
2919 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
2922 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2923 MemOpChains.push_back(Store);
2925 // Float varargs are always shadowed in available integer registers
2926 if (GPR_idx != NumGPRs) {
2927 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2928 MemOpChains.push_back(Load.getValue(1));
2929 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2931 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
2932 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
2933 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
2934 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2935 MemOpChains.push_back(Load.getValue(1));
2936 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2939 // If we have any FPRs remaining, we may also have GPRs remaining.
2940 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2942 if (GPR_idx != NumGPRs)
2944 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
2945 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
2949 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2950 isPPC64, isTailCall, false, MemOpChains,
2951 TailCallArguments, dl);
2957 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
2964 // These go aligned on the stack, or in the corresponding R registers
2965 // when within range. The Darwin PPC ABI doc claims they also go in
2966 // V registers; in fact gcc does this only for arguments that are
2967 // prototyped, not for those that match the ... We do it for all
2968 // arguments, seems to work.
2969 while (ArgOffset % 16 !=0) {
2970 ArgOffset += PtrByteSize;
2971 if (GPR_idx != NumGPRs)
2974 // We could elide this store in the case where the object fits
2975 // entirely in R registers. Maybe later.
2976 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2977 DAG.getConstant(ArgOffset, PtrVT));
2978 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2979 MemOpChains.push_back(Store);
2980 if (VR_idx != NumVRs) {
2981 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
2982 MemOpChains.push_back(Load.getValue(1));
2983 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
2986 for (unsigned i=0; i<16; i+=PtrByteSize) {
2987 if (GPR_idx == NumGPRs)
2989 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
2990 DAG.getConstant(i, PtrVT));
2991 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
2992 MemOpChains.push_back(Load.getValue(1));
2993 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2998 // Non-varargs Altivec params generally go in registers, but have
2999 // stack space allocated at the end.
3000 if (VR_idx != NumVRs) {
3001 // Doesn't have GPR space allocated.
3002 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3003 } else if (nAltivecParamsAtEnd==0) {
3004 // We are emitting Altivec params in order.
3005 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3006 isPPC64, isTailCall, true, MemOpChains,
3007 TailCallArguments, dl);
3013 // If all Altivec parameters fit in registers, as they usually do,
3014 // they get stack space following the non-Altivec parameters. We
3015 // don't track this here because nobody below needs it.
3016 // If there are more Altivec parameters than fit in registers emit
3018 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3020 // Offset is aligned; skip 1st 12 params which go in V registers.
3021 ArgOffset = ((ArgOffset+15)/16)*16;
3023 for (unsigned i = 0; i != NumOps; ++i) {
3024 SDValue Arg = TheCall->getArg(i);
3025 MVT ArgType = Arg.getValueType();
3026 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3027 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3030 // We are emitting Altivec params in order.
3031 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3032 isPPC64, isTailCall, true, MemOpChains,
3033 TailCallArguments, dl);
3040 if (!MemOpChains.empty())
3041 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3042 &MemOpChains[0], MemOpChains.size());
3044 // Build a sequence of copy-to-reg nodes chained together with token chain
3045 // and flag operands which copy the outgoing args into the appropriate regs.
3047 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3048 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3049 RegsToPass[i].second, InFlag);
3050 InFlag = Chain.getValue(1);
3054 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3055 FPOp, true, TailCallArguments);
3058 return FinishCall(DAG, TheCall, TM, RegsToPass, Op, InFlag, Chain, Callee,
3062 SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
3063 TargetMachine &TM) {
3064 SmallVector<CCValAssign, 16> RVLocs;
3065 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
3066 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
3067 DebugLoc dl = Op.getDebugLoc();
3068 CCState CCInfo(CC, isVarArg, TM, RVLocs);
3069 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
3071 // If this is the first return lowered for this function, add the regs to the
3072 // liveout set for the function.
3073 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3074 for (unsigned i = 0; i != RVLocs.size(); ++i)
3075 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3078 SDValue Chain = Op.getOperand(0);
3080 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
3081 if (Chain.getOpcode() == PPCISD::TAILCALL) {
3082 SDValue TailCall = Chain;
3083 SDValue TargetAddress = TailCall.getOperand(1);
3084 SDValue StackAdjustment = TailCall.getOperand(2);
3086 assert(((TargetAddress.getOpcode() == ISD::Register &&
3087 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
3088 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
3089 TargetAddress.getOpcode() == ISD::TargetGlobalAddress ||
3090 isa<ConstantSDNode>(TargetAddress)) &&
3091 "Expecting an global address, external symbol, absolute value or register");
3093 assert(StackAdjustment.getOpcode() == ISD::Constant &&
3094 "Expecting a const value");
3096 SmallVector<SDValue,8> Operands;
3097 Operands.push_back(Chain.getOperand(0));
3098 Operands.push_back(TargetAddress);
3099 Operands.push_back(StackAdjustment);
3100 // Copy registers used by the call. Last operand is a flag so it is not
3102 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
3103 Operands.push_back(Chain.getOperand(i));
3105 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Operands[0],
3111 // Copy the result values into the output registers.
3112 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3113 CCValAssign &VA = RVLocs[i];
3114 assert(VA.isRegLoc() && "Can only return in registers!");
3115 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3116 Op.getOperand(i*2+1), Flag);
3117 Flag = Chain.getValue(1);
3121 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3123 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3126 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3127 const PPCSubtarget &Subtarget) {
3128 // When we pop the dynamic allocation we need to restore the SP link.
3129 DebugLoc dl = Op.getDebugLoc();
3131 // Get the corect type for pointers.
3132 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3134 // Construct the stack pointer operand.
3135 bool IsPPC64 = Subtarget.isPPC64();
3136 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
3137 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3139 // Get the operands for the STACKRESTORE.
3140 SDValue Chain = Op.getOperand(0);
3141 SDValue SaveSP = Op.getOperand(1);
3143 // Load the old link SP.
3144 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
3146 // Restore the stack pointer.
3147 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3149 // Store the old link SP.
3150 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
3156 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3157 MachineFunction &MF = DAG.getMachineFunction();
3158 bool IsPPC64 = PPCSubTarget.isPPC64();
3159 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3160 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3162 // Get current frame pointer save index. The users of this index will be
3163 // primarily DYNALLOC instructions.
3164 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3165 int RASI = FI->getReturnAddrSaveIndex();
3167 // If the frame pointer save index hasn't been defined yet.
3169 // Find out what the fix offset of the frame pointer save area.
3170 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
3171 // Allocate the frame index for frame pointer save area.
3172 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
3174 FI->setReturnAddrSaveIndex(RASI);
3176 return DAG.getFrameIndex(RASI, PtrVT);
3180 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3181 MachineFunction &MF = DAG.getMachineFunction();
3182 bool IsPPC64 = PPCSubTarget.isPPC64();
3183 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3184 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3186 // Get current frame pointer save index. The users of this index will be
3187 // primarily DYNALLOC instructions.
3188 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3189 int FPSI = FI->getFramePointerSaveIndex();
3191 // If the frame pointer save index hasn't been defined yet.
3193 // Find out what the fix offset of the frame pointer save area.
3194 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
3197 // Allocate the frame index for frame pointer save area.
3198 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
3200 FI->setFramePointerSaveIndex(FPSI);
3202 return DAG.getFrameIndex(FPSI, PtrVT);
3205 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3207 const PPCSubtarget &Subtarget) {
3209 SDValue Chain = Op.getOperand(0);
3210 SDValue Size = Op.getOperand(1);
3211 DebugLoc dl = Op.getDebugLoc();
3213 // Get the corect type for pointers.
3214 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3216 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3217 DAG.getConstant(0, PtrVT), Size);
3218 // Construct a node for the frame pointer save index.
3219 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3220 // Build a DYNALLOC node.
3221 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3222 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3223 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3226 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3228 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
3229 // Not FP? Not a fsel.
3230 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3231 !Op.getOperand(2).getValueType().isFloatingPoint())
3234 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3236 // Cannot handle SETEQ/SETNE.
3237 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3239 MVT ResVT = Op.getValueType();
3240 MVT CmpVT = Op.getOperand(0).getValueType();
3241 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3242 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3243 DebugLoc dl = Op.getDebugLoc();
3245 // If the RHS of the comparison is a 0.0, we don't need to do the
3246 // subtraction at all.
3247 if (isFloatingPointZero(RHS))
3249 default: break; // SETUO etc aren't handled by fsel.
3252 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3255 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3256 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3257 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3260 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3263 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3264 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3265 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3266 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3271 default: break; // SETUO etc aren't handled by fsel.
3274 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3275 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3276 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3277 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3280 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3281 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3282 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3283 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3286 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3287 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3288 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3289 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3292 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3293 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3294 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3295 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3300 // FIXME: Split this code up when LegalizeDAGTypes lands.
3301 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3303 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3304 SDValue Src = Op.getOperand(0);
3305 if (Src.getValueType() == MVT::f32)
3306 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3309 switch (Op.getValueType().getSimpleVT()) {
3310 default: assert(0 && "Unhandled FP_TO_INT type in custom expander!");
3312 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3317 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3321 // Convert the FP value to an int value through memory.
3322 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3324 // Emit a store to the stack slot.
3325 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
3327 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3329 if (Op.getValueType() == MVT::i32)
3330 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3331 DAG.getConstant(4, FIPtr.getValueType()));
3332 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
3335 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3336 DebugLoc dl = Op.getDebugLoc();
3337 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3338 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3341 if (Op.getOperand(0).getValueType() == MVT::i64) {
3342 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
3343 MVT::f64, Op.getOperand(0));
3344 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3345 if (Op.getValueType() == MVT::f32)
3346 FP = DAG.getNode(ISD::FP_ROUND, dl,
3347 MVT::f32, FP, DAG.getIntPtrConstant(0));
3351 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3352 "Unhandled SINT_TO_FP type in custom expander!");
3353 // Since we only generate this in 64-bit mode, we can take advantage of
3354 // 64-bit registers. In particular, sign extend the input value into the
3355 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3356 // then lfd it and fcfid it.
3357 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3358 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
3359 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3360 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3362 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3365 // STD the extended value into the stack slot.
3366 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
3367 MachineMemOperand::MOStore, 0, 8, 8);
3368 SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other,
3369 DAG.getEntryNode(), Ext64, FIdx,
3370 DAG.getMemOperand(MO));
3371 // Load the value as a double.
3372 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
3374 // FCFID it and return it.
3375 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3376 if (Op.getValueType() == MVT::f32)
3377 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3381 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
3382 DebugLoc dl = Op.getDebugLoc();
3384 The rounding mode is in bits 30:31 of FPSR, and has the following
3391 FLT_ROUNDS, on the other hand, expects the following:
3398 To perform the conversion, we do:
3399 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3402 MachineFunction &MF = DAG.getMachineFunction();
3403 MVT VT = Op.getValueType();
3404 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3405 std::vector<MVT> NodeTys;
3406 SDValue MFFSreg, InFlag;
3408 // Save FP Control Word to register
3409 NodeTys.push_back(MVT::f64); // return register
3410 NodeTys.push_back(MVT::Flag); // unused in this context
3411 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3413 // Save FP register to stack slot
3414 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3415 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3416 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3417 StackSlot, NULL, 0);
3419 // Load FP Control Word from low 32 bits of stack slot.
3420 SDValue Four = DAG.getConstant(4, PtrVT);
3421 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3422 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
3424 // Transform as necessary
3426 DAG.getNode(ISD::AND, dl, MVT::i32,
3427 CWD, DAG.getConstant(3, MVT::i32));
3429 DAG.getNode(ISD::SRL, dl, MVT::i32,
3430 DAG.getNode(ISD::AND, dl, MVT::i32,
3431 DAG.getNode(ISD::XOR, dl, MVT::i32,
3432 CWD, DAG.getConstant(3, MVT::i32)),
3433 DAG.getConstant(3, MVT::i32)),
3434 DAG.getConstant(1, MVT::i32));
3437 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3439 return DAG.getNode((VT.getSizeInBits() < 16 ?
3440 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3443 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
3444 MVT VT = Op.getValueType();
3445 unsigned BitWidth = VT.getSizeInBits();
3446 DebugLoc dl = Op.getDebugLoc();
3447 assert(Op.getNumOperands() == 3 &&
3448 VT == Op.getOperand(1).getValueType() &&
3451 // Expand into a bunch of logical ops. Note that these ops
3452 // depend on the PPC behavior for oversized shift amounts.
3453 SDValue Lo = Op.getOperand(0);
3454 SDValue Hi = Op.getOperand(1);
3455 SDValue Amt = Op.getOperand(2);
3456 MVT AmtVT = Amt.getValueType();
3458 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3459 DAG.getConstant(BitWidth, AmtVT), Amt);
3460 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3461 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3462 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3463 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3464 DAG.getConstant(-BitWidth, AmtVT));
3465 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3466 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3467 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3468 SDValue OutOps[] = { OutLo, OutHi };
3469 return DAG.getMergeValues(OutOps, 2, dl);
3472 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3473 MVT VT = Op.getValueType();
3474 DebugLoc dl = Op.getDebugLoc();
3475 unsigned BitWidth = VT.getSizeInBits();
3476 assert(Op.getNumOperands() == 3 &&
3477 VT == Op.getOperand(1).getValueType() &&
3480 // Expand into a bunch of logical ops. Note that these ops
3481 // depend on the PPC behavior for oversized shift amounts.
3482 SDValue Lo = Op.getOperand(0);
3483 SDValue Hi = Op.getOperand(1);
3484 SDValue Amt = Op.getOperand(2);
3485 MVT AmtVT = Amt.getValueType();
3487 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3488 DAG.getConstant(BitWidth, AmtVT), Amt);
3489 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3490 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3491 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3492 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3493 DAG.getConstant(-BitWidth, AmtVT));
3494 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3495 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3496 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3497 SDValue OutOps[] = { OutLo, OutHi };
3498 return DAG.getMergeValues(OutOps, 2, dl);
3501 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3502 DebugLoc dl = Op.getDebugLoc();
3503 MVT VT = Op.getValueType();
3504 unsigned BitWidth = VT.getSizeInBits();
3505 assert(Op.getNumOperands() == 3 &&
3506 VT == Op.getOperand(1).getValueType() &&
3509 // Expand into a bunch of logical ops, followed by a select_cc.
3510 SDValue Lo = Op.getOperand(0);
3511 SDValue Hi = Op.getOperand(1);
3512 SDValue Amt = Op.getOperand(2);
3513 MVT AmtVT = Amt.getValueType();
3515 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3516 DAG.getConstant(BitWidth, AmtVT), Amt);
3517 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3518 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3519 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3520 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3521 DAG.getConstant(-BitWidth, AmtVT));
3522 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3523 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3524 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3525 Tmp4, Tmp6, ISD::SETLE);
3526 SDValue OutOps[] = { OutLo, OutHi };
3527 return DAG.getMergeValues(OutOps, 2, dl);
3530 //===----------------------------------------------------------------------===//
3531 // Vector related lowering.
3534 /// BuildSplatI - Build a canonical splati of Val with an element size of
3535 /// SplatSize. Cast the result to VT.
3536 static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT,
3537 SelectionDAG &DAG, DebugLoc dl) {
3538 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3540 static const MVT VTys[] = { // canonical VT to use for each size.
3541 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3544 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3546 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3550 MVT CanonicalVT = VTys[SplatSize-1];
3552 // Build a canonical splat for this value.
3553 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3554 SmallVector<SDValue, 8> Ops;
3555 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3556 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3557 &Ops[0], Ops.size());
3558 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3561 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3562 /// specified intrinsic ID.
3563 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3564 SelectionDAG &DAG, DebugLoc dl,
3565 MVT DestVT = MVT::Other) {
3566 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3567 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3568 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3571 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3572 /// specified intrinsic ID.
3573 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3574 SDValue Op2, SelectionDAG &DAG,
3575 DebugLoc dl, MVT DestVT = MVT::Other) {
3576 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3577 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3578 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3582 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3583 /// amount. The result has the specified value type.
3584 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3585 MVT VT, SelectionDAG &DAG, DebugLoc dl) {
3586 // Force LHS/RHS to be the right type.
3587 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3588 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3591 for (unsigned i = 0; i != 16; ++i)
3593 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3594 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3597 // If this is a case we can't handle, return null and let the default
3598 // expansion code take care of it. If we CAN select this case, and if it
3599 // selects to a single instruction, return Op. Otherwise, if we can codegen
3600 // this case more efficiently than a constant pool load, lower it to the
3601 // sequence of ops that should be used.
3602 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3603 DebugLoc dl = Op.getDebugLoc();
3604 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3605 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3607 // Check if this is a splat of a constant value.
3608 APInt APSplatBits, APSplatUndef;
3609 unsigned SplatBitSize;
3611 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3612 HasAnyUndefs) || SplatBitSize > 32)
3615 unsigned SplatBits = APSplatBits.getZExtValue();
3616 unsigned SplatUndef = APSplatUndef.getZExtValue();
3617 unsigned SplatSize = SplatBitSize / 8;
3619 // First, handle single instruction cases.
3622 if (SplatBits == 0) {
3623 // Canonicalize all zero vectors to be v4i32.
3624 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3625 SDValue Z = DAG.getConstant(0, MVT::i32);
3626 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3627 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3632 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3633 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3635 if (SextVal >= -16 && SextVal <= 15)
3636 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3639 // Two instruction sequences.
3641 // If this value is in the range [-32,30] and is even, use:
3642 // tmp = VSPLTI[bhw], result = add tmp, tmp
3643 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3644 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3645 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3646 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3649 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3650 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3652 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3653 // Make -1 and vspltisw -1:
3654 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3656 // Make the VSLW intrinsic, computing 0x8000_0000.
3657 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3660 // xor by OnesV to invert it.
3661 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3662 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3665 // Check to see if this is a wide variety of vsplti*, binop self cases.
3666 static const signed char SplatCsts[] = {
3667 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3668 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3671 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3672 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3673 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3674 int i = SplatCsts[idx];
3676 // Figure out what shift amount will be used by altivec if shifted by i in
3678 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3680 // vsplti + shl self.
3681 if (SextVal == (i << (int)TypeShiftAmt)) {
3682 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3683 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3684 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3685 Intrinsic::ppc_altivec_vslw
3687 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3688 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3691 // vsplti + srl self.
3692 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3693 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3694 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3695 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3696 Intrinsic::ppc_altivec_vsrw
3698 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3699 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3702 // vsplti + sra self.
3703 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3704 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3705 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3706 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3707 Intrinsic::ppc_altivec_vsraw
3709 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3710 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3713 // vsplti + rol self.
3714 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3715 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3716 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3717 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3718 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3719 Intrinsic::ppc_altivec_vrlw
3721 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3722 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3725 // t = vsplti c, result = vsldoi t, t, 1
3726 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3727 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3728 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3730 // t = vsplti c, result = vsldoi t, t, 2
3731 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3732 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3733 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3735 // t = vsplti c, result = vsldoi t, t, 3
3736 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3737 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3738 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3742 // Three instruction sequences.
3744 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3745 if (SextVal >= 0 && SextVal <= 31) {
3746 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3747 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3748 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3749 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3751 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3752 if (SextVal >= -31 && SextVal <= 0) {
3753 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3754 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3755 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3756 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3762 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3763 /// the specified operations to build the shuffle.
3764 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3765 SDValue RHS, SelectionDAG &DAG,
3767 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3768 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3769 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3772 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3784 if (OpNum == OP_COPY) {
3785 if (LHSID == (1*9+2)*9+3) return LHS;
3786 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3790 SDValue OpLHS, OpRHS;
3791 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3792 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3796 default: assert(0 && "Unknown i32 permute!");
3798 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3799 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3800 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3801 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3804 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3805 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3806 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3807 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3810 for (unsigned i = 0; i != 16; ++i)
3811 ShufIdxs[i] = (i&3)+0;
3814 for (unsigned i = 0; i != 16; ++i)
3815 ShufIdxs[i] = (i&3)+4;
3818 for (unsigned i = 0; i != 16; ++i)
3819 ShufIdxs[i] = (i&3)+8;
3822 for (unsigned i = 0; i != 16; ++i)
3823 ShufIdxs[i] = (i&3)+12;
3826 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
3828 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
3830 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
3832 MVT VT = OpLHS.getValueType();
3833 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
3834 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
3835 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
3836 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3839 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3840 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3841 /// return the code it can be lowered into. Worst case, it can always be
3842 /// lowered into a vperm.
3843 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
3844 SelectionDAG &DAG) {
3845 DebugLoc dl = Op.getDebugLoc();
3846 SDValue V1 = Op.getOperand(0);
3847 SDValue V2 = Op.getOperand(1);
3848 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
3849 MVT VT = Op.getValueType();
3851 // Cases that are handled by instructions that take permute immediates
3852 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3853 // selected by the instruction selector.
3854 if (V2.getOpcode() == ISD::UNDEF) {
3855 if (PPC::isSplatShuffleMask(SVOp, 1) ||
3856 PPC::isSplatShuffleMask(SVOp, 2) ||
3857 PPC::isSplatShuffleMask(SVOp, 4) ||
3858 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
3859 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
3860 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
3861 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
3862 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
3863 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
3864 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
3865 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
3866 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
3871 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3872 // and produce a fixed permutation. If any of these match, do not lower to
3874 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
3875 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
3876 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
3877 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
3878 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
3879 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
3880 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
3881 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
3882 PPC::isVMRGHShuffleMask(SVOp, 4, false))
3885 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3886 // perfect shuffle table to emit an optimal matching sequence.
3887 SmallVector<int, 16> PermMask;
3888 SVOp->getMask(PermMask);
3890 unsigned PFIndexes[4];
3891 bool isFourElementShuffle = true;
3892 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3893 unsigned EltNo = 8; // Start out undef.
3894 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3895 if (PermMask[i*4+j] < 0)
3896 continue; // Undef, ignore it.
3898 unsigned ByteSource = PermMask[i*4+j];
3899 if ((ByteSource & 3) != j) {
3900 isFourElementShuffle = false;
3905 EltNo = ByteSource/4;
3906 } else if (EltNo != ByteSource/4) {
3907 isFourElementShuffle = false;
3911 PFIndexes[i] = EltNo;
3914 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3915 // perfect shuffle vector to determine if it is cost effective to do this as
3916 // discrete instructions, or whether we should use a vperm.
3917 if (isFourElementShuffle) {
3918 // Compute the index in the perfect shuffle table.
3919 unsigned PFTableIndex =
3920 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3922 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3923 unsigned Cost = (PFEntry >> 30);
3925 // Determining when to avoid vperm is tricky. Many things affect the cost
3926 // of vperm, particularly how many times the perm mask needs to be computed.
3927 // For example, if the perm mask can be hoisted out of a loop or is already
3928 // used (perhaps because there are multiple permutes with the same shuffle
3929 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3930 // the loop requires an extra register.
3932 // As a compromise, we only emit discrete instructions if the shuffle can be
3933 // generated in 3 or fewer operations. When we have loop information
3934 // available, if this block is within a loop, we should avoid using vperm
3935 // for 3-operation perms and use a constant pool load instead.
3937 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3940 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3941 // vector that will get spilled to the constant pool.
3942 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3944 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3945 // that it is in input element units, not in bytes. Convert now.
3946 MVT EltVT = V1.getValueType().getVectorElementType();
3947 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
3949 SmallVector<SDValue, 16> ResultMask;
3950 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
3951 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
3953 for (unsigned j = 0; j != BytesPerElement; ++j)
3954 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3958 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
3959 &ResultMask[0], ResultMask.size());
3960 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
3963 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3964 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3965 /// information about the intrinsic.
3966 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
3968 unsigned IntrinsicID =
3969 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
3972 switch (IntrinsicID) {
3973 default: return false;
3974 // Comparison predicates.
3975 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3976 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3977 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3978 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3979 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3980 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3981 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3982 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3983 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3984 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3985 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3986 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3987 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3989 // Normal Comparisons.
3990 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3991 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3992 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3993 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3994 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3995 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3996 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3997 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3998 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3999 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4000 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4001 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4002 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4007 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4008 /// lower, do it, otherwise return null.
4009 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4010 SelectionDAG &DAG) {
4011 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4012 // opcode number of the comparison.
4013 DebugLoc dl = Op.getDebugLoc();
4016 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4017 return SDValue(); // Don't custom lower most intrinsics.
4019 // If this is a non-dot comparison, make the VCMP node and we are done.
4021 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4022 Op.getOperand(1), Op.getOperand(2),
4023 DAG.getConstant(CompareOpc, MVT::i32));
4024 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
4027 // Create the PPCISD altivec 'dot' comparison node.
4029 Op.getOperand(2), // LHS
4030 Op.getOperand(3), // RHS
4031 DAG.getConstant(CompareOpc, MVT::i32)
4033 std::vector<MVT> VTs;
4034 VTs.push_back(Op.getOperand(2).getValueType());
4035 VTs.push_back(MVT::Flag);
4036 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4038 // Now that we have the comparison, emit a copy from the CR to a GPR.
4039 // This is flagged to the above dot comparison.
4040 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4041 DAG.getRegister(PPC::CR6, MVT::i32),
4042 CompNode.getValue(1));
4044 // Unpack the result based on how the target uses it.
4045 unsigned BitNo; // Bit # of CR6.
4046 bool InvertBit; // Invert result?
4047 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4048 default: // Can't happen, don't crash on invalid number though.
4049 case 0: // Return the value of the EQ bit of CR6.
4050 BitNo = 0; InvertBit = false;
4052 case 1: // Return the inverted value of the EQ bit of CR6.
4053 BitNo = 0; InvertBit = true;
4055 case 2: // Return the value of the LT bit of CR6.
4056 BitNo = 2; InvertBit = false;
4058 case 3: // Return the inverted value of the LT bit of CR6.
4059 BitNo = 2; InvertBit = true;
4063 // Shift the bit into the low position.
4064 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4065 DAG.getConstant(8-(3-BitNo), MVT::i32));
4067 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4068 DAG.getConstant(1, MVT::i32));
4070 // If we are supposed to, toggle the bit.
4072 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4073 DAG.getConstant(1, MVT::i32));
4077 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4078 SelectionDAG &DAG) {
4079 DebugLoc dl = Op.getDebugLoc();
4080 // Create a stack slot that is 16-byte aligned.
4081 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4082 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
4083 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4084 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4086 // Store the input value into Value#0 of the stack slot.
4087 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4088 Op.getOperand(0), FIdx, NULL, 0);
4090 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0);
4093 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
4094 DebugLoc dl = Op.getDebugLoc();
4095 if (Op.getValueType() == MVT::v4i32) {
4096 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4098 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4099 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4101 SDValue RHSSwap = // = vrlw RHS, 16
4102 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4104 // Shrinkify inputs to v8i16.
4105 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
4106 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
4107 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
4109 // Low parts multiplied together, generating 32-bit results (we ignore the
4111 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4112 LHS, RHS, DAG, dl, MVT::v4i32);
4114 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4115 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4116 // Shift the high parts up 16 bits.
4117 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4119 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4120 } else if (Op.getValueType() == MVT::v8i16) {
4121 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4123 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4125 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4126 LHS, RHS, Zero, DAG, dl);
4127 } else if (Op.getValueType() == MVT::v16i8) {
4128 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4130 // Multiply the even 8-bit parts, producing 16-bit sums.
4131 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4132 LHS, RHS, DAG, dl, MVT::v8i16);
4133 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
4135 // Multiply the odd 8-bit parts, producing 16-bit sums.
4136 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4137 LHS, RHS, DAG, dl, MVT::v8i16);
4138 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
4140 // Merge the results together.
4142 for (unsigned i = 0; i != 8; ++i) {
4144 Ops[i*2+1] = 2*i+1+16;
4146 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4148 LLVM_UNREACHABLE("Unknown mul to lower!");
4152 /// LowerOperation - Provide custom lowering hooks for some operations.
4154 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4155 switch (Op.getOpcode()) {
4156 default: assert(0 && "Wasn't expecting to be able to lower this!");
4157 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4158 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4159 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4160 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4161 case ISD::SETCC: return LowerSETCC(Op, DAG);
4162 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4164 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4165 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4168 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4169 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4171 case ISD::FORMAL_ARGUMENTS:
4172 if (PPCSubTarget.isSVR4ABI()) {
4173 return LowerFORMAL_ARGUMENTS_SVR4(Op, DAG, VarArgsFrameIndex,
4174 VarArgsStackOffset, VarArgsNumGPR,
4175 VarArgsNumFPR, PPCSubTarget);
4177 return LowerFORMAL_ARGUMENTS_Darwin(Op, DAG, VarArgsFrameIndex,
4182 if (PPCSubTarget.isSVR4ABI()) {
4183 return LowerCALL_SVR4(Op, DAG, PPCSubTarget, getTargetMachine());
4185 return LowerCALL_Darwin(Op, DAG, PPCSubTarget, getTargetMachine());
4188 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
4189 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4190 case ISD::DYNAMIC_STACKALLOC:
4191 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4193 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4194 case ISD::FP_TO_UINT:
4195 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4197 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4198 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4200 // Lower 64-bit shifts.
4201 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4202 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4203 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4205 // Vector-related lowering.
4206 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4207 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4208 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4209 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4210 case ISD::MUL: return LowerMUL(Op, DAG);
4212 // Frame & Return address.
4213 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4214 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4219 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4220 SmallVectorImpl<SDValue>&Results,
4221 SelectionDAG &DAG) {
4222 DebugLoc dl = N->getDebugLoc();
4223 switch (N->getOpcode()) {
4225 assert(false && "Do not know how to custom type legalize this operation!");
4227 case ISD::FP_ROUND_INREG: {
4228 assert(N->getValueType(0) == MVT::ppcf128);
4229 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4230 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4231 MVT::f64, N->getOperand(0),
4232 DAG.getIntPtrConstant(0));
4233 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4234 MVT::f64, N->getOperand(0),
4235 DAG.getIntPtrConstant(1));
4237 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4238 // of the long double, and puts FPSCR back the way it was. We do not
4239 // actually model FPSCR.
4240 std::vector<MVT> NodeTys;
4241 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4243 NodeTys.push_back(MVT::f64); // Return register
4244 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
4245 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4246 MFFSreg = Result.getValue(0);
4247 InFlag = Result.getValue(1);
4250 NodeTys.push_back(MVT::Flag); // Returns a flag
4251 Ops[0] = DAG.getConstant(31, MVT::i32);
4253 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4254 InFlag = Result.getValue(0);
4257 NodeTys.push_back(MVT::Flag); // Returns a flag
4258 Ops[0] = DAG.getConstant(30, MVT::i32);
4260 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4261 InFlag = Result.getValue(0);
4264 NodeTys.push_back(MVT::f64); // result of add
4265 NodeTys.push_back(MVT::Flag); // Returns a flag
4269 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4270 FPreg = Result.getValue(0);
4271 InFlag = Result.getValue(1);
4274 NodeTys.push_back(MVT::f64);
4275 Ops[0] = DAG.getConstant(1, MVT::i32);
4279 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4280 FPreg = Result.getValue(0);
4282 // We know the low half is about to be thrown away, so just use something
4284 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4288 case ISD::FP_TO_SINT:
4289 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4295 //===----------------------------------------------------------------------===//
4296 // Other Lowering Code
4297 //===----------------------------------------------------------------------===//
4300 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4301 bool is64bit, unsigned BinOpcode) const {
4302 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4303 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4305 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4306 MachineFunction *F = BB->getParent();
4307 MachineFunction::iterator It = BB;
4310 unsigned dest = MI->getOperand(0).getReg();
4311 unsigned ptrA = MI->getOperand(1).getReg();
4312 unsigned ptrB = MI->getOperand(2).getReg();
4313 unsigned incr = MI->getOperand(3).getReg();
4314 DebugLoc dl = MI->getDebugLoc();
4316 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4317 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4318 F->insert(It, loopMBB);
4319 F->insert(It, exitMBB);
4320 exitMBB->transferSuccessors(BB);
4322 MachineRegisterInfo &RegInfo = F->getRegInfo();
4323 unsigned TmpReg = (!BinOpcode) ? incr :
4324 RegInfo.createVirtualRegister(
4325 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4326 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4330 // fallthrough --> loopMBB
4331 BB->addSuccessor(loopMBB);
4334 // l[wd]arx dest, ptr
4335 // add r0, dest, incr
4336 // st[wd]cx. r0, ptr
4338 // fallthrough --> exitMBB
4340 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4341 .addReg(ptrA).addReg(ptrB);
4343 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4344 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4345 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4346 BuildMI(BB, dl, TII->get(PPC::BCC))
4347 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4348 BB->addSuccessor(loopMBB);
4349 BB->addSuccessor(exitMBB);
4358 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4359 MachineBasicBlock *BB,
4360 bool is8bit, // operation
4361 unsigned BinOpcode) const {
4362 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4363 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4364 // In 64 bit mode we have to use 64 bits for addresses, even though the
4365 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4366 // registers without caring whether they're 32 or 64, but here we're
4367 // doing actual arithmetic on the addresses.
4368 bool is64bit = PPCSubTarget.isPPC64();
4370 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4371 MachineFunction *F = BB->getParent();
4372 MachineFunction::iterator It = BB;
4375 unsigned dest = MI->getOperand(0).getReg();
4376 unsigned ptrA = MI->getOperand(1).getReg();
4377 unsigned ptrB = MI->getOperand(2).getReg();
4378 unsigned incr = MI->getOperand(3).getReg();
4379 DebugLoc dl = MI->getDebugLoc();
4381 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4382 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4383 F->insert(It, loopMBB);
4384 F->insert(It, exitMBB);
4385 exitMBB->transferSuccessors(BB);
4387 MachineRegisterInfo &RegInfo = F->getRegInfo();
4388 const TargetRegisterClass *RC =
4389 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4390 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4391 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4392 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4393 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4394 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4395 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4396 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4397 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4398 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4399 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4400 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4401 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4403 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4407 // fallthrough --> loopMBB
4408 BB->addSuccessor(loopMBB);
4410 // The 4-byte load must be aligned, while a char or short may be
4411 // anywhere in the word. Hence all this nasty bookkeeping code.
4412 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4413 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4414 // xori shift, shift1, 24 [16]
4415 // rlwinm ptr, ptr1, 0, 0, 29
4416 // slw incr2, incr, shift
4417 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4418 // slw mask, mask2, shift
4420 // lwarx tmpDest, ptr
4421 // add tmp, tmpDest, incr2
4422 // andc tmp2, tmpDest, mask
4423 // and tmp3, tmp, mask
4424 // or tmp4, tmp3, tmp2
4427 // fallthrough --> exitMBB
4428 // srw dest, tmpDest, shift
4430 if (ptrA!=PPC::R0) {
4431 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4432 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4433 .addReg(ptrA).addReg(ptrB);
4437 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4438 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4439 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4440 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4442 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4443 .addReg(Ptr1Reg).addImm(0).addImm(61);
4445 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4446 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4447 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4448 .addReg(incr).addReg(ShiftReg);
4450 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4452 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4453 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4455 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4456 .addReg(Mask2Reg).addReg(ShiftReg);
4459 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4460 .addReg(PPC::R0).addReg(PtrReg);
4462 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4463 .addReg(Incr2Reg).addReg(TmpDestReg);
4464 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4465 .addReg(TmpDestReg).addReg(MaskReg);
4466 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4467 .addReg(TmpReg).addReg(MaskReg);
4468 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4469 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4470 BuildMI(BB, dl, TII->get(PPC::STWCX))
4471 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4472 BuildMI(BB, dl, TII->get(PPC::BCC))
4473 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4474 BB->addSuccessor(loopMBB);
4475 BB->addSuccessor(exitMBB);
4480 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4485 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4486 MachineBasicBlock *BB) const {
4487 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4489 // To "insert" these instructions we actually have to insert their
4490 // control-flow patterns.
4491 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4492 MachineFunction::iterator It = BB;
4495 MachineFunction *F = BB->getParent();
4497 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4498 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4499 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4500 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4501 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4503 // The incoming instruction knows the destination vreg to set, the
4504 // condition code register to branch on, the true/false values to
4505 // select between, and a branch opcode to use.
4510 // cmpTY ccX, r1, r2
4512 // fallthrough --> copy0MBB
4513 MachineBasicBlock *thisMBB = BB;
4514 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4515 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4516 unsigned SelectPred = MI->getOperand(4).getImm();
4517 DebugLoc dl = MI->getDebugLoc();
4518 BuildMI(BB, dl, TII->get(PPC::BCC))
4519 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4520 F->insert(It, copy0MBB);
4521 F->insert(It, sinkMBB);
4522 // Update machine-CFG edges by transferring all successors of the current
4523 // block to the new block which will contain the Phi node for the select.
4524 sinkMBB->transferSuccessors(BB);
4525 // Next, add the true and fallthrough blocks as its successors.
4526 BB->addSuccessor(copy0MBB);
4527 BB->addSuccessor(sinkMBB);
4530 // %FalseValue = ...
4531 // # fallthrough to sinkMBB
4534 // Update machine-CFG edges
4535 BB->addSuccessor(sinkMBB);
4538 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4541 BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4542 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4543 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4545 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4546 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4547 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4548 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4549 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4550 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4551 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4552 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4554 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4555 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4556 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4557 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4558 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4559 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4560 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4561 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4563 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4564 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4565 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4566 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4567 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4568 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4569 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4570 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4572 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4573 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4574 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4575 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4576 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4577 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4578 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4579 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4581 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4582 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4583 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4584 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4585 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4586 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4587 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4588 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4590 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4591 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4592 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4593 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4594 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4595 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4596 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4597 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4599 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4600 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4601 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4602 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4603 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4604 BB = EmitAtomicBinary(MI, BB, false, 0);
4605 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4606 BB = EmitAtomicBinary(MI, BB, true, 0);
4608 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4609 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4610 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4612 unsigned dest = MI->getOperand(0).getReg();
4613 unsigned ptrA = MI->getOperand(1).getReg();
4614 unsigned ptrB = MI->getOperand(2).getReg();
4615 unsigned oldval = MI->getOperand(3).getReg();
4616 unsigned newval = MI->getOperand(4).getReg();
4617 DebugLoc dl = MI->getDebugLoc();
4619 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4620 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4621 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4622 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4623 F->insert(It, loop1MBB);
4624 F->insert(It, loop2MBB);
4625 F->insert(It, midMBB);
4626 F->insert(It, exitMBB);
4627 exitMBB->transferSuccessors(BB);
4631 // fallthrough --> loopMBB
4632 BB->addSuccessor(loop1MBB);
4635 // l[wd]arx dest, ptr
4636 // cmp[wd] dest, oldval
4639 // st[wd]cx. newval, ptr
4643 // st[wd]cx. dest, ptr
4646 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4647 .addReg(ptrA).addReg(ptrB);
4648 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4649 .addReg(oldval).addReg(dest);
4650 BuildMI(BB, dl, TII->get(PPC::BCC))
4651 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4652 BB->addSuccessor(loop2MBB);
4653 BB->addSuccessor(midMBB);
4656 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4657 .addReg(newval).addReg(ptrA).addReg(ptrB);
4658 BuildMI(BB, dl, TII->get(PPC::BCC))
4659 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4660 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4661 BB->addSuccessor(loop1MBB);
4662 BB->addSuccessor(exitMBB);
4665 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4666 .addReg(dest).addReg(ptrA).addReg(ptrB);
4667 BB->addSuccessor(exitMBB);
4672 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4673 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4674 // We must use 64-bit registers for addresses when targeting 64-bit,
4675 // since we're actually doing arithmetic on them. Other registers
4677 bool is64bit = PPCSubTarget.isPPC64();
4678 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4680 unsigned dest = MI->getOperand(0).getReg();
4681 unsigned ptrA = MI->getOperand(1).getReg();
4682 unsigned ptrB = MI->getOperand(2).getReg();
4683 unsigned oldval = MI->getOperand(3).getReg();
4684 unsigned newval = MI->getOperand(4).getReg();
4685 DebugLoc dl = MI->getDebugLoc();
4687 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4688 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4689 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4690 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4691 F->insert(It, loop1MBB);
4692 F->insert(It, loop2MBB);
4693 F->insert(It, midMBB);
4694 F->insert(It, exitMBB);
4695 exitMBB->transferSuccessors(BB);
4697 MachineRegisterInfo &RegInfo = F->getRegInfo();
4698 const TargetRegisterClass *RC =
4699 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4700 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4701 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4702 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4703 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4704 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4705 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4706 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4707 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4708 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4709 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4710 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4711 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4712 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4713 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4715 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4718 // fallthrough --> loopMBB
4719 BB->addSuccessor(loop1MBB);
4721 // The 4-byte load must be aligned, while a char or short may be
4722 // anywhere in the word. Hence all this nasty bookkeeping code.
4723 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4724 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4725 // xori shift, shift1, 24 [16]
4726 // rlwinm ptr, ptr1, 0, 0, 29
4727 // slw newval2, newval, shift
4728 // slw oldval2, oldval,shift
4729 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4730 // slw mask, mask2, shift
4731 // and newval3, newval2, mask
4732 // and oldval3, oldval2, mask
4734 // lwarx tmpDest, ptr
4735 // and tmp, tmpDest, mask
4736 // cmpw tmp, oldval3
4739 // andc tmp2, tmpDest, mask
4740 // or tmp4, tmp2, newval3
4745 // stwcx. tmpDest, ptr
4747 // srw dest, tmpDest, shift
4748 if (ptrA!=PPC::R0) {
4749 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4750 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4751 .addReg(ptrA).addReg(ptrB);
4755 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4756 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4757 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4758 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4760 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4761 .addReg(Ptr1Reg).addImm(0).addImm(61);
4763 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4764 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4765 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4766 .addReg(newval).addReg(ShiftReg);
4767 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4768 .addReg(oldval).addReg(ShiftReg);
4770 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4772 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4773 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4774 .addReg(Mask3Reg).addImm(65535);
4776 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4777 .addReg(Mask2Reg).addReg(ShiftReg);
4778 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
4779 .addReg(NewVal2Reg).addReg(MaskReg);
4780 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
4781 .addReg(OldVal2Reg).addReg(MaskReg);
4784 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4785 .addReg(PPC::R0).addReg(PtrReg);
4786 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
4787 .addReg(TmpDestReg).addReg(MaskReg);
4788 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
4789 .addReg(TmpReg).addReg(OldVal3Reg);
4790 BuildMI(BB, dl, TII->get(PPC::BCC))
4791 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4792 BB->addSuccessor(loop2MBB);
4793 BB->addSuccessor(midMBB);
4796 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
4797 .addReg(TmpDestReg).addReg(MaskReg);
4798 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
4799 .addReg(Tmp2Reg).addReg(NewVal3Reg);
4800 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4801 .addReg(PPC::R0).addReg(PtrReg);
4802 BuildMI(BB, dl, TII->get(PPC::BCC))
4803 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4804 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4805 BB->addSuccessor(loop1MBB);
4806 BB->addSuccessor(exitMBB);
4809 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4810 .addReg(PPC::R0).addReg(PtrReg);
4811 BB->addSuccessor(exitMBB);
4816 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4818 assert(0 && "Unexpected instr type to insert");
4821 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4825 //===----------------------------------------------------------------------===//
4826 // Target Optimization Hooks
4827 //===----------------------------------------------------------------------===//
4829 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4830 DAGCombinerInfo &DCI) const {
4831 TargetMachine &TM = getTargetMachine();
4832 SelectionDAG &DAG = DCI.DAG;
4833 DebugLoc dl = N->getDebugLoc();
4834 switch (N->getOpcode()) {
4837 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4838 if (C->getZExtValue() == 0) // 0 << V -> 0.
4839 return N->getOperand(0);
4843 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4844 if (C->getZExtValue() == 0) // 0 >>u V -> 0.
4845 return N->getOperand(0);
4849 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4850 if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
4851 C->isAllOnesValue()) // -1 >>s V -> -1.
4852 return N->getOperand(0);
4856 case ISD::SINT_TO_FP:
4857 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4858 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4859 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4860 // We allow the src/dst to be either f32/f64, but the intermediate
4861 // type must be i64.
4862 if (N->getOperand(0).getValueType() == MVT::i64 &&
4863 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4864 SDValue Val = N->getOperand(0).getOperand(0);
4865 if (Val.getValueType() == MVT::f32) {
4866 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4867 DCI.AddToWorklist(Val.getNode());
4870 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
4871 DCI.AddToWorklist(Val.getNode());
4872 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
4873 DCI.AddToWorklist(Val.getNode());
4874 if (N->getValueType(0) == MVT::f32) {
4875 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
4876 DAG.getIntPtrConstant(0));
4877 DCI.AddToWorklist(Val.getNode());
4880 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4881 // If the intermediate type is i32, we can avoid the load/store here
4888 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4889 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4890 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4891 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4892 N->getOperand(1).getValueType() == MVT::i32 &&
4893 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4894 SDValue Val = N->getOperand(1).getOperand(0);
4895 if (Val.getValueType() == MVT::f32) {
4896 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4897 DCI.AddToWorklist(Val.getNode());
4899 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
4900 DCI.AddToWorklist(Val.getNode());
4902 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
4903 N->getOperand(2), N->getOperand(3));
4904 DCI.AddToWorklist(Val.getNode());
4908 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4909 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
4910 N->getOperand(1).getNode()->hasOneUse() &&
4911 (N->getOperand(1).getValueType() == MVT::i32 ||
4912 N->getOperand(1).getValueType() == MVT::i16)) {
4913 SDValue BSwapOp = N->getOperand(1).getOperand(0);
4914 // Do an any-extend to 32-bits if this is a half-word input.
4915 if (BSwapOp.getValueType() == MVT::i16)
4916 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
4918 return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0),
4919 BSwapOp, N->getOperand(2), N->getOperand(3),
4920 DAG.getValueType(N->getOperand(1).getValueType()));
4924 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4925 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
4926 N->getOperand(0).hasOneUse() &&
4927 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4928 SDValue Load = N->getOperand(0);
4929 LoadSDNode *LD = cast<LoadSDNode>(Load);
4930 // Create the byte-swapping load.
4931 std::vector<MVT> VTs;
4932 VTs.push_back(MVT::i32);
4933 VTs.push_back(MVT::Other);
4934 SDValue MO = DAG.getMemOperand(LD->getMemOperand());
4936 LD->getChain(), // Chain
4937 LD->getBasePtr(), // Ptr
4939 DAG.getValueType(N->getValueType(0)) // VT
4941 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4);
4943 // If this is an i16 load, insert the truncate.
4944 SDValue ResVal = BSLoad;
4945 if (N->getValueType(0) == MVT::i16)
4946 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
4948 // First, combine the bswap away. This makes the value produced by the
4950 DCI.CombineTo(N, ResVal);
4952 // Next, combine the load away, we give it a bogus result value but a real
4953 // chain result. The result value is dead because the bswap is dead.
4954 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
4956 // Return N so it doesn't get rechecked!
4957 return SDValue(N, 0);
4961 case PPCISD::VCMP: {
4962 // If a VCMPo node already exists with exactly the same operands as this
4963 // node, use its result instead of this node (VCMPo computes both a CR6 and
4964 // a normal output).
4966 if (!N->getOperand(0).hasOneUse() &&
4967 !N->getOperand(1).hasOneUse() &&
4968 !N->getOperand(2).hasOneUse()) {
4970 // Scan all of the users of the LHS, looking for VCMPo's that match.
4971 SDNode *VCMPoNode = 0;
4973 SDNode *LHSN = N->getOperand(0).getNode();
4974 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
4976 if (UI->getOpcode() == PPCISD::VCMPo &&
4977 UI->getOperand(1) == N->getOperand(1) &&
4978 UI->getOperand(2) == N->getOperand(2) &&
4979 UI->getOperand(0) == N->getOperand(0)) {
4984 // If there is no VCMPo node, or if the flag value has a single use, don't
4986 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
4989 // Look at the (necessarily single) use of the flag value. If it has a
4990 // chain, this transformation is more complex. Note that multiple things
4991 // could use the value result, which we should ignore.
4992 SDNode *FlagUser = 0;
4993 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
4994 FlagUser == 0; ++UI) {
4995 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
4997 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
4998 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5005 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5006 // give up for right now.
5007 if (FlagUser->getOpcode() == PPCISD::MFCR)
5008 return SDValue(VCMPoNode, 0);
5013 // If this is a branch on an altivec predicate comparison, lower this so
5014 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5015 // lowering is done pre-legalize, because the legalizer lowers the predicate
5016 // compare down to code that is difficult to reassemble.
5017 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5018 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5022 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5023 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5024 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5025 assert(isDot && "Can't compare against a vector result!");
5027 // If this is a comparison against something other than 0/1, then we know
5028 // that the condition is never/always true.
5029 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5030 if (Val != 0 && Val != 1) {
5031 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5032 return N->getOperand(0);
5033 // Always !=, turn it into an unconditional branch.
5034 return DAG.getNode(ISD::BR, dl, MVT::Other,
5035 N->getOperand(0), N->getOperand(4));
5038 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5040 // Create the PPCISD altivec 'dot' comparison node.
5041 std::vector<MVT> VTs;
5043 LHS.getOperand(2), // LHS of compare
5044 LHS.getOperand(3), // RHS of compare
5045 DAG.getConstant(CompareOpc, MVT::i32)
5047 VTs.push_back(LHS.getOperand(2).getValueType());
5048 VTs.push_back(MVT::Flag);
5049 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5051 // Unpack the result based on how the target uses it.
5052 PPC::Predicate CompOpc;
5053 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5054 default: // Can't happen, don't crash on invalid number though.
5055 case 0: // Branch on the value of the EQ bit of CR6.
5056 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5058 case 1: // Branch on the inverted value of the EQ bit of CR6.
5059 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5061 case 2: // Branch on the value of the LT bit of CR6.
5062 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5064 case 3: // Branch on the inverted value of the LT bit of CR6.
5065 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5069 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5070 DAG.getConstant(CompOpc, MVT::i32),
5071 DAG.getRegister(PPC::CR6, MVT::i32),
5072 N->getOperand(4), CompNode.getValue(1));
5081 //===----------------------------------------------------------------------===//
5082 // Inline Assembly Support
5083 //===----------------------------------------------------------------------===//
5085 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5089 const SelectionDAG &DAG,
5090 unsigned Depth) const {
5091 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5092 switch (Op.getOpcode()) {
5094 case PPCISD::LBRX: {
5095 // lhbrx is known to have the top bits cleared out.
5096 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
5097 KnownZero = 0xFFFF0000;
5100 case ISD::INTRINSIC_WO_CHAIN: {
5101 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5103 case Intrinsic::ppc_altivec_vcmpbfp_p:
5104 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5105 case Intrinsic::ppc_altivec_vcmpequb_p:
5106 case Intrinsic::ppc_altivec_vcmpequh_p:
5107 case Intrinsic::ppc_altivec_vcmpequw_p:
5108 case Intrinsic::ppc_altivec_vcmpgefp_p:
5109 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5110 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5111 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5112 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5113 case Intrinsic::ppc_altivec_vcmpgtub_p:
5114 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5115 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5116 KnownZero = ~1U; // All bits but the low one are known to be zero.
5124 /// getConstraintType - Given a constraint, return the type of
5125 /// constraint it is for this target.
5126 PPCTargetLowering::ConstraintType
5127 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5128 if (Constraint.size() == 1) {
5129 switch (Constraint[0]) {
5136 return C_RegisterClass;
5139 return TargetLowering::getConstraintType(Constraint);
5142 std::pair<unsigned, const TargetRegisterClass*>
5143 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5145 if (Constraint.size() == 1) {
5146 // GCC RS6000 Constraint Letters
5147 switch (Constraint[0]) {
5150 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5151 return std::make_pair(0U, PPC::G8RCRegisterClass);
5152 return std::make_pair(0U, PPC::GPRCRegisterClass);
5155 return std::make_pair(0U, PPC::F4RCRegisterClass);
5156 else if (VT == MVT::f64)
5157 return std::make_pair(0U, PPC::F8RCRegisterClass);
5160 return std::make_pair(0U, PPC::VRRCRegisterClass);
5162 return std::make_pair(0U, PPC::CRRCRegisterClass);
5166 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5170 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5171 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
5172 /// it means one of the asm constraint of the inline asm instruction being
5173 /// processed is 'm'.
5174 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5176 std::vector<SDValue>&Ops,
5177 SelectionDAG &DAG) const {
5178 SDValue Result(0,0);
5189 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5190 if (!CST) return; // Must be an immediate to match.
5191 unsigned Value = CST->getZExtValue();
5193 default: assert(0 && "Unknown constraint letter!");
5194 case 'I': // "I" is a signed 16-bit constant.
5195 if ((short)Value == (int)Value)
5196 Result = DAG.getTargetConstant(Value, Op.getValueType());
5198 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5199 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5200 if ((short)Value == 0)
5201 Result = DAG.getTargetConstant(Value, Op.getValueType());
5203 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5204 if ((Value >> 16) == 0)
5205 Result = DAG.getTargetConstant(Value, Op.getValueType());
5207 case 'M': // "M" is a constant that is greater than 31.
5209 Result = DAG.getTargetConstant(Value, Op.getValueType());
5211 case 'N': // "N" is a positive constant that is an exact power of two.
5212 if ((int)Value > 0 && isPowerOf2_32(Value))
5213 Result = DAG.getTargetConstant(Value, Op.getValueType());
5215 case 'O': // "O" is the constant zero.
5217 Result = DAG.getTargetConstant(Value, Op.getValueType());
5219 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5220 if ((short)-Value == (int)-Value)
5221 Result = DAG.getTargetConstant(Value, Op.getValueType());
5228 if (Result.getNode()) {
5229 Ops.push_back(Result);
5233 // Handle standard constraint letters.
5234 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
5237 // isLegalAddressingMode - Return true if the addressing mode represented
5238 // by AM is legal for this target, for a load/store of the specified type.
5239 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5240 const Type *Ty) const {
5241 // FIXME: PPC does not allow r+i addressing modes for vectors!
5243 // PPC allows a sign-extended 16-bit immediate field.
5244 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5247 // No global is ever allowed as a base.
5251 // PPC only support r+r,
5253 case 0: // "r+i" or just "i", depending on HasBaseReg.
5256 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5258 // Otherwise we have r+r or r+i.
5261 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5263 // Allow 2*r as r+r.
5266 // No other scales are supported.
5273 /// isLegalAddressImmediate - Return true if the integer value can be used
5274 /// as the offset of the target addressing mode for load / store of the
5276 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5277 // PPC allows a sign-extended 16-bit immediate field.
5278 return (V > -(1 << 16) && V < (1 << 16)-1);
5281 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5285 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5286 DebugLoc dl = Op.getDebugLoc();
5287 // Depths > 0 not supported yet!
5288 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5291 MachineFunction &MF = DAG.getMachineFunction();
5292 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5294 // Just load the return address off the stack.
5295 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5297 // Make sure the function really does not optimize away the store of the RA
5299 FuncInfo->setLRStoreRequired();
5300 return DAG.getLoad(getPointerTy(), dl,
5301 DAG.getEntryNode(), RetAddrFI, NULL, 0);
5304 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5305 DebugLoc dl = Op.getDebugLoc();
5306 // Depths > 0 not supported yet!
5307 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5310 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5311 bool isPPC64 = PtrVT == MVT::i64;
5313 MachineFunction &MF = DAG.getMachineFunction();
5314 MachineFrameInfo *MFI = MF.getFrameInfo();
5315 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
5316 && MFI->getStackSize();
5319 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
5322 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
5327 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5328 // The PowerPC target isn't yet aware of offsets.
5332 MVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
5333 bool isSrcConst, bool isSrcStr,
5334 SelectionDAG &DAG) const {
5335 if (this->PPCSubTarget.isPPC64()) {