1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Target/TargetOptions.h"
29 /// VRRegNo - Map from a numbered VR register to its enum value.
31 static const uint16_t VRRegNo[] = {
32 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
33 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
34 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
35 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
38 /// RemoveVRSaveCode - We have found that this function does not need any code
39 /// to manipulate the VRSAVE register, even though it uses vector registers.
40 /// This can happen when the only registers used are known to be live in or out
41 /// of the function. Remove all of the VRSAVE related code from the function.
42 /// FIXME: The removal of the code results in a compile failure at -O0 when the
43 /// function contains a function call, as the GPR containing original VRSAVE
44 /// contents is spilled and reloaded around the call. Without the prolog code,
45 /// the spill instruction refers to an undefined register. This code needs
46 /// to account for all uses of that GPR.
47 static void RemoveVRSaveCode(MachineInstr *MI) {
48 MachineBasicBlock *Entry = MI->getParent();
49 MachineFunction *MF = Entry->getParent();
51 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
52 MachineBasicBlock::iterator MBBI = MI;
54 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
55 MBBI->eraseFromParent();
57 bool RemovedAllMTVRSAVEs = true;
58 // See if we can find and remove the MTVRSAVE instruction from all of the
60 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
61 // If last instruction is a return instruction, add an epilogue
62 if (!I->empty() && I->back().isReturn()) {
64 for (MBBI = I->end(); MBBI != I->begin(); ) {
66 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
67 MBBI->eraseFromParent(); // remove it.
72 RemovedAllMTVRSAVEs &= FoundIt;
76 // If we found and removed all MTVRSAVE instructions, remove the read of
78 if (RemovedAllMTVRSAVEs) {
80 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
82 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
83 MBBI->eraseFromParent();
86 // Finally, nuke the UPDATE_VRSAVE.
87 MI->eraseFromParent();
90 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
91 // instruction selector. Based on the vector registers that have been used,
92 // transform this into the appropriate ORI instruction.
93 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
94 MachineFunction *MF = MI->getParent()->getParent();
95 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
96 DebugLoc dl = MI->getDebugLoc();
98 unsigned UsedRegMask = 0;
99 for (unsigned i = 0; i != 32; ++i)
100 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
101 UsedRegMask |= 1 << (31-i);
103 // Live in and live out values already must be in the mask, so don't bother
105 for (MachineRegisterInfo::livein_iterator
106 I = MF->getRegInfo().livein_begin(),
107 E = MF->getRegInfo().livein_end(); I != E; ++I) {
108 unsigned RegNo = TRI->getEncodingValue(I->first);
109 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
110 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
113 // Live out registers appear as use operands on return instructions.
114 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
115 UsedRegMask != 0 && BI != BE; ++BI) {
116 const MachineBasicBlock &MBB = *BI;
117 if (MBB.empty() || !MBB.back().isReturn())
119 const MachineInstr &Ret = MBB.back();
120 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
121 const MachineOperand &MO = Ret.getOperand(I);
122 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
124 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
125 UsedRegMask &= ~(1 << (31-RegNo));
129 // If no registers are used, turn this into a copy.
130 if (UsedRegMask == 0) {
131 // Remove all VRSAVE code.
132 RemoveVRSaveCode(MI);
136 unsigned SrcReg = MI->getOperand(1).getReg();
137 unsigned DstReg = MI->getOperand(0).getReg();
139 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
140 if (DstReg != SrcReg)
141 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
143 .addImm(UsedRegMask);
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
146 .addReg(SrcReg, RegState::Kill)
147 .addImm(UsedRegMask);
148 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
149 if (DstReg != SrcReg)
150 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
152 .addImm(UsedRegMask >> 16);
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
155 .addReg(SrcReg, RegState::Kill)
156 .addImm(UsedRegMask >> 16);
158 if (DstReg != SrcReg)
159 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
161 .addImm(UsedRegMask >> 16);
163 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
164 .addReg(SrcReg, RegState::Kill)
165 .addImm(UsedRegMask >> 16);
167 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
168 .addReg(DstReg, RegState::Kill)
169 .addImm(UsedRegMask & 0xFFFF);
172 // Remove the old UPDATE_VRSAVE instruction.
173 MI->eraseFromParent();
176 static bool spillsCR(const MachineFunction &MF) {
177 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
178 return FuncInfo->isCRSpilled();
181 static bool spillsVRSAVE(const MachineFunction &MF) {
182 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
183 return FuncInfo->isVRSAVESpilled();
186 static bool hasSpills(const MachineFunction &MF) {
187 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
188 return FuncInfo->hasSpills();
191 static bool hasNonRISpills(const MachineFunction &MF) {
192 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
193 return FuncInfo->hasNonRISpills();
196 /// determineFrameLayout - Determine the size of the frame and maximum call
198 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
200 bool UseEstimate) const {
201 MachineFrameInfo *MFI = MF.getFrameInfo();
203 // Get the number of bytes to allocate from the FrameInfo
205 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
207 // Get stack alignments. The frame must be aligned to the greatest of these:
208 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
209 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
210 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
212 const PPCRegisterInfo *RegInfo =
213 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
215 // If we are a leaf function, and use up to 224 bytes of stack space,
216 // don't have a frame pointer, calls, or dynamic alloca then we do not need
217 // to adjust the stack pointer (we fit in the Red Zone).
218 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
219 // stackless code if all local vars are reg-allocated.
220 bool DisableRedZone = MF.getFunction()->getAttributes().
221 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
222 if (!DisableRedZone &&
223 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
224 !Subtarget.isSVR4ABI() || // allocated locals.
226 FrameSize <= 224 && // Fits in red zone.
227 !MFI->hasVarSizedObjects() && // No dynamic alloca.
228 !MFI->adjustsStack() && // No calls.
229 !RegInfo->hasBasePointer(MF)) { // No special alignment.
232 MFI->setStackSize(0);
236 // Get the maximum call frame size of all the calls.
237 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
239 // Maximum call frame needs to be at least big enough for linkage and 8 args.
240 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
241 Subtarget.isDarwinABI());
242 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
244 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
245 // that allocations will be aligned.
246 if (MFI->hasVarSizedObjects())
247 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
249 // Update maximum call frame size.
251 MFI->setMaxCallFrameSize(maxCallFrameSize);
253 // Include call frame size in total.
254 FrameSize += maxCallFrameSize;
256 // Make sure the frame is aligned.
257 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
259 // Update frame info.
261 MFI->setStackSize(FrameSize);
266 // hasFP - Return true if the specified function actually has a dedicated frame
268 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
269 const MachineFrameInfo *MFI = MF.getFrameInfo();
270 // FIXME: This is pretty much broken by design: hasFP() might be called really
271 // early, before the stack layout was calculated and thus hasFP() might return
272 // true or false here depending on the time of call.
273 return (MFI->getStackSize()) && needsFP(MF);
276 // needsFP - Return true if the specified function should have a dedicated frame
277 // pointer register. This is true if the function has variable sized allocas or
278 // if frame pointer elimination is disabled.
279 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
280 const MachineFrameInfo *MFI = MF.getFrameInfo();
282 // Naked functions have no stack frame pushed, so we don't have a frame
284 if (MF.getFunction()->getAttributes().hasAttribute(
285 AttributeSet::FunctionIndex, Attribute::Naked))
288 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
289 MFI->hasVarSizedObjects() ||
290 (MF.getTarget().Options.GuaranteedTailCallOpt &&
291 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
294 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
295 bool is31 = needsFP(MF);
296 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
297 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
299 const PPCRegisterInfo *RegInfo =
300 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
301 bool HasBP = RegInfo->hasBasePointer(MF);
302 unsigned BPReg = HasBP ? (unsigned) PPC::R30 : FPReg;
303 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
305 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
307 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
309 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
310 MachineOperand &MO = MBBI->getOperand(I);
314 switch (MO.getReg()) {
333 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
334 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
335 MachineBasicBlock::iterator MBBI = MBB.begin();
336 MachineFrameInfo *MFI = MF.getFrameInfo();
337 const PPCInstrInfo &TII =
338 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
339 const PPCRegisterInfo *RegInfo =
340 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
342 MachineModuleInfo &MMI = MF.getMMI();
343 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
345 bool needsFrameMoves = MMI.hasDebugInfo() ||
346 MF.getFunction()->needsUnwindTableEntry();
348 // Get processor type.
349 bool isPPC64 = Subtarget.isPPC64();
351 bool isDarwinABI = Subtarget.isDarwinABI();
352 bool isSVR4ABI = Subtarget.isSVR4ABI();
353 assert((isDarwinABI || isSVR4ABI) &&
354 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
356 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
359 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
360 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
361 HandleVRSaveUpdate(MBBI, TII);
366 // Move MBBI back to the beginning of the function.
369 // Work out frame sizes.
370 unsigned FrameSize = determineFrameLayout(MF);
371 int NegFrameSize = -FrameSize;
372 if (!isInt<32>(NegFrameSize))
373 llvm_unreachable("Unhandled stack size!");
375 if (MFI->isFrameAddressTaken())
376 replaceFPWithRealFP(MF);
378 // Check if the link register (LR) must be saved.
379 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
380 bool MustSaveLR = FI->mustSaveLR();
381 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
382 // Do we have a frame pointer and/or base pointer for this function?
383 bool HasFP = hasFP(MF);
384 bool HasBP = RegInfo->hasBasePointer(MF);
386 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
387 unsigned BPReg = isPPC64 ? PPC::X30 : PPC::R30;
388 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
389 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
390 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
391 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
392 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
393 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
395 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
397 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
399 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
401 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
403 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
405 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
407 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
409 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
412 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
413 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
414 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
415 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
416 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
417 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
419 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
424 MachineFrameInfo *FFI = MF.getFrameInfo();
425 int FPIndex = FI->getFramePointerSaveIndex();
426 assert(FPIndex && "No Frame Pointer Save Slot!");
427 FPOffset = FFI->getObjectOffset(FPIndex);
430 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
437 MachineFrameInfo *FFI = MF.getFrameInfo();
438 int BPIndex = FI->getBasePointerSaveIndex();
439 assert(BPIndex && "No Base Pointer Save Slot!");
440 BPOffset = FFI->getObjectOffset(BPIndex);
443 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
447 // Get stack alignments.
448 unsigned MaxAlign = MFI->getMaxAlignment();
449 if (HasBP && MaxAlign > 1)
450 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
451 "Invalid alignment!");
453 // Frames of 32KB & larger require special handling because they cannot be
454 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
455 bool isLargeFrame = !isInt<16>(NegFrameSize);
458 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
460 assert((isPPC64 || MustSaveCRs.empty()) &&
461 "Prologue CR saving supported only in 64-bit mode");
463 if (!MustSaveCRs.empty()) { // will only occur for PPC64
464 MachineInstrBuilder MIB =
465 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
466 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
467 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
471 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
472 BuildMI(MBB, MBBI, dl, StoreInst)
478 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
479 BuildMI(MBB, MBBI, dl, StoreInst)
485 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
486 BuildMI(MBB, MBBI, dl, StoreInst)
491 if (!MustSaveCRs.empty()) // will only occur for PPC64
492 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
493 .addReg(TempReg, getKillRegState(true))
497 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
498 if (!FrameSize) return;
500 // Adjust stack pointer: r1 += NegFrameSize.
501 // If there is a preferred stack alignment, align R1 now
504 // Save a copy of r1 as the base pointer.
505 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
510 if (HasBP && MaxAlign > 1) {
512 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
515 .addImm(64 - Log2_32(MaxAlign));
517 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
520 .addImm(32 - Log2_32(MaxAlign))
523 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
524 .addReg(ScratchReg, RegState::Kill)
525 .addImm(NegFrameSize);
527 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
528 .addImm(NegFrameSize >> 16);
529 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
530 .addReg(TempReg, RegState::Kill)
531 .addImm(NegFrameSize & 0xFFFF);
532 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
533 .addReg(ScratchReg, RegState::Kill)
534 .addReg(TempReg, RegState::Kill);
536 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
537 .addReg(SPReg, RegState::Kill)
541 } else if (!isLargeFrame) {
542 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
544 .addImm(NegFrameSize)
548 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
549 .addImm(NegFrameSize >> 16);
550 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
551 .addReg(ScratchReg, RegState::Kill)
552 .addImm(NegFrameSize & 0xFFFF);
553 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
554 .addReg(SPReg, RegState::Kill)
559 // Add the "machine moves" for the instructions we generated above, but in
561 if (needsFrameMoves) {
562 // Show update of SP.
563 assert(NegFrameSize);
564 unsigned CFIIndex = MMI.addFrameInst(
565 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
566 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
569 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
570 CFIIndex = MMI.addFrameInst(
571 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
572 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
573 .addCFIIndex(CFIIndex);
577 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
578 CFIIndex = MMI.addFrameInst(
579 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
580 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
581 .addCFIIndex(CFIIndex);
585 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
586 CFIIndex = MMI.addFrameInst(
587 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
588 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
589 .addCFIIndex(CFIIndex);
593 // If there is a frame pointer, copy R1 into R31
595 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
599 if (needsFrameMoves) {
600 // Mark effective beginning of when frame pointer is ready.
601 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
602 unsigned CFIIndex = MMI.addFrameInst(
603 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
605 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
606 .addCFIIndex(CFIIndex);
610 if (needsFrameMoves) {
611 // Add callee saved registers to move list.
612 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
613 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
614 unsigned Reg = CSI[I].getReg();
615 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
617 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
618 // subregisters of CR2. We just need to emit a move of CR2.
619 if (PPC::CRBITRCRegClass.contains(Reg))
622 // For SVR4, don't emit a move for the CR spill slot if we haven't
624 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
625 && MustSaveCRs.empty())
628 // For 64-bit SVR4 when we have spilled CRs, the spill location
629 // is SP+8, not a frame-relative slot.
630 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
631 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
632 nullptr, MRI->getDwarfRegNum(PPC::CR2, true), 8));
633 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
634 .addCFIIndex(CFIIndex);
638 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
639 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
640 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
641 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
642 .addCFIIndex(CFIIndex);
647 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
648 MachineBasicBlock &MBB) const {
649 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
650 assert(MBBI != MBB.end() && "Returning block has no terminator");
651 const PPCInstrInfo &TII =
652 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
653 const PPCRegisterInfo *RegInfo =
654 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
656 unsigned RetOpcode = MBBI->getOpcode();
659 assert((RetOpcode == PPC::BLR ||
660 RetOpcode == PPC::TCRETURNri ||
661 RetOpcode == PPC::TCRETURNdi ||
662 RetOpcode == PPC::TCRETURNai ||
663 RetOpcode == PPC::TCRETURNri8 ||
664 RetOpcode == PPC::TCRETURNdi8 ||
665 RetOpcode == PPC::TCRETURNai8) &&
666 "Can only insert epilog into returning blocks");
668 // Get alignment info so we know how to restore the SP.
669 const MachineFrameInfo *MFI = MF.getFrameInfo();
671 // Get the number of bytes allocated from the FrameInfo.
672 int FrameSize = MFI->getStackSize();
674 // Get processor type.
675 bool isPPC64 = Subtarget.isPPC64();
677 bool isDarwinABI = Subtarget.isDarwinABI();
678 bool isSVR4ABI = Subtarget.isSVR4ABI();
680 // Check if the link register (LR) has been saved.
681 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
682 bool MustSaveLR = FI->mustSaveLR();
683 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
684 // Do we have a frame pointer and/or base pointer for this function?
685 bool HasFP = hasFP(MF);
686 bool HasBP = RegInfo->hasBasePointer(MF);
688 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
689 unsigned BPReg = isPPC64 ? PPC::X30 : PPC::R30;
690 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
691 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
692 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
693 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
695 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
697 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
699 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
701 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
703 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
706 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
711 MachineFrameInfo *FFI = MF.getFrameInfo();
712 int FPIndex = FI->getFramePointerSaveIndex();
713 assert(FPIndex && "No Frame Pointer Save Slot!");
714 FPOffset = FFI->getObjectOffset(FPIndex);
717 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
724 MachineFrameInfo *FFI = MF.getFrameInfo();
725 int BPIndex = FI->getBasePointerSaveIndex();
726 assert(BPIndex && "No Base Pointer Save Slot!");
727 BPOffset = FFI->getObjectOffset(BPIndex);
730 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
734 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
735 RetOpcode == PPC::TCRETURNdi ||
736 RetOpcode == PPC::TCRETURNai ||
737 RetOpcode == PPC::TCRETURNri8 ||
738 RetOpcode == PPC::TCRETURNdi8 ||
739 RetOpcode == PPC::TCRETURNai8;
742 int MaxTCRetDelta = FI->getTailCallSPDelta();
743 MachineOperand &StackAdjust = MBBI->getOperand(1);
744 assert(StackAdjust.isImm() && "Expecting immediate value.");
745 // Adjust stack pointer.
746 int StackAdj = StackAdjust.getImm();
747 int Delta = StackAdj - MaxTCRetDelta;
748 assert((Delta >= 0) && "Delta must be positive");
750 FrameSize += (StackAdj +Delta);
752 FrameSize += StackAdj;
755 // Frames of 32KB & larger require special handling because they cannot be
756 // indexed into with a simple LD/LWZ immediate offset operand.
757 bool isLargeFrame = !isInt<16>(FrameSize);
760 // In the prologue, the loaded (or persistent) stack pointer value is offset
761 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
763 // If this function contained a fastcc call and GuaranteedTailCallOpt is
764 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
765 // call which invalidates the stack pointer value in SP(0). So we use the
766 // value of R31 in this case.
767 if (FI->hasFastCall()) {
768 assert(HasFP && "Expecting a valid frame pointer.");
770 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
771 .addReg(FPReg).addImm(FrameSize);
773 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
774 .addImm(FrameSize >> 16);
775 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
776 .addReg(ScratchReg, RegState::Kill)
777 .addImm(FrameSize & 0xFFFF);
778 BuildMI(MBB, MBBI, dl, AddInst)
783 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
784 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
788 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
796 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
800 assert((isPPC64 || MustSaveCRs.empty()) &&
801 "Epilogue CR restoring supported only in 64-bit mode");
803 if (!MustSaveCRs.empty()) // will only occur for PPC64
804 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
809 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
814 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
818 if (!MustSaveCRs.empty()) // will only occur for PPC64
819 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
820 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
821 .addReg(TempReg, getKillRegState(i == e-1));
824 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
826 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
828 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
829 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
830 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
831 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
833 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
834 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
835 .addReg(SPReg).addImm(CallerAllocatedAmt);
837 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
838 .addImm(CallerAllocatedAmt >> 16);
839 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
840 .addReg(ScratchReg, RegState::Kill)
841 .addImm(CallerAllocatedAmt & 0xFFFF);
842 BuildMI(MBB, MBBI, dl, AddInst)
847 } else if (RetOpcode == PPC::TCRETURNdi) {
848 MBBI = MBB.getLastNonDebugInstr();
849 MachineOperand &JumpTarget = MBBI->getOperand(0);
850 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
851 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
852 } else if (RetOpcode == PPC::TCRETURNri) {
853 MBBI = MBB.getLastNonDebugInstr();
854 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
855 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
856 } else if (RetOpcode == PPC::TCRETURNai) {
857 MBBI = MBB.getLastNonDebugInstr();
858 MachineOperand &JumpTarget = MBBI->getOperand(0);
859 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
860 } else if (RetOpcode == PPC::TCRETURNdi8) {
861 MBBI = MBB.getLastNonDebugInstr();
862 MachineOperand &JumpTarget = MBBI->getOperand(0);
863 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
864 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
865 } else if (RetOpcode == PPC::TCRETURNri8) {
866 MBBI = MBB.getLastNonDebugInstr();
867 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
868 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
869 } else if (RetOpcode == PPC::TCRETURNai8) {
870 MBBI = MBB.getLastNonDebugInstr();
871 MachineOperand &JumpTarget = MBBI->getOperand(0);
872 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
876 /// MustSaveLR - Return true if this function requires that we save the LR
877 /// register onto the stack in the prolog and restore it in the epilog of the
879 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
880 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
882 // We need a save/restore of LR if there is any def of LR (which is
883 // defined by calls, including the PIC setup sequence), or if there is
884 // some use of the LR stack slot (e.g. for builtin_return_address).
885 // (LR comes in 32 and 64 bit versions.)
886 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
887 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
891 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
892 RegScavenger *) const {
893 const PPCRegisterInfo *RegInfo =
894 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
896 // Save and clear the LR state.
897 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
898 unsigned LR = RegInfo->getRARegister();
899 FI->setMustSaveLR(MustSaveLR(MF, LR));
900 MachineRegisterInfo &MRI = MF.getRegInfo();
901 MRI.setPhysRegUnused(LR);
903 // Save R31 if necessary
904 int FPSI = FI->getFramePointerSaveIndex();
905 bool isPPC64 = Subtarget.isPPC64();
906 bool isDarwinABI = Subtarget.isDarwinABI();
907 MachineFrameInfo *MFI = MF.getFrameInfo();
909 // If the frame pointer save index hasn't been defined yet.
910 if (!FPSI && needsFP(MF)) {
911 // Find out what the fix offset of the frame pointer save area.
912 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
913 // Allocate the frame index for frame pointer save area.
914 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
916 FI->setFramePointerSaveIndex(FPSI);
919 int BPSI = FI->getBasePointerSaveIndex();
920 if (!BPSI && RegInfo->hasBasePointer(MF)) {
921 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI);
922 // Allocate the frame index for the base pointer save area.
923 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
925 FI->setBasePointerSaveIndex(BPSI);
928 // Reserve stack space to move the linkage area to in case of a tail call.
930 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
931 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
932 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
935 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
936 // function uses CR 2, 3, or 4.
937 if (!isPPC64 && !isDarwinABI &&
938 (MRI.isPhysRegUsed(PPC::CR2) ||
939 MRI.isPhysRegUsed(PPC::CR3) ||
940 MRI.isPhysRegUsed(PPC::CR4))) {
941 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
942 FI->setCRSpillFrameIndex(FrameIdx);
946 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
947 RegScavenger *RS) const {
948 // Early exit if not using the SVR4 ABI.
949 if (!Subtarget.isSVR4ABI()) {
950 addScavengingSpillSlot(MF, RS);
954 // Get callee saved register information.
955 MachineFrameInfo *FFI = MF.getFrameInfo();
956 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
958 // Early exit if no callee saved registers are modified!
959 if (CSI.empty() && !needsFP(MF)) {
960 addScavengingSpillSlot(MF, RS);
964 unsigned MinGPR = PPC::R31;
965 unsigned MinG8R = PPC::X31;
966 unsigned MinFPR = PPC::F31;
967 unsigned MinVR = PPC::V31;
969 bool HasGPSaveArea = false;
970 bool HasG8SaveArea = false;
971 bool HasFPSaveArea = false;
972 bool HasVRSAVESaveArea = false;
973 bool HasVRSaveArea = false;
975 SmallVector<CalleeSavedInfo, 18> GPRegs;
976 SmallVector<CalleeSavedInfo, 18> G8Regs;
977 SmallVector<CalleeSavedInfo, 18> FPRegs;
978 SmallVector<CalleeSavedInfo, 18> VRegs;
980 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
981 unsigned Reg = CSI[i].getReg();
982 if (PPC::GPRCRegClass.contains(Reg)) {
983 HasGPSaveArea = true;
985 GPRegs.push_back(CSI[i]);
990 } else if (PPC::G8RCRegClass.contains(Reg)) {
991 HasG8SaveArea = true;
993 G8Regs.push_back(CSI[i]);
998 } else if (PPC::F8RCRegClass.contains(Reg)) {
999 HasFPSaveArea = true;
1001 FPRegs.push_back(CSI[i]);
1006 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1007 PPC::CRRCRegClass.contains(Reg)) {
1008 ; // do nothing, as we already know whether CRs are spilled
1009 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1010 HasVRSAVESaveArea = true;
1011 } else if (PPC::VRRCRegClass.contains(Reg)) {
1012 HasVRSaveArea = true;
1014 VRegs.push_back(CSI[i]);
1020 llvm_unreachable("Unknown RegisterClass!");
1024 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1025 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
1027 int64_t LowerBound = 0;
1029 // Take into account stack space reserved for tail calls.
1031 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1032 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1033 LowerBound = TCSPDelta;
1036 // The Floating-point register save area is right below the back chain word
1037 // of the previous stack frame.
1038 if (HasFPSaveArea) {
1039 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1040 int FI = FPRegs[i].getFrameIdx();
1042 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1045 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1048 // Check whether the frame pointer register is allocated. If so, make sure it
1049 // is spilled to the correct offset.
1051 HasGPSaveArea = true;
1053 int FI = PFI->getFramePointerSaveIndex();
1054 assert(FI && "No Frame Pointer Save Slot!");
1056 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1059 const PPCRegisterInfo *RegInfo =
1060 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
1061 if (RegInfo->hasBasePointer(MF)) {
1062 HasGPSaveArea = true;
1064 int FI = PFI->getBasePointerSaveIndex();
1065 assert(FI && "No Base Pointer Save Slot!");
1067 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1070 // General register save area starts right below the Floating-point
1071 // register save area.
1072 if (HasGPSaveArea || HasG8SaveArea) {
1073 // Move general register save area spill slots down, taking into account
1074 // the size of the Floating-point register save area.
1075 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1076 int FI = GPRegs[i].getFrameIdx();
1078 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1081 // Move general register save area spill slots down, taking into account
1082 // the size of the Floating-point register save area.
1083 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1084 int FI = G8Regs[i].getFrameIdx();
1086 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1090 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1091 TRI->getEncodingValue(MinG8R));
1093 if (Subtarget.isPPC64()) {
1094 LowerBound -= (31 - MinReg + 1) * 8;
1096 LowerBound -= (31 - MinReg + 1) * 4;
1100 // For 32-bit only, the CR save area is below the general register
1101 // save area. For 64-bit SVR4, the CR save area is addressed relative
1102 // to the stack pointer and hence does not need an adjustment here.
1103 // Only CR2 (the first nonvolatile spilled) has an associated frame
1104 // index so that we have a single uniform save area.
1105 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1106 // Adjust the frame index of the CR spill slot.
1107 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1108 unsigned Reg = CSI[i].getReg();
1110 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1111 // Leave Darwin logic as-is.
1112 || (!Subtarget.isSVR4ABI() &&
1113 (PPC::CRBITRCRegClass.contains(Reg) ||
1114 PPC::CRRCRegClass.contains(Reg)))) {
1115 int FI = CSI[i].getFrameIdx();
1117 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1121 LowerBound -= 4; // The CR save area is always 4 bytes long.
1124 if (HasVRSAVESaveArea) {
1125 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1126 // which have the VRSAVE register class?
1127 // Adjust the frame index of the VRSAVE spill slot.
1128 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1129 unsigned Reg = CSI[i].getReg();
1131 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1132 int FI = CSI[i].getFrameIdx();
1134 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1138 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1141 if (HasVRSaveArea) {
1142 // Insert alignment padding, we need 16-byte alignment.
1143 LowerBound = (LowerBound - 15) & ~(15);
1145 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1146 int FI = VRegs[i].getFrameIdx();
1148 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1152 addScavengingSpillSlot(MF, RS);
1156 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1157 RegScavenger *RS) const {
1158 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1159 // a large stack, which will require scavenging a register to materialize a
1162 // We need to have a scavenger spill slot for spills if the frame size is
1163 // large. In case there is no free register for large-offset addressing,
1164 // this slot is used for the necessary emergency spill. Also, we need the
1165 // slot for dynamic stack allocations.
1167 // The scavenger might be invoked if the frame offset does not fit into
1168 // the 16-bit immediate. We don't know the complete frame size here
1169 // because we've not yet computed callee-saved register spills or the
1170 // needed alignment padding.
1171 unsigned StackSize = determineFrameLayout(MF, false, true);
1172 MachineFrameInfo *MFI = MF.getFrameInfo();
1173 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1174 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1175 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1176 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1177 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1178 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1182 // Might we have over-aligned allocas?
1183 bool HasAlVars = MFI->hasVarSizedObjects() &&
1184 MFI->getMaxAlignment() > getStackAlignment();
1186 // These kinds of spills might need two registers.
1187 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1188 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1196 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1197 MachineBasicBlock::iterator MI,
1198 const std::vector<CalleeSavedInfo> &CSI,
1199 const TargetRegisterInfo *TRI) const {
1201 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1202 // Return false otherwise to maintain pre-existing behavior.
1203 if (!Subtarget.isSVR4ABI())
1206 MachineFunction *MF = MBB.getParent();
1207 const PPCInstrInfo &TII =
1208 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1210 bool CRSpilled = false;
1211 MachineInstrBuilder CRMIB;
1213 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1214 unsigned Reg = CSI[i].getReg();
1215 // Only Darwin actually uses the VRSAVE register, but it can still appear
1216 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1217 // Darwin, ignore it.
1218 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1221 // CR2 through CR4 are the nonvolatile CR fields.
1222 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1224 // Add the callee-saved register as live-in; it's killed at the spill.
1227 if (CRSpilled && IsCRField) {
1228 CRMIB.addReg(Reg, RegState::ImplicitKill);
1232 // Insert the spill to the stack frame.
1234 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1235 if (Subtarget.isPPC64()) {
1236 // The actual spill will happen at the start of the prologue.
1237 FuncInfo->addMustSaveCR(Reg);
1240 FuncInfo->setSpillsCR();
1242 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1243 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1244 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1245 .addReg(Reg, RegState::ImplicitKill);
1247 MBB.insert(MI, CRMIB);
1248 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1250 getKillRegState(true)),
1251 CSI[i].getFrameIdx()));
1254 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1255 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1256 CSI[i].getFrameIdx(), RC, TRI);
1263 restoreCRs(bool isPPC64, bool is31,
1264 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1265 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1266 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1268 MachineFunction *MF = MBB.getParent();
1269 const PPCInstrInfo &TII =
1270 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1272 unsigned RestoreOp, MoveReg;
1275 // This is handled during epilogue generation.
1278 // 32-bit: FP-relative
1279 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1281 CSI[CSIIndex].getFrameIdx()));
1282 RestoreOp = PPC::MTOCRF;
1287 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1288 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1291 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1292 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1295 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1296 .addReg(MoveReg, getKillRegState(true)));
1299 void PPCFrameLowering::
1300 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1301 MachineBasicBlock::iterator I) const {
1302 const PPCInstrInfo &TII =
1303 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1304 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1305 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1306 // Add (actually subtract) back the amount the callee popped on return.
1307 if (int CalleeAmt = I->getOperand(1).getImm()) {
1308 bool is64Bit = Subtarget.isPPC64();
1310 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1311 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1312 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1313 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1314 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1315 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1316 MachineInstr *MI = I;
1317 DebugLoc dl = MI->getDebugLoc();
1319 if (isInt<16>(CalleeAmt)) {
1320 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1321 .addReg(StackReg, RegState::Kill)
1324 MachineBasicBlock::iterator MBBI = I;
1325 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1326 .addImm(CalleeAmt >> 16);
1327 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1328 .addReg(TmpReg, RegState::Kill)
1329 .addImm(CalleeAmt & 0xFFFF);
1330 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1331 .addReg(StackReg, RegState::Kill)
1336 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1341 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1342 MachineBasicBlock::iterator MI,
1343 const std::vector<CalleeSavedInfo> &CSI,
1344 const TargetRegisterInfo *TRI) const {
1346 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1347 // Return false otherwise to maintain pre-existing behavior.
1348 if (!Subtarget.isSVR4ABI())
1351 MachineFunction *MF = MBB.getParent();
1352 const PPCInstrInfo &TII =
1353 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1354 bool CR2Spilled = false;
1355 bool CR3Spilled = false;
1356 bool CR4Spilled = false;
1357 unsigned CSIIndex = 0;
1359 // Initialize insertion-point logic; we will be restoring in reverse
1361 MachineBasicBlock::iterator I = MI, BeforeI = I;
1362 bool AtStart = I == MBB.begin();
1367 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1368 unsigned Reg = CSI[i].getReg();
1370 // Only Darwin actually uses the VRSAVE register, but it can still appear
1371 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1372 // Darwin, ignore it.
1373 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1376 if (Reg == PPC::CR2) {
1378 // The spill slot is associated only with CR2, which is the
1379 // first nonvolatile spilled. Save it here.
1382 } else if (Reg == PPC::CR3) {
1385 } else if (Reg == PPC::CR4) {
1389 // When we first encounter a non-CR register after seeing at
1390 // least one CR register, restore all spilled CRs together.
1391 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1392 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1393 bool is31 = needsFP(*MF);
1394 restoreCRs(Subtarget.isPPC64(), is31,
1395 CR2Spilled, CR3Spilled, CR4Spilled,
1396 MBB, I, CSI, CSIIndex);
1397 CR2Spilled = CR3Spilled = CR4Spilled = false;
1400 // Default behavior for non-CR saves.
1401 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1402 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1404 assert(I != MBB.begin() &&
1405 "loadRegFromStackSlot didn't insert any code!");
1408 // Insert in reverse order.
1417 // If we haven't yet spilled the CRs, do so now.
1418 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1419 bool is31 = needsFP(*MF);
1420 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1421 MBB, I, CSI, CSIIndex);