1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Target/TargetOptions.h"
31 /// VRRegNo - Map from a numbered VR register to its enum value.
33 static const MCPhysReg VRRegNo[] = {
34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
41 if (STI.isDarwinABI())
42 return STI.isPPC64() ? 16 : 8;
44 return STI.isPPC64() ? 16 : 4;
47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
48 return STI.isELFv2ABI() ? 24 : 40;
51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
52 // For the Darwin ABI:
53 // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
54 // for saving the frame pointer (if needed.) While the published ABI has
55 // not used this slot since at least MacOSX 10.2, there is older code
56 // around that does use it, and that needs to continue to work.
57 if (STI.isDarwinABI())
58 return STI.isPPC64() ? -8U : -4U;
60 // SVR4 ABI: First slot in the general register save area.
61 return STI.isPPC64() ? -8U : -4U;
64 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
65 if (STI.isDarwinABI() || STI.isPPC64())
66 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
73 if (STI.isDarwinABI())
74 return STI.isPPC64() ? -16U : -8U;
76 // SVR4 ABI: First slot in the general register save area.
79 : (STI.getTargetMachine().getRelocationModel() == Reloc::PIC_)
84 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
85 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
86 STI.getPlatformStackAlignment(), 0),
87 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
88 TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
89 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
90 LinkageSize(computeLinkageSize(Subtarget)),
91 BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {}
93 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
94 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
95 unsigned &NumEntries) const {
96 if (Subtarget.isDarwinABI()) {
98 if (Subtarget.isPPC64()) {
99 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
100 return &darwin64Offsets;
102 static const SpillSlot darwinOffsets = {PPC::R31, -4};
103 return &darwinOffsets;
107 // Early exit if not using the SVR4 ABI.
108 if (!Subtarget.isSVR4ABI()) {
113 // Note that the offsets here overlap, but this is fixed up in
114 // processFunctionBeforeFrameFinalized.
116 static const SpillSlot Offsets[] = {
117 // Floating-point register save area offsets.
137 // General register save area offsets.
157 // CR save area offset. We map each of the nonvolatile CR fields
158 // to the slot for CR2, which is the first of the nonvolatile CR
159 // fields to be assigned, so that we only allocate one save slot.
160 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
163 // VRSAVE save area offset.
166 // Vector register save area
180 static const SpillSlot Offsets64[] = {
181 // Floating-point register save area offsets.
201 // General register save area offsets.
221 // VRSAVE save area offset.
224 // Vector register save area
238 if (Subtarget.isPPC64()) {
239 NumEntries = array_lengthof(Offsets64);
243 NumEntries = array_lengthof(Offsets);
249 /// RemoveVRSaveCode - We have found that this function does not need any code
250 /// to manipulate the VRSAVE register, even though it uses vector registers.
251 /// This can happen when the only registers used are known to be live in or out
252 /// of the function. Remove all of the VRSAVE related code from the function.
253 /// FIXME: The removal of the code results in a compile failure at -O0 when the
254 /// function contains a function call, as the GPR containing original VRSAVE
255 /// contents is spilled and reloaded around the call. Without the prolog code,
256 /// the spill instruction refers to an undefined register. This code needs
257 /// to account for all uses of that GPR.
258 static void RemoveVRSaveCode(MachineInstr *MI) {
259 MachineBasicBlock *Entry = MI->getParent();
260 MachineFunction *MF = Entry->getParent();
262 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
263 MachineBasicBlock::iterator MBBI = MI;
265 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
266 MBBI->eraseFromParent();
268 bool RemovedAllMTVRSAVEs = true;
269 // See if we can find and remove the MTVRSAVE instruction from all of the
271 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
272 // If last instruction is a return instruction, add an epilogue
273 if (I->isReturnBlock()) {
274 bool FoundIt = false;
275 for (MBBI = I->end(); MBBI != I->begin(); ) {
277 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
278 MBBI->eraseFromParent(); // remove it.
283 RemovedAllMTVRSAVEs &= FoundIt;
287 // If we found and removed all MTVRSAVE instructions, remove the read of
289 if (RemovedAllMTVRSAVEs) {
291 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
293 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
294 MBBI->eraseFromParent();
297 // Finally, nuke the UPDATE_VRSAVE.
298 MI->eraseFromParent();
301 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
302 // instruction selector. Based on the vector registers that have been used,
303 // transform this into the appropriate ORI instruction.
304 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
305 MachineFunction *MF = MI->getParent()->getParent();
306 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
307 DebugLoc dl = MI->getDebugLoc();
309 const MachineRegisterInfo &MRI = MF->getRegInfo();
310 unsigned UsedRegMask = 0;
311 for (unsigned i = 0; i != 32; ++i)
312 if (MRI.isPhysRegModified(VRRegNo[i]))
313 UsedRegMask |= 1 << (31-i);
315 // Live in and live out values already must be in the mask, so don't bother
317 for (MachineRegisterInfo::livein_iterator
318 I = MF->getRegInfo().livein_begin(),
319 E = MF->getRegInfo().livein_end(); I != E; ++I) {
320 unsigned RegNo = TRI->getEncodingValue(I->first);
321 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
322 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
325 // Live out registers appear as use operands on return instructions.
326 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
327 UsedRegMask != 0 && BI != BE; ++BI) {
328 const MachineBasicBlock &MBB = *BI;
329 if (!MBB.isReturnBlock())
331 const MachineInstr &Ret = MBB.back();
332 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
333 const MachineOperand &MO = Ret.getOperand(I);
334 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
336 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
337 UsedRegMask &= ~(1 << (31-RegNo));
341 // If no registers are used, turn this into a copy.
342 if (UsedRegMask == 0) {
343 // Remove all VRSAVE code.
344 RemoveVRSaveCode(MI);
348 unsigned SrcReg = MI->getOperand(1).getReg();
349 unsigned DstReg = MI->getOperand(0).getReg();
351 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
352 if (DstReg != SrcReg)
353 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
355 .addImm(UsedRegMask);
357 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
358 .addReg(SrcReg, RegState::Kill)
359 .addImm(UsedRegMask);
360 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
361 if (DstReg != SrcReg)
362 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
364 .addImm(UsedRegMask >> 16);
366 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
367 .addReg(SrcReg, RegState::Kill)
368 .addImm(UsedRegMask >> 16);
370 if (DstReg != SrcReg)
371 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
373 .addImm(UsedRegMask >> 16);
375 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
376 .addReg(SrcReg, RegState::Kill)
377 .addImm(UsedRegMask >> 16);
379 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
380 .addReg(DstReg, RegState::Kill)
381 .addImm(UsedRegMask & 0xFFFF);
384 // Remove the old UPDATE_VRSAVE instruction.
385 MI->eraseFromParent();
388 static bool spillsCR(const MachineFunction &MF) {
389 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
390 return FuncInfo->isCRSpilled();
393 static bool spillsVRSAVE(const MachineFunction &MF) {
394 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
395 return FuncInfo->isVRSAVESpilled();
398 static bool hasSpills(const MachineFunction &MF) {
399 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
400 return FuncInfo->hasSpills();
403 static bool hasNonRISpills(const MachineFunction &MF) {
404 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
405 return FuncInfo->hasNonRISpills();
408 /// MustSaveLR - Return true if this function requires that we save the LR
409 /// register onto the stack in the prolog and restore it in the epilog of the
411 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
412 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
414 // We need a save/restore of LR if there is any def of LR (which is
415 // defined by calls, including the PIC setup sequence), or if there is
416 // some use of the LR stack slot (e.g. for builtin_return_address).
417 // (LR comes in 32 and 64 bit versions.)
418 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
419 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
422 /// determineFrameLayout - Determine the size of the frame and maximum call
424 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
426 bool UseEstimate) const {
427 MachineFrameInfo *MFI = MF.getFrameInfo();
429 // Get the number of bytes to allocate from the FrameInfo
431 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
433 // Get stack alignments. The frame must be aligned to the greatest of these:
434 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
435 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
436 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
438 const PPCRegisterInfo *RegInfo =
439 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
441 // If we are a leaf function, and use up to 224 bytes of stack space,
442 // don't have a frame pointer, calls, or dynamic alloca then we do not need
443 // to adjust the stack pointer (we fit in the Red Zone).
444 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
445 // stackless code if all local vars are reg-allocated.
446 bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone);
447 unsigned LR = RegInfo->getRARegister();
448 if (!DisableRedZone &&
449 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
450 !Subtarget.isSVR4ABI() || // allocated locals.
452 FrameSize <= 224 && // Fits in red zone.
453 !MFI->hasVarSizedObjects() && // No dynamic alloca.
454 !MFI->adjustsStack() && // No calls.
455 !MustSaveLR(MF, LR) &&
456 !RegInfo->hasBasePointer(MF)) { // No special alignment.
459 MFI->setStackSize(0);
463 // Get the maximum call frame size of all the calls.
464 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
466 // Maximum call frame needs to be at least big enough for linkage area.
467 unsigned minCallFrameSize = getLinkageSize();
468 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
470 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
471 // that allocations will be aligned.
472 if (MFI->hasVarSizedObjects())
473 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
475 // Update maximum call frame size.
477 MFI->setMaxCallFrameSize(maxCallFrameSize);
479 // Include call frame size in total.
480 FrameSize += maxCallFrameSize;
482 // Make sure the frame is aligned.
483 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
485 // Update frame info.
487 MFI->setStackSize(FrameSize);
492 // hasFP - Return true if the specified function actually has a dedicated frame
494 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
495 const MachineFrameInfo *MFI = MF.getFrameInfo();
496 // FIXME: This is pretty much broken by design: hasFP() might be called really
497 // early, before the stack layout was calculated and thus hasFP() might return
498 // true or false here depending on the time of call.
499 return (MFI->getStackSize()) && needsFP(MF);
502 // needsFP - Return true if the specified function should have a dedicated frame
503 // pointer register. This is true if the function has variable sized allocas or
504 // if frame pointer elimination is disabled.
505 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
506 const MachineFrameInfo *MFI = MF.getFrameInfo();
508 // Naked functions have no stack frame pushed, so we don't have a frame
510 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
513 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
514 MFI->hasVarSizedObjects() ||
515 MFI->hasStackMap() || MFI->hasPatchPoint() ||
516 (MF.getTarget().Options.GuaranteedTailCallOpt &&
517 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
520 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
521 bool is31 = needsFP(MF);
522 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
523 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
525 const PPCRegisterInfo *RegInfo =
526 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
527 bool HasBP = RegInfo->hasBasePointer(MF);
528 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
529 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
531 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
533 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
535 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
536 MachineOperand &MO = MBBI->getOperand(I);
540 switch (MO.getReg()) {
559 /* This function will do the following:
560 - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12
561 respectively (defaults recommended by the ABI) and return true
562 - If MBB is not an entry block, initialize the register scavenger and look
563 for available registers.
564 - If the defaults (R0/R12) are available, return true
565 - If TwoUniqueRegsRequired is set to true, it looks for two unique
566 registers. Otherwise, look for a single available register.
567 - If the required registers are found, set SR1 and SR2 and return true.
568 - If the required registers are not found, set SR2 or both SR1 and SR2 to
569 PPC::NoRegister and return false.
571 Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired
572 is not set, this function will attempt to find two different registers, but
573 still return true if only one register is available (and set SR1 == SR2).
576 PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
578 bool TwoUniqueRegsRequired,
580 unsigned *SR2) const {
582 unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
583 unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;
585 // Set the defaults for the two scratch registers.
590 assert (SR1 && "Asking for the second scratch register but not the first?");
594 // If MBB is an entry or exit block, use R0 and R12 as the scratch registers.
595 if ((UseAtEnd && MBB->isReturnBlock()) ||
596 (!UseAtEnd && (&MBB->getParent()->front() == MBB)))
599 RS.enterBasicBlock(MBB);
601 if (UseAtEnd && !MBB->empty()) {
602 // The scratch register will be used at the end of the block, so must
603 // consider all registers used within the block
605 MachineBasicBlock::iterator MBBI = MBB->getFirstTerminator();
606 // If no terminator, back iterator up to previous instruction.
607 if (MBBI == MBB->end())
608 MBBI = std::prev(MBBI);
610 if (MBBI != MBB->begin())
614 // If the two registers are available, we're all good.
615 // Note that we only return here if both R0 and R12 are available because
616 // although the function may not require two unique registers, it may benefit
617 // from having two so we should try to provide them.
618 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12))
621 // Get the list of callee-saved registers for the target.
622 const PPCRegisterInfo *RegInfo =
623 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
624 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent());
626 // Get all the available registers in the block.
627 BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :
630 // We shouldn't use callee-saved registers as scratch registers as they may be
631 // available when looking for a candidate block for shrink wrapping but not
632 // available when the actual prologue/epilogue is being emitted because they
633 // were added as live-in to the prologue block by PrologueEpilogueInserter.
634 for (int i = 0; CSRegs[i]; ++i)
637 // Set the first scratch register to the first available one.
639 int FirstScratchReg = BV.find_first();
640 *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg;
643 // If there is another one available, set the second scratch register to that.
644 // Otherwise, set it to either PPC::NoRegister if this function requires two
645 // or to whatever SR1 is set to if this function doesn't require two.
647 int SecondScratchReg = BV.find_next(*SR1);
648 if (SecondScratchReg != -1)
649 *SR2 = SecondScratchReg;
651 *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1;
654 // Now that we've done our best to provide both registers, double check
655 // whether we were unable to provide enough.
656 if (BV.count() < (TwoUniqueRegsRequired ? 2 : 1))
662 // We need a scratch register for spilling LR and for spilling CR. By default,
663 // we use two scratch registers to hide latency. However, if only one scratch
664 // register is available, we can adjust for that by not overlapping the spill
665 // code. However, if we need to realign the stack (i.e. have a base pointer)
666 // and the stack frame is large, we need two scratch registers.
668 PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
669 const PPCRegisterInfo *RegInfo =
670 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
671 MachineFunction &MF = *(MBB->getParent());
672 bool HasBP = RegInfo->hasBasePointer(MF);
673 unsigned FrameSize = determineFrameLayout(MF, false);
674 int NegFrameSize = -FrameSize;
675 bool IsLargeFrame = !isInt<16>(NegFrameSize);
676 MachineFrameInfo *MFI = MF.getFrameInfo();
677 unsigned MaxAlign = MFI->getMaxAlignment();
679 return IsLargeFrame && HasBP && MaxAlign > 1;
682 bool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const {
683 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
685 return findScratchRegister(TmpMBB, false,
686 twoUniqueScratchRegsRequired(TmpMBB));
689 bool PPCFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
690 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
692 return findScratchRegister(TmpMBB, true);
695 void PPCFrameLowering::emitPrologue(MachineFunction &MF,
696 MachineBasicBlock &MBB) const {
697 MachineBasicBlock::iterator MBBI = MBB.begin();
698 MachineFrameInfo *MFI = MF.getFrameInfo();
699 const PPCInstrInfo &TII =
700 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
701 const PPCRegisterInfo *RegInfo =
702 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
704 MachineModuleInfo &MMI = MF.getMMI();
705 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
707 bool needsCFI = MMI.hasDebugInfo() ||
708 MF.getFunction()->needsUnwindTableEntry();
710 // Get processor type.
711 bool isPPC64 = Subtarget.isPPC64();
713 bool isSVR4ABI = Subtarget.isSVR4ABI();
714 bool isELFv2ABI = Subtarget.isELFv2ABI();
715 assert((Subtarget.isDarwinABI() || isSVR4ABI) &&
716 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
718 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
721 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
722 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
723 HandleVRSaveUpdate(MBBI, TII);
728 // Move MBBI back to the beginning of the prologue block.
731 // Work out frame sizes.
732 unsigned FrameSize = determineFrameLayout(MF);
733 int NegFrameSize = -FrameSize;
734 if (!isInt<32>(NegFrameSize))
735 llvm_unreachable("Unhandled stack size!");
737 if (MFI->isFrameAddressTaken())
738 replaceFPWithRealFP(MF);
740 // Check if the link register (LR) must be saved.
741 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
742 bool MustSaveLR = FI->mustSaveLR();
743 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
744 bool MustSaveCR = !MustSaveCRs.empty();
745 // Do we have a frame pointer and/or base pointer for this function?
746 bool HasFP = hasFP(MF);
747 bool HasBP = RegInfo->hasBasePointer(MF);
749 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
750 unsigned BPReg = RegInfo->getBaseRegister(MF);
751 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
752 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
753 unsigned ScratchReg = 0;
754 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
755 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
756 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
758 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
760 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
762 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
764 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
766 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
768 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
770 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
772 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
775 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
776 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
777 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
778 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
779 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
780 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
782 // Using the same bool variable as below to supress compiler warnings.
783 bool SingleScratchReg =
784 findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB),
785 &ScratchReg, &TempReg);
786 assert(SingleScratchReg &&
787 "Required number of registers not available in this block");
789 SingleScratchReg = ScratchReg == TempReg;
791 int LROffset = getReturnSaveOffset();
796 MachineFrameInfo *FFI = MF.getFrameInfo();
797 int FPIndex = FI->getFramePointerSaveIndex();
798 assert(FPIndex && "No Frame Pointer Save Slot!");
799 FPOffset = FFI->getObjectOffset(FPIndex);
801 FPOffset = getFramePointerSaveOffset();
808 MachineFrameInfo *FFI = MF.getFrameInfo();
809 int BPIndex = FI->getBasePointerSaveIndex();
810 assert(BPIndex && "No Base Pointer Save Slot!");
811 BPOffset = FFI->getObjectOffset(BPIndex);
813 BPOffset = getBasePointerSaveOffset();
818 if (FI->usesPICBase()) {
819 MachineFrameInfo *FFI = MF.getFrameInfo();
820 int PBPIndex = FI->getPICBasePointerSaveIndex();
821 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
822 PBPOffset = FFI->getObjectOffset(PBPIndex);
825 // Get stack alignments.
826 unsigned MaxAlign = MFI->getMaxAlignment();
827 if (HasBP && MaxAlign > 1)
828 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
829 "Invalid alignment!");
831 // Frames of 32KB & larger require special handling because they cannot be
832 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
833 bool isLargeFrame = !isInt<16>(NegFrameSize);
835 assert((isPPC64 || !MustSaveCR) &&
836 "Prologue CR saving supported only in 64-bit mode");
838 // If we need to spill the CR and the LR but we don't have two separate
839 // registers available, we must spill them one at a time
840 if (MustSaveCR && SingleScratchReg && MustSaveLR) {
841 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
842 // If only one or two CR fields are clobbered, it could be more
843 // efficient to use mfocrf to selectively save just those fields.
844 MachineInstrBuilder MIB =
845 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
846 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
847 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
848 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
849 .addReg(TempReg, getKillRegState(true))
855 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
858 !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
859 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
860 // If only one or two CR fields are clobbered, it could be more
861 // efficient to use mfocrf to selectively save just those fields.
862 MachineInstrBuilder MIB =
863 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
864 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
865 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
869 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
870 BuildMI(MBB, MBBI, dl, StoreInst)
875 if (FI->usesPICBase())
876 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
877 BuildMI(MBB, MBBI, dl, StoreInst)
883 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
884 BuildMI(MBB, MBBI, dl, StoreInst)
890 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
891 BuildMI(MBB, MBBI, dl, StoreInst)
897 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
898 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
899 .addReg(TempReg, getKillRegState(true))
903 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
904 if (!FrameSize) return;
906 // Adjust stack pointer: r1 += NegFrameSize.
907 // If there is a preferred stack alignment, align R1 now
910 // Save a copy of r1 as the base pointer.
911 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
916 // This condition must be kept in sync with canUseAsPrologue.
917 if (HasBP && MaxAlign > 1) {
919 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
922 .addImm(64 - Log2_32(MaxAlign));
924 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
927 .addImm(32 - Log2_32(MaxAlign))
930 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
931 .addReg(ScratchReg, RegState::Kill)
932 .addImm(NegFrameSize);
934 assert(!SingleScratchReg && "Only a single scratch reg available");
935 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
936 .addImm(NegFrameSize >> 16);
937 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
938 .addReg(TempReg, RegState::Kill)
939 .addImm(NegFrameSize & 0xFFFF);
940 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
941 .addReg(ScratchReg, RegState::Kill)
942 .addReg(TempReg, RegState::Kill);
944 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
945 .addReg(SPReg, RegState::Kill)
949 } else if (!isLargeFrame) {
950 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
952 .addImm(NegFrameSize)
956 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
957 .addImm(NegFrameSize >> 16);
958 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
959 .addReg(ScratchReg, RegState::Kill)
960 .addImm(NegFrameSize & 0xFFFF);
961 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
962 .addReg(SPReg, RegState::Kill)
967 // Add Call Frame Information for the instructions we generated above.
972 // Define CFA in terms of BP. Do this in preference to using FP/SP,
973 // because if the stack needed aligning then CFA won't be at a fixed
974 // offset from FP/SP.
975 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
976 CFIIndex = MMI.addFrameInst(
977 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
979 // Adjust the definition of CFA to account for the change in SP.
980 assert(NegFrameSize);
981 CFIIndex = MMI.addFrameInst(
982 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
984 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
985 .addCFIIndex(CFIIndex);
988 // Describe where FP was saved, at a fixed offset from CFA.
989 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
990 CFIIndex = MMI.addFrameInst(
991 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
992 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
993 .addCFIIndex(CFIIndex);
996 if (FI->usesPICBase()) {
997 // Describe where FP was saved, at a fixed offset from CFA.
998 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
999 CFIIndex = MMI.addFrameInst(
1000 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
1001 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1002 .addCFIIndex(CFIIndex);
1006 // Describe where BP was saved, at a fixed offset from CFA.
1007 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1008 CFIIndex = MMI.addFrameInst(
1009 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
1010 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1011 .addCFIIndex(CFIIndex);
1015 // Describe where LR was saved, at a fixed offset from CFA.
1016 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
1017 CFIIndex = MMI.addFrameInst(
1018 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
1019 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1020 .addCFIIndex(CFIIndex);
1024 // If there is a frame pointer, copy R1 into R31
1026 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1030 if (!HasBP && needsCFI) {
1031 // Change the definition of CFA from SP+offset to FP+offset, because SP
1032 // will change at every alloca.
1033 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1034 unsigned CFIIndex = MMI.addFrameInst(
1035 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
1037 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1038 .addCFIIndex(CFIIndex);
1043 // Describe where callee saved registers were saved, at fixed offsets from
1045 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1046 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1047 unsigned Reg = CSI[I].getReg();
1048 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1050 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
1051 // subregisters of CR2. We just need to emit a move of CR2.
1052 if (PPC::CRBITRCRegClass.contains(Reg))
1055 // For SVR4, don't emit a move for the CR spill slot if we haven't
1057 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1061 // For 64-bit SVR4 when we have spilled CRs, the spill location
1062 // is SP+8, not a frame-relative slot.
1063 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1064 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
1065 // the whole CR word. In the ELFv2 ABI, every CR that was
1066 // actually saved gets its own CFI record.
1067 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
1068 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1069 nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
1070 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1071 .addCFIIndex(CFIIndex);
1075 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1076 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1077 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
1078 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1079 .addCFIIndex(CFIIndex);
1084 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
1085 MachineBasicBlock &MBB) const {
1086 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
1089 if (MBBI != MBB.end())
1090 dl = MBBI->getDebugLoc();
1092 const PPCInstrInfo &TII =
1093 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1094 const PPCRegisterInfo *RegInfo =
1095 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1097 // Get alignment info so we know how to restore the SP.
1098 const MachineFrameInfo *MFI = MF.getFrameInfo();
1100 // Get the number of bytes allocated from the FrameInfo.
1101 int FrameSize = MFI->getStackSize();
1103 // Get processor type.
1104 bool isPPC64 = Subtarget.isPPC64();
1106 bool isSVR4ABI = Subtarget.isSVR4ABI();
1108 // Check if the link register (LR) has been saved.
1109 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1110 bool MustSaveLR = FI->mustSaveLR();
1111 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
1112 bool MustSaveCR = !MustSaveCRs.empty();
1113 // Do we have a frame pointer and/or base pointer for this function?
1114 bool HasFP = hasFP(MF);
1115 bool HasBP = RegInfo->hasBasePointer(MF);
1117 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1118 unsigned BPReg = RegInfo->getBaseRegister(MF);
1119 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1120 unsigned ScratchReg = 0;
1121 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1122 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1124 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1126 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1128 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1130 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1132 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1135 int LROffset = getReturnSaveOffset();
1139 // Using the same bool variable as below to supress compiler warnings.
1140 bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg,
1142 assert(SingleScratchReg &&
1143 "Could not find an available scratch register");
1145 SingleScratchReg = ScratchReg == TempReg;
1149 MachineFrameInfo *FFI = MF.getFrameInfo();
1150 int FPIndex = FI->getFramePointerSaveIndex();
1151 assert(FPIndex && "No Frame Pointer Save Slot!");
1152 FPOffset = FFI->getObjectOffset(FPIndex);
1154 FPOffset = getFramePointerSaveOffset();
1161 MachineFrameInfo *FFI = MF.getFrameInfo();
1162 int BPIndex = FI->getBasePointerSaveIndex();
1163 assert(BPIndex && "No Base Pointer Save Slot!");
1164 BPOffset = FFI->getObjectOffset(BPIndex);
1166 BPOffset = getBasePointerSaveOffset();
1171 if (FI->usesPICBase()) {
1172 MachineFrameInfo *FFI = MF.getFrameInfo();
1173 int PBPIndex = FI->getPICBasePointerSaveIndex();
1174 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
1175 PBPOffset = FFI->getObjectOffset(PBPIndex);
1178 bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn());
1180 if (IsReturnBlock) {
1181 unsigned RetOpcode = MBBI->getOpcode();
1182 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1183 RetOpcode == PPC::TCRETURNdi ||
1184 RetOpcode == PPC::TCRETURNai ||
1185 RetOpcode == PPC::TCRETURNri8 ||
1186 RetOpcode == PPC::TCRETURNdi8 ||
1187 RetOpcode == PPC::TCRETURNai8;
1190 int MaxTCRetDelta = FI->getTailCallSPDelta();
1191 MachineOperand &StackAdjust = MBBI->getOperand(1);
1192 assert(StackAdjust.isImm() && "Expecting immediate value.");
1193 // Adjust stack pointer.
1194 int StackAdj = StackAdjust.getImm();
1195 int Delta = StackAdj - MaxTCRetDelta;
1196 assert((Delta >= 0) && "Delta must be positive");
1197 if (MaxTCRetDelta>0)
1198 FrameSize += (StackAdj +Delta);
1200 FrameSize += StackAdj;
1204 // Frames of 32KB & larger require special handling because they cannot be
1205 // indexed into with a simple LD/LWZ immediate offset operand.
1206 bool isLargeFrame = !isInt<16>(FrameSize);
1209 // In the prologue, the loaded (or persistent) stack pointer value is offset
1210 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
1212 // If this function contained a fastcc call and GuaranteedTailCallOpt is
1213 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1214 // call which invalidates the stack pointer value in SP(0). So we use the
1215 // value of R31 in this case.
1216 if (FI->hasFastCall()) {
1217 assert(HasFP && "Expecting a valid frame pointer.");
1218 if (!isLargeFrame) {
1219 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1220 .addReg(FPReg).addImm(FrameSize);
1222 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1223 .addImm(FrameSize >> 16);
1224 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1225 .addReg(ScratchReg, RegState::Kill)
1226 .addImm(FrameSize & 0xFFFF);
1227 BuildMI(MBB, MBBI, dl, AddInst)
1230 .addReg(ScratchReg);
1232 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
1233 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1237 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
1243 assert((isPPC64 || !MustSaveCR) &&
1244 "Epilogue CR restoring supported only in 64-bit mode");
1246 // If we need to save both the LR and the CR and we only have one available
1247 // scratch register, we must do them one at a time.
1248 if (MustSaveCR && SingleScratchReg && MustSaveLR) {
1249 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1252 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1253 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1254 .addReg(TempReg, getKillRegState(i == e-1));
1258 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1263 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
1264 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1269 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1273 if (FI->usesPICBase())
1274 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
1275 BuildMI(MBB, MBBI, dl, LoadInst)
1281 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1286 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
1287 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1288 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1289 .addReg(TempReg, getKillRegState(i == e-1));
1292 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1294 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1295 // call optimization
1296 if (IsReturnBlock) {
1297 unsigned RetOpcode = MBBI->getOpcode();
1298 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1299 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1300 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1301 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1302 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1304 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1305 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1306 .addReg(SPReg).addImm(CallerAllocatedAmt);
1308 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1309 .addImm(CallerAllocatedAmt >> 16);
1310 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1311 .addReg(ScratchReg, RegState::Kill)
1312 .addImm(CallerAllocatedAmt & 0xFFFF);
1313 BuildMI(MBB, MBBI, dl, AddInst)
1316 .addReg(ScratchReg);
1318 } else if (RetOpcode == PPC::TCRETURNdi) {
1319 MBBI = MBB.getLastNonDebugInstr();
1320 MachineOperand &JumpTarget = MBBI->getOperand(0);
1321 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1322 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1323 } else if (RetOpcode == PPC::TCRETURNri) {
1324 MBBI = MBB.getLastNonDebugInstr();
1325 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1326 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1327 } else if (RetOpcode == PPC::TCRETURNai) {
1328 MBBI = MBB.getLastNonDebugInstr();
1329 MachineOperand &JumpTarget = MBBI->getOperand(0);
1330 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1331 } else if (RetOpcode == PPC::TCRETURNdi8) {
1332 MBBI = MBB.getLastNonDebugInstr();
1333 MachineOperand &JumpTarget = MBBI->getOperand(0);
1334 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1335 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1336 } else if (RetOpcode == PPC::TCRETURNri8) {
1337 MBBI = MBB.getLastNonDebugInstr();
1338 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1339 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1340 } else if (RetOpcode == PPC::TCRETURNai8) {
1341 MBBI = MBB.getLastNonDebugInstr();
1342 MachineOperand &JumpTarget = MBBI->getOperand(0);
1343 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1348 void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF,
1349 BitVector &SavedRegs,
1350 RegScavenger *RS) const {
1351 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1353 const PPCRegisterInfo *RegInfo =
1354 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1356 // Save and clear the LR state.
1357 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1358 unsigned LR = RegInfo->getRARegister();
1359 FI->setMustSaveLR(MustSaveLR(MF, LR));
1360 SavedRegs.reset(LR);
1362 // Save R31 if necessary
1363 int FPSI = FI->getFramePointerSaveIndex();
1364 bool isPPC64 = Subtarget.isPPC64();
1365 bool isDarwinABI = Subtarget.isDarwinABI();
1366 MachineFrameInfo *MFI = MF.getFrameInfo();
1368 // If the frame pointer save index hasn't been defined yet.
1369 if (!FPSI && needsFP(MF)) {
1370 // Find out what the fix offset of the frame pointer save area.
1371 int FPOffset = getFramePointerSaveOffset();
1372 // Allocate the frame index for frame pointer save area.
1373 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1375 FI->setFramePointerSaveIndex(FPSI);
1378 int BPSI = FI->getBasePointerSaveIndex();
1379 if (!BPSI && RegInfo->hasBasePointer(MF)) {
1380 int BPOffset = getBasePointerSaveOffset();
1381 // Allocate the frame index for the base pointer save area.
1382 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1384 FI->setBasePointerSaveIndex(BPSI);
1387 // Reserve stack space for the PIC Base register (R30).
1388 // Only used in SVR4 32-bit.
1389 if (FI->usesPICBase()) {
1390 int PBPSI = MFI->CreateFixedObject(4, -8, true);
1391 FI->setPICBasePointerSaveIndex(PBPSI);
1394 // Reserve stack space to move the linkage area to in case of a tail call.
1396 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1397 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1398 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1401 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1402 // function uses CR 2, 3, or 4.
1403 if (!isPPC64 && !isDarwinABI &&
1404 (SavedRegs.test(PPC::CR2) ||
1405 SavedRegs.test(PPC::CR3) ||
1406 SavedRegs.test(PPC::CR4))) {
1407 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1408 FI->setCRSpillFrameIndex(FrameIdx);
1412 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
1413 RegScavenger *RS) const {
1414 // Early exit if not using the SVR4 ABI.
1415 if (!Subtarget.isSVR4ABI()) {
1416 addScavengingSpillSlot(MF, RS);
1420 // Get callee saved register information.
1421 MachineFrameInfo *FFI = MF.getFrameInfo();
1422 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1424 // Early exit if no callee saved registers are modified!
1425 if (CSI.empty() && !needsFP(MF)) {
1426 addScavengingSpillSlot(MF, RS);
1430 unsigned MinGPR = PPC::R31;
1431 unsigned MinG8R = PPC::X31;
1432 unsigned MinFPR = PPC::F31;
1433 unsigned MinVR = PPC::V31;
1435 bool HasGPSaveArea = false;
1436 bool HasG8SaveArea = false;
1437 bool HasFPSaveArea = false;
1438 bool HasVRSAVESaveArea = false;
1439 bool HasVRSaveArea = false;
1441 SmallVector<CalleeSavedInfo, 18> GPRegs;
1442 SmallVector<CalleeSavedInfo, 18> G8Regs;
1443 SmallVector<CalleeSavedInfo, 18> FPRegs;
1444 SmallVector<CalleeSavedInfo, 18> VRegs;
1446 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1447 unsigned Reg = CSI[i].getReg();
1448 if (PPC::GPRCRegClass.contains(Reg)) {
1449 HasGPSaveArea = true;
1451 GPRegs.push_back(CSI[i]);
1456 } else if (PPC::G8RCRegClass.contains(Reg)) {
1457 HasG8SaveArea = true;
1459 G8Regs.push_back(CSI[i]);
1464 } else if (PPC::F8RCRegClass.contains(Reg)) {
1465 HasFPSaveArea = true;
1467 FPRegs.push_back(CSI[i]);
1472 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1473 PPC::CRRCRegClass.contains(Reg)) {
1474 ; // do nothing, as we already know whether CRs are spilled
1475 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1476 HasVRSAVESaveArea = true;
1477 } else if (PPC::VRRCRegClass.contains(Reg)) {
1478 HasVRSaveArea = true;
1480 VRegs.push_back(CSI[i]);
1486 llvm_unreachable("Unknown RegisterClass!");
1490 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1491 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1493 int64_t LowerBound = 0;
1495 // Take into account stack space reserved for tail calls.
1497 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1498 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1499 LowerBound = TCSPDelta;
1502 // The Floating-point register save area is right below the back chain word
1503 // of the previous stack frame.
1504 if (HasFPSaveArea) {
1505 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1506 int FI = FPRegs[i].getFrameIdx();
1508 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1511 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1514 // Check whether the frame pointer register is allocated. If so, make sure it
1515 // is spilled to the correct offset.
1517 HasGPSaveArea = true;
1519 int FI = PFI->getFramePointerSaveIndex();
1520 assert(FI && "No Frame Pointer Save Slot!");
1522 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1525 if (PFI->usesPICBase()) {
1526 HasGPSaveArea = true;
1528 int FI = PFI->getPICBasePointerSaveIndex();
1529 assert(FI && "No PIC Base Pointer Save Slot!");
1531 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1534 const PPCRegisterInfo *RegInfo =
1535 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1536 if (RegInfo->hasBasePointer(MF)) {
1537 HasGPSaveArea = true;
1539 int FI = PFI->getBasePointerSaveIndex();
1540 assert(FI && "No Base Pointer Save Slot!");
1542 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1545 // General register save area starts right below the Floating-point
1546 // register save area.
1547 if (HasGPSaveArea || HasG8SaveArea) {
1548 // Move general register save area spill slots down, taking into account
1549 // the size of the Floating-point register save area.
1550 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1551 int FI = GPRegs[i].getFrameIdx();
1553 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1556 // Move general register save area spill slots down, taking into account
1557 // the size of the Floating-point register save area.
1558 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1559 int FI = G8Regs[i].getFrameIdx();
1561 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1565 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1566 TRI->getEncodingValue(MinG8R));
1568 if (Subtarget.isPPC64()) {
1569 LowerBound -= (31 - MinReg + 1) * 8;
1571 LowerBound -= (31 - MinReg + 1) * 4;
1575 // For 32-bit only, the CR save area is below the general register
1576 // save area. For 64-bit SVR4, the CR save area is addressed relative
1577 // to the stack pointer and hence does not need an adjustment here.
1578 // Only CR2 (the first nonvolatile spilled) has an associated frame
1579 // index so that we have a single uniform save area.
1580 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1581 // Adjust the frame index of the CR spill slot.
1582 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1583 unsigned Reg = CSI[i].getReg();
1585 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1586 // Leave Darwin logic as-is.
1587 || (!Subtarget.isSVR4ABI() &&
1588 (PPC::CRBITRCRegClass.contains(Reg) ||
1589 PPC::CRRCRegClass.contains(Reg)))) {
1590 int FI = CSI[i].getFrameIdx();
1592 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1596 LowerBound -= 4; // The CR save area is always 4 bytes long.
1599 if (HasVRSAVESaveArea) {
1600 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1601 // which have the VRSAVE register class?
1602 // Adjust the frame index of the VRSAVE spill slot.
1603 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1604 unsigned Reg = CSI[i].getReg();
1606 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1607 int FI = CSI[i].getFrameIdx();
1609 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1613 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1616 if (HasVRSaveArea) {
1617 // Insert alignment padding, we need 16-byte alignment.
1618 LowerBound = (LowerBound - 15) & ~(15);
1620 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1621 int FI = VRegs[i].getFrameIdx();
1623 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1627 addScavengingSpillSlot(MF, RS);
1631 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1632 RegScavenger *RS) const {
1633 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1634 // a large stack, which will require scavenging a register to materialize a
1637 // We need to have a scavenger spill slot for spills if the frame size is
1638 // large. In case there is no free register for large-offset addressing,
1639 // this slot is used for the necessary emergency spill. Also, we need the
1640 // slot for dynamic stack allocations.
1642 // The scavenger might be invoked if the frame offset does not fit into
1643 // the 16-bit immediate. We don't know the complete frame size here
1644 // because we've not yet computed callee-saved register spills or the
1645 // needed alignment padding.
1646 unsigned StackSize = determineFrameLayout(MF, false, true);
1647 MachineFrameInfo *MFI = MF.getFrameInfo();
1648 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1649 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1650 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1651 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1652 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1653 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1657 // Might we have over-aligned allocas?
1658 bool HasAlVars = MFI->hasVarSizedObjects() &&
1659 MFI->getMaxAlignment() > getStackAlignment();
1661 // These kinds of spills might need two registers.
1662 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1663 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1671 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1672 MachineBasicBlock::iterator MI,
1673 const std::vector<CalleeSavedInfo> &CSI,
1674 const TargetRegisterInfo *TRI) const {
1676 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1677 // Return false otherwise to maintain pre-existing behavior.
1678 if (!Subtarget.isSVR4ABI())
1681 MachineFunction *MF = MBB.getParent();
1682 const PPCInstrInfo &TII =
1683 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1685 bool CRSpilled = false;
1686 MachineInstrBuilder CRMIB;
1688 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1689 unsigned Reg = CSI[i].getReg();
1690 // Only Darwin actually uses the VRSAVE register, but it can still appear
1691 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1692 // Darwin, ignore it.
1693 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1696 // CR2 through CR4 are the nonvolatile CR fields.
1697 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1699 // Add the callee-saved register as live-in; it's killed at the spill.
1702 if (CRSpilled && IsCRField) {
1703 CRMIB.addReg(Reg, RegState::ImplicitKill);
1707 // Insert the spill to the stack frame.
1709 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1710 if (Subtarget.isPPC64()) {
1711 // The actual spill will happen at the start of the prologue.
1712 FuncInfo->addMustSaveCR(Reg);
1715 FuncInfo->setSpillsCR();
1717 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1718 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1719 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1720 .addReg(Reg, RegState::ImplicitKill);
1722 MBB.insert(MI, CRMIB);
1723 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1725 getKillRegState(true)),
1726 CSI[i].getFrameIdx()));
1729 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1730 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1731 CSI[i].getFrameIdx(), RC, TRI);
1738 restoreCRs(bool isPPC64, bool is31,
1739 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1740 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1741 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1743 MachineFunction *MF = MBB.getParent();
1744 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
1746 unsigned RestoreOp, MoveReg;
1749 // This is handled during epilogue generation.
1752 // 32-bit: FP-relative
1753 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1755 CSI[CSIIndex].getFrameIdx()));
1756 RestoreOp = PPC::MTOCRF;
1761 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1762 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1765 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1766 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1769 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1770 .addReg(MoveReg, getKillRegState(true)));
1773 void PPCFrameLowering::
1774 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1775 MachineBasicBlock::iterator I) const {
1776 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1777 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1778 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1779 // Add (actually subtract) back the amount the callee popped on return.
1780 if (int CalleeAmt = I->getOperand(1).getImm()) {
1781 bool is64Bit = Subtarget.isPPC64();
1783 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1784 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1785 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1786 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1787 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1788 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1789 MachineInstr *MI = I;
1790 DebugLoc dl = MI->getDebugLoc();
1792 if (isInt<16>(CalleeAmt)) {
1793 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1794 .addReg(StackReg, RegState::Kill)
1797 MachineBasicBlock::iterator MBBI = I;
1798 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1799 .addImm(CalleeAmt >> 16);
1800 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1801 .addReg(TmpReg, RegState::Kill)
1802 .addImm(CalleeAmt & 0xFFFF);
1803 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1804 .addReg(StackReg, RegState::Kill)
1809 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1814 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1815 MachineBasicBlock::iterator MI,
1816 const std::vector<CalleeSavedInfo> &CSI,
1817 const TargetRegisterInfo *TRI) const {
1819 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1820 // Return false otherwise to maintain pre-existing behavior.
1821 if (!Subtarget.isSVR4ABI())
1824 MachineFunction *MF = MBB.getParent();
1825 const PPCInstrInfo &TII =
1826 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1827 bool CR2Spilled = false;
1828 bool CR3Spilled = false;
1829 bool CR4Spilled = false;
1830 unsigned CSIIndex = 0;
1832 // Initialize insertion-point logic; we will be restoring in reverse
1834 MachineBasicBlock::iterator I = MI, BeforeI = I;
1835 bool AtStart = I == MBB.begin();
1840 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1841 unsigned Reg = CSI[i].getReg();
1843 // Only Darwin actually uses the VRSAVE register, but it can still appear
1844 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1845 // Darwin, ignore it.
1846 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1849 if (Reg == PPC::CR2) {
1851 // The spill slot is associated only with CR2, which is the
1852 // first nonvolatile spilled. Save it here.
1855 } else if (Reg == PPC::CR3) {
1858 } else if (Reg == PPC::CR4) {
1862 // When we first encounter a non-CR register after seeing at
1863 // least one CR register, restore all spilled CRs together.
1864 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1865 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1866 bool is31 = needsFP(*MF);
1867 restoreCRs(Subtarget.isPPC64(), is31,
1868 CR2Spilled, CR3Spilled, CR4Spilled,
1869 MBB, I, CSI, CSIIndex);
1870 CR2Spilled = CR3Spilled = CR4Spilled = false;
1873 // Default behavior for non-CR saves.
1874 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1875 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1877 assert(I != MBB.begin() &&
1878 "loadRegFromStackSlot didn't insert any code!");
1881 // Insert in reverse order.
1890 // If we haven't yet spilled the CRs, do so now.
1891 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1892 bool is31 = needsFP(*MF);
1893 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1894 MBB, I, CSI, CSIIndex);
1900 bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
1901 return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
1902 MF.getSubtarget<PPCSubtarget>().isPPC64());