1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
50 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
51 "Enable 64-bit instructions">;
52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
53 "Enable 64-bit registers usage for ppc32 [beta]">;
54 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
55 "Enable Altivec instructions">;
56 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
57 "Enable the MFOCRF instruction">;
58 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
59 "Enable the fsqrt instruction">;
60 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
61 "Enable the stfiwx instruction">;
62 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
63 "Enable the isel instruction">;
64 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
65 "Enable the popcnt[dw] instructions">;
66 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
67 "Enable Book E instructions">;
68 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
69 "Enable QPX instructions">;
71 // Note: Future features to add when support is extended to more
74 // CMPB p6, p6x, p7 cmpb
75 // DFP p6, p6x, p7 decimal floating-point instructions
76 // FLT_CVT p7 fcfids, fcfidu, fcfidus, fcfiduz, fctiwuz
77 // FPRND p5x, p6, p6x, p7 frim, frin, frip, friz
78 // FRE p5 through p7 fre (vs. fres, available since p3)
79 // FRSQRTES p5 through p7 frsqrtes (vs. frsqrte, available since p3)
80 // LDBRX p7 load with byte reversal
81 // LFIWAX p6, p6x, p7 lfiwax
83 // POPCNTB p5 through p7 popcntb and related instructions
84 // RECIP_PREC p6, p6x, p7 higher precision reciprocal estimates
85 // VSX p7 vector-scalar instruction set
87 //===----------------------------------------------------------------------===//
88 // Register File Description
89 //===----------------------------------------------------------------------===//
91 include "PPCRegisterInfo.td"
92 include "PPCSchedule.td"
93 include "PPCInstrInfo.td"
95 //===----------------------------------------------------------------------===//
96 // PowerPC processors supported.
99 def : Processor<"generic", G3Itineraries, [Directive32]>;
100 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
102 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
104 def : Processor<"601", G3Itineraries, [Directive601]>;
105 def : Processor<"602", G3Itineraries, [Directive602]>;
106 def : Processor<"603", G3Itineraries, [Directive603]>;
107 def : Processor<"603e", G3Itineraries, [Directive603]>;
108 def : Processor<"603ev", G3Itineraries, [Directive603]>;
109 def : Processor<"604", G3Itineraries, [Directive604]>;
110 def : Processor<"604e", G3Itineraries, [Directive604]>;
111 def : Processor<"620", G3Itineraries, [Directive620]>;
112 def : Processor<"750", G4Itineraries, [Directive750]>;
113 def : Processor<"g3", G3Itineraries, [Directive750]>;
114 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
115 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
116 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
117 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
118 def : Processor<"970", G5Itineraries,
119 [Directive970, FeatureAltivec,
120 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
121 Feature64Bit /*, Feature64BitRegs */]>;
122 def : Processor<"g5", G5Itineraries,
123 [Directive970, FeatureAltivec,
124 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
125 Feature64Bit /*, Feature64BitRegs */]>;
126 def : ProcessorModel<"e500mc", PPCE500mcModel,
127 [DirectiveE500mc, FeatureMFOCRF,
128 FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
129 def : ProcessorModel<"e5500", PPCE5500Model,
130 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
131 FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
132 def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
133 FeatureMFOCRF, FeatureFSqrt,
134 FeatureSTFIWX, FeatureISEL,
135 FeaturePOPCNTD, Feature64Bit
136 /*, Feature64BitRegs */]>;
137 def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
138 FeatureMFOCRF, FeatureFSqrt,
139 FeatureSTFIWX, FeatureISEL,
140 FeaturePOPCNTD, Feature64Bit
141 /*, Feature64BitRegs */,
143 def : Processor<"pwr3", G5Itineraries,
144 [DirectivePwr3, FeatureAltivec, FeatureMFOCRF,
145 FeatureSTFIWX, Feature64Bit]>;
146 def : Processor<"pwr4", G5Itineraries,
147 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
148 FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
149 def : Processor<"pwr5", G5Itineraries,
150 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
151 FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
152 def : Processor<"pwr5x", G5Itineraries,
153 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
154 FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
155 def : Processor<"pwr6", G5Itineraries,
156 [DirectivePwr6, FeatureAltivec,
157 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
158 Feature64Bit /*, Feature64BitRegs */]>;
159 def : Processor<"pwr6x", G5Itineraries,
160 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
161 FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
162 def : Processor<"pwr7", G5Itineraries,
163 [DirectivePwr7, FeatureAltivec,
164 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
165 FeatureISEL, FeaturePOPCNTD, Feature64Bit
166 /*, Feature64BitRegs */]>;
167 def : Processor<"ppc", G3Itineraries, [Directive32]>;
168 def : Processor<"ppc64", G5Itineraries,
169 [Directive64, FeatureAltivec,
170 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
171 Feature64Bit /*, Feature64BitRegs */]>;
174 //===----------------------------------------------------------------------===//
175 // Calling Conventions
176 //===----------------------------------------------------------------------===//
178 include "PPCCallingConv.td"
180 def PPCInstrInfo : InstrInfo {
181 let isLittleEndianEncoding = 1;
184 def PPCAsmWriter : AsmWriter {
185 string AsmWriterClassName = "InstPrinter";
186 bit isMCAsmWriter = 1;
190 // Information about the instructions.
191 let InstructionSet = PPCInstrInfo;
193 let AssemblyWriters = [PPCAsmWriter];