1 //===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "../Target.td"
18 //===----------------------------------------------------------------------===//
19 // Register File Description
20 //===----------------------------------------------------------------------===//
22 include "PPCRegisterInfo.td"
23 include "PPCSchedule.td"
24 include "PPCInstrInfo.td"
28 //===----------------------------------------------------------------------===//
29 // PowerPC Subtarget features.
32 def F64Bit : SubtargetFeature<"64bit",
33 "Should 64 bit instructions be used">;
34 def F64BitRegs : SubtargetFeature<"64bitregs",
35 "Should 64 bit registers be used">;
36 def FAltivec : SubtargetFeature<"altivec",
37 "Should Altivec instructions be used">;
38 def FGPUL : SubtargetFeature<"gpul",
39 "Should GPUL instructions be used">;
40 def FFSQRT : SubtargetFeature<"fsqrt",
41 "Should the fsqrt instruction be used">;
43 //===----------------------------------------------------------------------===//
44 // PowerPC chips sets supported
47 def : Processor<"601", G3Itineraries, []>;
48 def : Processor<"602", G3Itineraries, []>;
49 def : Processor<"603", G3Itineraries, []>;
50 def : Processor<"604", G3Itineraries, []>;
51 def : Processor<"750", G3Itineraries, []>;
52 def : Processor<"7400", G4Itineraries, [FAltivec]>;
53 def : Processor<"g4", G4Itineraries, [FAltivec]>;
54 def : Processor<"7450", G4PlusItineraries, [FAltivec]>;
55 def : Processor<"g4+", G4PlusItineraries, [FAltivec]>;
56 def : Processor<"970", G5Itineraries,
57 [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
58 def : Processor<"g5", G5Itineraries,
59 [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
63 // Pointers on PPC are 32-bits in size.
64 let PointerType = i32;
66 // According to the Mach-O Runtime ABI, these regs are nonvolatile across
68 let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
69 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
70 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
71 F30, F31, CR2, CR3, CR4, LR];
73 // Pull in Instruction Info:
74 let InstructionSet = PowerPCInstrInfo;