1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
50 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
51 "Enable 64-bit instructions">;
52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
53 "Enable 64-bit registers usage for ppc32 [beta]">;
54 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
55 "Use condition-register bits individually">;
56 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
57 "Enable Altivec instructions">;
58 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
59 "Enable the MFOCRF instruction">;
60 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
61 "Enable the fsqrt instruction">;
62 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
63 "Enable the fcpsgn instruction">;
64 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
65 "Enable the fre instruction">;
66 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
67 "Enable the fres instruction">;
68 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
69 "Enable the frsqrte instruction">;
70 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
71 "Enable the frsqrtes instruction">;
72 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
73 "Assume higher precision reciprocal estimates">;
74 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
75 "Enable the stfiwx instruction">;
76 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
77 "Enable the lfiwax instruction">;
78 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
79 "Enable the fri[mnpz] instructions">;
80 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
81 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
82 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
83 "Enable the isel instruction">;
84 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
85 "Enable the popcnt[dw] instructions">;
86 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
87 "Enable the ldbrx instruction">;
88 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
89 "Enable Book E instructions">;
90 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
91 "Enable QPX instructions">;
92 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
93 "Enable VSX instructions">;
95 def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
96 "Treat mftb as deprecated">;
97 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
98 "Treat vector data stream cache control instructions as deprecated">;
100 // Note: Future features to add when support is extended to more
101 // recent ISA levels:
103 // CMPB p6, p6x, p7 cmpb
104 // DFP p6, p6x, p7 decimal floating-point instructions
105 // POPCNTB p5 through p7 popcntb and related instructions
106 // VSX p7 vector-scalar instruction set
108 //===----------------------------------------------------------------------===//
109 // Classes used for relation maps.
110 //===----------------------------------------------------------------------===//
111 // RecFormRel - Filter class used to relate non-record-form instructions with
112 // their record-form variants.
115 //===----------------------------------------------------------------------===//
116 // Relation Map Definitions.
117 //===----------------------------------------------------------------------===//
119 def getRecordFormOpcode : InstrMapping {
120 let FilterClass = "RecFormRel";
121 // Instructions with the same BaseName and Interpretation64Bit values
123 let RowFields = ["BaseName", "Interpretation64Bit"];
124 // Instructions with the same RC value form a column.
125 let ColFields = ["RC"];
126 // The key column are the non-record-form instructions.
128 // Value columns RC=1
129 let ValueCols = [["1"]];
132 def getNonRecordFormOpcode : InstrMapping {
133 let FilterClass = "RecFormRel";
134 // Instructions with the same BaseName and Interpretation64Bit values
136 let RowFields = ["BaseName", "Interpretation64Bit"];
137 // Instructions with the same RC value form a column.
138 let ColFields = ["RC"];
139 // The key column are the record-form instructions.
141 // Value columns are RC=0
142 let ValueCols = [["0"]];
145 //===----------------------------------------------------------------------===//
146 // Register File Description
147 //===----------------------------------------------------------------------===//
149 include "PPCRegisterInfo.td"
150 include "PPCSchedule.td"
151 include "PPCInstrInfo.td"
153 //===----------------------------------------------------------------------===//
154 // PowerPC processors supported.
157 def : Processor<"generic", G3Itineraries, [Directive32]>;
158 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
159 FeatureFRES, FeatureFRSQRTE,
160 FeatureBookE, DeprecatedMFTB]>;
161 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
162 FeatureFRES, FeatureFRSQRTE,
163 FeatureBookE, DeprecatedMFTB]>;
164 def : Processor<"601", G3Itineraries, [Directive601]>;
165 def : Processor<"602", G3Itineraries, [Directive602]>;
166 def : Processor<"603", G3Itineraries, [Directive603,
167 FeatureFRES, FeatureFRSQRTE]>;
168 def : Processor<"603e", G3Itineraries, [Directive603,
169 FeatureFRES, FeatureFRSQRTE]>;
170 def : Processor<"603ev", G3Itineraries, [Directive603,
171 FeatureFRES, FeatureFRSQRTE]>;
172 def : Processor<"604", G3Itineraries, [Directive604,
173 FeatureFRES, FeatureFRSQRTE]>;
174 def : Processor<"604e", G3Itineraries, [Directive604,
175 FeatureFRES, FeatureFRSQRTE]>;
176 def : Processor<"620", G3Itineraries, [Directive620,
177 FeatureFRES, FeatureFRSQRTE]>;
178 def : Processor<"750", G4Itineraries, [Directive750,
179 FeatureFRES, FeatureFRSQRTE]>;
180 def : Processor<"g3", G3Itineraries, [Directive750,
181 FeatureFRES, FeatureFRSQRTE]>;
182 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
183 FeatureFRES, FeatureFRSQRTE]>;
184 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
185 FeatureFRES, FeatureFRSQRTE]>;
186 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
187 FeatureFRES, FeatureFRSQRTE]>;
188 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
189 FeatureFRES, FeatureFRSQRTE]>;
190 def : ProcessorModel<"970", G5Model,
191 [Directive970, FeatureAltivec,
192 FeatureMFOCRF, FeatureFSqrt,
193 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
194 Feature64Bit /*, Feature64BitRegs */]>;
195 def : ProcessorModel<"g5", G5Model,
196 [Directive970, FeatureAltivec,
197 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
198 FeatureFRES, FeatureFRSQRTE,
199 Feature64Bit /*, Feature64BitRegs */,
200 DeprecatedMFTB, DeprecatedDST]>;
201 def : ProcessorModel<"e500mc", PPCE500mcModel,
202 [DirectiveE500mc, FeatureMFOCRF,
203 FeatureSTFIWX, FeatureBookE, FeatureISEL,
205 def : ProcessorModel<"e5500", PPCE5500Model,
206 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
207 FeatureSTFIWX, FeatureBookE, FeatureISEL,
209 def : ProcessorModel<"a2", PPCA2Model,
210 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
211 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
212 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
213 FeatureSTFIWX, FeatureLFIWAX,
214 FeatureFPRND, FeatureFPCVT, FeatureISEL,
215 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
216 /*, Feature64BitRegs */, DeprecatedMFTB]>;
217 def : ProcessorModel<"a2q", PPCA2Model,
218 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
219 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
220 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
221 FeatureSTFIWX, FeatureLFIWAX,
222 FeatureFPRND, FeatureFPCVT, FeatureISEL,
223 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
224 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
225 def : ProcessorModel<"pwr3", G5Model,
226 [DirectivePwr3, FeatureAltivec,
227 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
228 FeatureSTFIWX, Feature64Bit]>;
229 def : ProcessorModel<"pwr4", G5Model,
230 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
231 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
232 FeatureSTFIWX, Feature64Bit]>;
233 def : ProcessorModel<"pwr5", G5Model,
234 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
235 FeatureFSqrt, FeatureFRE, FeatureFRES,
236 FeatureFRSQRTE, FeatureFRSQRTES,
237 FeatureSTFIWX, Feature64Bit,
238 DeprecatedMFTB, DeprecatedDST]>;
239 def : ProcessorModel<"pwr5x", G5Model,
240 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
241 FeatureFSqrt, FeatureFRE, FeatureFRES,
242 FeatureFRSQRTE, FeatureFRSQRTES,
243 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
244 DeprecatedMFTB, DeprecatedDST]>;
245 def : ProcessorModel<"pwr6", G5Model,
246 [DirectivePwr6, FeatureAltivec,
247 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
248 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
249 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
250 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
251 DeprecatedMFTB, DeprecatedDST]>;
252 def : ProcessorModel<"pwr6x", G5Model,
253 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
254 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
255 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
256 FeatureSTFIWX, FeatureLFIWAX,
257 FeatureFPRND, Feature64Bit,
258 DeprecatedMFTB, DeprecatedDST]>;
259 def : ProcessorModel<"pwr7", P7Model,
260 [DirectivePwr7, FeatureAltivec,
261 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
262 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
263 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
264 FeatureFPRND, FeatureFPCVT, FeatureISEL,
265 FeaturePOPCNTD, FeatureLDBRX,
266 Feature64Bit /*, Feature64BitRegs */,
267 DeprecatedMFTB, DeprecatedDST]>;
268 def : Processor<"ppc", G3Itineraries, [Directive32]>;
269 def : ProcessorModel<"ppc64", G5Model,
270 [Directive64, FeatureAltivec,
271 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
272 FeatureFRSQRTE, FeatureSTFIWX,
273 Feature64Bit /*, Feature64BitRegs */]>;
274 def : ProcessorModel<"ppc64le", G5Model,
275 [Directive64, FeatureAltivec,
276 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
277 FeatureFRSQRTE, FeatureSTFIWX,
278 Feature64Bit /*, Feature64BitRegs */]>;
280 //===----------------------------------------------------------------------===//
281 // Calling Conventions
282 //===----------------------------------------------------------------------===//
284 include "PPCCallingConv.td"
286 def PPCInstrInfo : InstrInfo {
287 let isLittleEndianEncoding = 1;
289 // FIXME: Unset this when no longer needed!
290 let decodePositionallyEncodedOperands = 1;
293 def PPCAsmParser : AsmParser {
294 let ShouldEmitMatchRegisterName = 0;
297 def PPCAsmParserVariant : AsmParserVariant {
300 // We do not use hard coded registers in asm strings. However, some
301 // InstAlias definitions use immediate literals. Set RegisterPrefix
302 // so that those are not misinterpreted as registers.
303 string RegisterPrefix = "%";
307 // Information about the instructions.
308 let InstructionSet = PPCInstrInfo;
310 let AssemblyParsers = [PPCAsmParser];
311 let AssemblyParserVariants = [PPCAsmParserVariant];