lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
  50
  51 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  52                                         "Enable 64-bit instructions">;
  53 def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
  54                               "Use software emulation for floating point">;
  55 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  56                               "Enable 64-bit registers usage for ppc32 [beta]">;
  57 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  58                               "Use condition-register bits individually">;
  59 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  60                                         "Enable Altivec instructions">;
  61 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
  62                                         "Enable SPE instructions">;
  63 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  64                                         "Enable the MFOCRF instruction">;
  65 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  66                                         "Enable the fsqrt instruction">;
  67 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  68                                         "Enable the fcpsgn instruction">;
  69 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  70                                         "Enable the fre instruction">;
  71 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  72                                         "Enable the fres instruction">;
  73 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  74                                         "Enable the frsqrte instruction">;
  75 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  76                                         "Enable the frsqrtes instruction">;
  77 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  78                               "Assume higher precision reciprocal estimates">;
  79 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  80                                         "Enable the stfiwx instruction">;
  81 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
  82                                         "Enable the lfiwax instruction">;
  83 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
  84                                         "Enable the fri[mnpz] instructions">;
  85 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
  86   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
  87 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  88                                         "Enable the isel instruction">;
  89 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
  90                                         "Enable the popcnt[dw] instructions">;
  91 def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
  92                                         "Enable the bpermd instruction">;
  93 def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
  94                                         "Enable extended divide instructions">;
  95 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
  96                                         "Enable the ldbrx instruction">;
  97 def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
  98                                         "Enable the cmpb instruction">;
  99 def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
 100                                         "Enable icbt instruction">;
 101 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
 102                                         "Enable Book E instructions",
 103                                         [FeatureICBT]>;
 104 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
 105                               "Has only the msync instruction instead of sync",
 106                               [FeatureBookE]>;
 107 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
 108                                         "Enable E500/E500mc instructions">;
 109 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
 110                                         "Enable PPC 4xx instructions">;
 111 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
 112                                         "Enable PPC 6xx instructions">;
 113 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
 114                                         "Enable QPX instructions">;
 115 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
 116                                         "Enable VSX instructions",
 117                                         [FeatureAltivec]>;
 118 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
 119                                         "Enable POWER8 Altivec instructions",
 120                                         [FeatureAltivec]>;
 121 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
 122                                        "Enable POWER8 Crypto instructions",
 123                                        [FeatureP8Altivec]>;
 124 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
 125                                         "Enable POWER8 vector instructions",
 126                                         [FeatureVSX, FeatureP8Altivec]>;
 127 def FeatureDirectMove :
 128   SubtargetFeature<"direct-move", "HasDirectMove", "true",
 129                    "Enable Power8 direct move instructions",
 130                    [FeatureVSX]>;
 131 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
 132                                              "HasPartwordAtomics", "true",
 133                                              "Enable l[bh]arx and st[bh]cx.">;
 134 def FeatureInvariantFunctionDescriptors :
 135   SubtargetFeature<"invariant-function-descriptors",
 136                    "HasInvariantFunctionDescriptors", "true",
 137                    "Assume function descriptors are invariant">;
 138 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
 139                                   "Enable Hardware Transactional Memory instructions">;
 140 def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
 141                                         "Implement mftb using the mfspr instruction">;
 142 def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
 143                                      "Target supports add/load integer fusion.">;
 144
 145 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 146   "Treat vector data stream cache control instructions as deprecated">;
 147
 148 /*  Since new processors generally contain a superset of features of those that
 149     came before them, the idea is to make implementations of new processors
 150     less error prone and easier to read.
 151     Namely:
 152         list<SubtargetFeature> Power8FeatureList = ...
 153         list<SubtargetFeature> FutureProcessorSpecificFeatureList =
 154             [ features that Power8 does not support ]
 155         list<SubtargetFeature> FutureProcessorFeatureList =
 156             !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
 157
 158     Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
 159     well as providing a single point of definition if the feature set will be
 160     used elsewhere.
 161 */
 162 def ProcessorFeatures {
 163   list<SubtargetFeature> Power7FeatureList =
 164       [DirectivePwr7, FeatureAltivec, FeatureVSX,
 165        FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 166        FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 167        FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 168        FeatureFPRND, FeatureFPCVT, FeatureISEL,
 169        FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
 170        Feature64Bit /*, Feature64BitRegs */,
 171        FeatureBPERMD, FeatureExtDiv,
 172        FeatureMFTB, DeprecatedDST];
 173   list<SubtargetFeature> Power8SpecificFeatures =
 174       [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
 175        FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic,
 176        FeatureFusion];
 177   list<SubtargetFeature> Power8FeatureList =
 178       !listconcat(Power7FeatureList, Power8SpecificFeatures);
 179 }
 180
 181 // Note: Future features to add when support is extended to more
 182 // recent ISA levels:
 183 //
 184 // DFP          p6, p6x, p7        decimal floating-point instructions
 185 // POPCNTB      p5 through p7      popcntb and related instructions
 186
 187 //===----------------------------------------------------------------------===//
 188 // Classes used for relation maps.
 189 //===----------------------------------------------------------------------===//
 190 // RecFormRel - Filter class used to relate non-record-form instructions with
 191 // their record-form variants.
 192 class RecFormRel;
 193
 194 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 195 // FMA instruction forms with their corresponding factor-killing forms.
 196 class AltVSXFMARel {
 197   bit IsVSXFMAAlt = 0;
 198 }
 199
 200 //===----------------------------------------------------------------------===//
 201 // Relation Map Definitions.
 202 //===----------------------------------------------------------------------===//
 203
 204 def getRecordFormOpcode : InstrMapping {
 205   let FilterClass = "RecFormRel";
 206   // Instructions with the same BaseName and Interpretation64Bit values
 207   // form a row.
 208   let RowFields = ["BaseName", "Interpretation64Bit"];
 209   // Instructions with the same RC value form a column.
 210   let ColFields = ["RC"];
 211   // The key column are the non-record-form instructions.
 212   let KeyCol = ["0"];
 213   // Value columns RC=1
 214   let ValueCols = [["1"]];
 215 }
 216
 217 def getNonRecordFormOpcode : InstrMapping {
 218   let FilterClass = "RecFormRel";
 219   // Instructions with the same BaseName and Interpretation64Bit values
 220   // form a row.
 221   let RowFields = ["BaseName", "Interpretation64Bit"];
 222   // Instructions with the same RC value form a column.
 223   let ColFields = ["RC"];
 224   // The key column are the record-form instructions.
 225   let KeyCol = ["1"];
 226   // Value columns are RC=0
 227   let ValueCols = [["0"]];
 228 }
 229
 230 def getAltVSXFMAOpcode : InstrMapping {
 231   let FilterClass = "AltVSXFMARel";
 232   // Instructions with the same BaseName and Interpretation64Bit values
 233   // form a row.
 234   let RowFields = ["BaseName"];
 235   // Instructions with the same RC value form a column.
 236   let ColFields = ["IsVSXFMAAlt"];
 237   // The key column are the (default) addend-killing instructions.
 238   let KeyCol = ["0"];
 239   // Value columns IsVSXFMAAlt=1
 240   let ValueCols = [["1"]];
 241 }
 242
 243 //===----------------------------------------------------------------------===//
 244 // Register File Description
 245 //===----------------------------------------------------------------------===//
 246
 247 include "PPCRegisterInfo.td"
 248 include "PPCSchedule.td"
 249 include "PPCInstrInfo.td"
 250
 251 //===----------------------------------------------------------------------===//
 252 // PowerPC processors supported.
 253 //
 254
 255 def : Processor<"generic", G3Itineraries, [Directive32, FeatureMFTB]>;
 256 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 257                                           FeatureFRES, FeatureFRSQRTE,
 258                                           FeatureICBT, FeatureBookE,
 259                                           FeatureMSYNC, FeatureMFTB]>;
 260 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 261                                           FeatureFRES, FeatureFRSQRTE,
 262                                           FeatureICBT, FeatureBookE,
 263                                           FeatureMSYNC, FeatureMFTB]>;
 264 def : Processor<"601", G3Itineraries, [Directive601]>;
 265 def : Processor<"602", G3Itineraries, [Directive602,
 266                                        FeatureMFTB]>;
 267 def : Processor<"603", G3Itineraries, [Directive603,
 268                                        FeatureFRES, FeatureFRSQRTE,
 269                                        FeatureMFTB]>;
 270 def : Processor<"603e", G3Itineraries, [Directive603,
 271                                         FeatureFRES, FeatureFRSQRTE,
 272                                         FeatureMFTB]>;
 273 def : Processor<"603ev", G3Itineraries, [Directive603,
 274                                          FeatureFRES, FeatureFRSQRTE,
 275                                          FeatureMFTB]>;
 276 def : Processor<"604", G3Itineraries, [Directive604,
 277                                        FeatureFRES, FeatureFRSQRTE,
 278                                        FeatureMFTB]>;
 279 def : Processor<"604e", G3Itineraries, [Directive604,
 280                                         FeatureFRES, FeatureFRSQRTE,
 281                                         FeatureMFTB]>;
 282 def : Processor<"620", G3Itineraries, [Directive620,
 283                                        FeatureFRES, FeatureFRSQRTE,
 284                                        FeatureMFTB]>;
 285 def : Processor<"750", G4Itineraries, [Directive750,
 286                                        FeatureFRES, FeatureFRSQRTE,
 287                                        FeatureMFTB]>;
 288 def : Processor<"g3", G3Itineraries, [Directive750,
 289                                       FeatureFRES, FeatureFRSQRTE,
 290                                       FeatureMFTB]>;
 291 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 292                                         FeatureFRES, FeatureFRSQRTE,
 293                                         FeatureMFTB]>;
 294 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 295                                       FeatureFRES, FeatureFRSQRTE,
 296                                       FeatureMFTB]>;
 297 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 298                                             FeatureFRES, FeatureFRSQRTE,
 299                                             FeatureMFTB]>;
 300 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 301                                            FeatureFRES, FeatureFRSQRTE,
 302                                            FeatureMFTB]>;
 303
 304 def : ProcessorModel<"970", G5Model,
 305                   [Directive970, FeatureAltivec,
 306                    FeatureMFOCRF, FeatureFSqrt,
 307                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 308                    Feature64Bit /*, Feature64BitRegs */,
 309                    FeatureMFTB]>;
 310 def : ProcessorModel<"g5", G5Model,
 311                   [Directive970, FeatureAltivec,
 312                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 313                    FeatureFRES, FeatureFRSQRTE,
 314                    Feature64Bit /*, Feature64BitRegs */,
 315                    FeatureMFTB, DeprecatedDST]>;
 316 def : ProcessorModel<"e500mc", PPCE500mcModel,
 317                   [DirectiveE500mc,
 318                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 319                    FeatureISEL, FeatureMFTB]>;
 320 def : ProcessorModel<"e5500", PPCE5500Model,
 321                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 322                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 323                    FeatureISEL, FeatureMFTB]>;
 324 def : ProcessorModel<"a2", PPCA2Model,
 325                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 326                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 327                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 328                    FeatureSTFIWX, FeatureLFIWAX,
 329                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 330                    FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
 331                /*, Feature64BitRegs */, FeatureMFTB]>;
 332 def : ProcessorModel<"a2q", PPCA2Model,
 333                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 334                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 335                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 336                    FeatureSTFIWX, FeatureLFIWAX,
 337                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 338                    FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
 339                /*, Feature64BitRegs */, FeatureQPX, FeatureMFTB]>;
 340 def : ProcessorModel<"pwr3", G5Model,
 341                   [DirectivePwr3, FeatureAltivec,
 342                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 343                    FeatureSTFIWX, Feature64Bit]>;
 344 def : ProcessorModel<"pwr4", G5Model,
 345                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 346                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 347                    FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
 348 def : ProcessorModel<"pwr5", G5Model,
 349                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 350                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 351                    FeatureFRSQRTE, FeatureFRSQRTES,
 352                    FeatureSTFIWX, Feature64Bit,
 353                    FeatureMFTB, DeprecatedDST]>;
 354 def : ProcessorModel<"pwr5x", G5Model,
 355                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 356                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 357                    FeatureFRSQRTE, FeatureFRSQRTES,
 358                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 359                    FeatureMFTB, DeprecatedDST]>;
 360 def : ProcessorModel<"pwr6", G5Model,
 361                   [DirectivePwr6, FeatureAltivec,
 362                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 363                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 364                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 365                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 366                    FeatureMFTB, DeprecatedDST]>;
 367 def : ProcessorModel<"pwr6x", G5Model,
 368                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 369                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 370                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 371                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 372                    FeatureFPRND, Feature64Bit,
 373                    FeatureMFTB, DeprecatedDST]>;
 374 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
 375 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
 376 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>;
 377 def : ProcessorModel<"ppc64", G5Model,
 378                   [Directive64, FeatureAltivec,
 379                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 380                    FeatureFRSQRTE, FeatureSTFIWX,
 381                    Feature64Bit /*, Feature64BitRegs */,
 382                    FeatureMFTB]>;
 383 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
 384
 385 //===----------------------------------------------------------------------===//
 386 // Calling Conventions
 387 //===----------------------------------------------------------------------===//
 388
 389 include "PPCCallingConv.td"
 390
 391 def PPCInstrInfo : InstrInfo {
 392   let isLittleEndianEncoding = 1;
 393
 394   // FIXME: Unset this when no longer needed!
 395   let decodePositionallyEncodedOperands = 1;
 396
 397   let noNamedPositionallyEncodedOperands = 1;
 398 }
 399
 400 def PPCAsmParser : AsmParser {
 401   let ShouldEmitMatchRegisterName = 0;
 402 }
 403
 404 def PPCAsmParserVariant : AsmParserVariant {
 405   int Variant = 0;
 406
 407   // We do not use hard coded registers in asm strings.  However, some
 408   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 409   // so that those are not misinterpreted as registers.
 410   string RegisterPrefix = "%";
 411   string BreakCharacters = ".";
 412 }
 413
 414 def PPC : Target {
 415   // Information about the instructions.
 416   let InstructionSet = PPCInstrInfo;
 417
 418   let AssemblyParsers = [PPCAsmParser];
 419   let AssemblyParserVariants = [PPCAsmParserVariant];
 420 }