1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCParser/MCAsmLexer.h"
22 #include "llvm/MC/MCParser/MCAsmParser.h"
23 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCTargetAsmParser.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
36 static unsigned RRegs[32] = {
37 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
38 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
39 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
40 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44 PPC::R28, PPC::R29, PPC::R30, PPC::R31
46 static unsigned RRegsNoR0[32] = {
48 PPC::R1, PPC::R2, PPC::R3,
49 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
50 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
51 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55 PPC::R28, PPC::R29, PPC::R30, PPC::R31
57 static unsigned XRegs[32] = {
58 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
59 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
60 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
61 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65 PPC::X28, PPC::X29, PPC::X30, PPC::X31
67 static unsigned XRegsNoX0[32] = {
69 PPC::X1, PPC::X2, PPC::X3,
70 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
71 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
72 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76 PPC::X28, PPC::X29, PPC::X30, PPC::X31
78 static unsigned FRegs[32] = {
79 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
80 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
81 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
82 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86 PPC::F28, PPC::F29, PPC::F30, PPC::F31
88 static unsigned VRegs[32] = {
89 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
90 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
91 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
92 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96 PPC::V28, PPC::V29, PPC::V30, PPC::V31
98 static unsigned VSRegs[64] = {
99 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
100 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
101 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
102 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
108 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
109 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
110 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
111 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
117 static unsigned VSFRegs[64] = {
118 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
119 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
120 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
121 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
127 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
128 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
129 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
130 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
136 static unsigned CRBITRegs[32] = {
137 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
138 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
139 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
140 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
141 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
142 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
143 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
144 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
146 static unsigned CRRegs[8] = {
147 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
148 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
151 // Evaluate an expression containing condition register
152 // or condition register field symbols. Returns positive
153 // value on success, or -1 on error.
155 EvaluateCRExpr(const MCExpr *E) {
156 switch (E->getKind()) {
160 case MCExpr::Constant: {
161 int64_t Res = cast<MCConstantExpr>(E)->getValue();
162 return Res < 0 ? -1 : Res;
165 case MCExpr::SymbolRef: {
166 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
167 StringRef Name = SRE->getSymbol().getName();
169 if (Name == "lt") return 0;
170 if (Name == "gt") return 1;
171 if (Name == "eq") return 2;
172 if (Name == "so") return 3;
173 if (Name == "un") return 3;
175 if (Name == "cr0") return 0;
176 if (Name == "cr1") return 1;
177 if (Name == "cr2") return 2;
178 if (Name == "cr3") return 3;
179 if (Name == "cr4") return 4;
180 if (Name == "cr5") return 5;
181 if (Name == "cr6") return 6;
182 if (Name == "cr7") return 7;
190 case MCExpr::Binary: {
191 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
192 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
193 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
196 if (LHSVal < 0 || RHSVal < 0)
199 switch (BE->getOpcode()) {
201 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
202 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
205 return Res < 0 ? -1 : Res;
209 llvm_unreachable("Invalid expression kind!");
214 class PPCAsmParser : public MCTargetAsmParser {
215 MCSubtargetInfo &STI;
217 const MCInstrInfo &MII;
221 MCAsmParser &getParser() const { return Parser; }
222 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
224 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
225 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
227 bool isPPC64() const { return IsPPC64; }
228 bool isDarwin() const { return IsDarwin; }
230 bool MatchRegisterName(const AsmToken &Tok,
231 unsigned &RegNo, int64_t &IntVal);
233 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
235 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
236 PPCMCExpr::VariantKind &Variant);
237 const MCExpr *FixupVariantKind(const MCExpr *E);
238 bool ParseExpression(const MCExpr *&EVal);
239 bool ParseDarwinExpression(const MCExpr *&EVal);
241 bool ParseOperand(OperandVector &Operands);
243 bool ParseDirectiveWord(unsigned Size, SMLoc L);
244 bool ParseDirectiveTC(unsigned Size, SMLoc L);
245 bool ParseDirectiveMachine(SMLoc L);
246 bool ParseDarwinDirectiveMachine(SMLoc L);
247 bool ParseDirectiveAbiVersion(SMLoc L);
249 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
250 OperandVector &Operands, MCStreamer &Out,
252 bool MatchingInlineAsm) override;
254 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
256 /// @name Auto-generated Match Functions
259 #define GET_ASSEMBLER_HEADER
260 #include "PPCGenAsmMatcher.inc"
266 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
267 const MCInstrInfo &_MII,
268 const MCTargetOptions &Options)
269 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
270 // Check for 64-bit vs. 32-bit pointer mode.
271 Triple TheTriple(STI.getTargetTriple());
272 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
273 TheTriple.getArch() == Triple::ppc64le);
274 IsDarwin = TheTriple.isMacOSX();
275 // Initialize the set of available features.
276 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
279 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
280 SMLoc NameLoc, OperandVector &Operands) override;
282 bool ParseDirective(AsmToken DirectiveID) override;
284 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
285 unsigned Kind) override;
287 const MCExpr *applyModifierToExpr(const MCExpr *E,
288 MCSymbolRefExpr::VariantKind,
289 MCContext &Ctx) override;
292 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
294 struct PPCOperand : public MCParsedAsmOperand {
302 SMLoc StartLoc, EndLoc;
316 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
320 const MCSymbolRefExpr *Sym;
327 struct TLSRegOp TLSReg;
330 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
332 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
334 StartLoc = o.StartLoc;
353 /// getStartLoc - Get the location of the first token of this operand.
354 SMLoc getStartLoc() const override { return StartLoc; }
356 /// getEndLoc - Get the location of the last token of this operand.
357 SMLoc getEndLoc() const override { return EndLoc; }
359 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
360 bool isPPC64() const { return IsPPC64; }
362 int64_t getImm() const {
363 assert(Kind == Immediate && "Invalid access!");
367 const MCExpr *getExpr() const {
368 assert(Kind == Expression && "Invalid access!");
372 int64_t getExprCRVal() const {
373 assert(Kind == Expression && "Invalid access!");
377 const MCExpr *getTLSReg() const {
378 assert(Kind == TLSRegister && "Invalid access!");
382 unsigned getReg() const override {
383 assert(isRegNumber() && "Invalid access!");
384 return (unsigned) Imm.Val;
387 unsigned getVSReg() const {
388 assert(isVSRegNumber() && "Invalid access!");
389 return (unsigned) Imm.Val;
392 unsigned getCCReg() const {
393 assert(isCCRegNumber() && "Invalid access!");
394 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
397 unsigned getCRBit() const {
398 assert(isCRBitNumber() && "Invalid access!");
399 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
402 unsigned getCRBitMask() const {
403 assert(isCRBitMask() && "Invalid access!");
404 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
407 bool isToken() const override { return Kind == Token; }
408 bool isImm() const override { return Kind == Immediate || Kind == Expression; }
409 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
410 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
411 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
412 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
413 bool isU16Imm() const { return Kind == Expression ||
414 (Kind == Immediate && isUInt<16>(getImm())); }
415 bool isS16Imm() const { return Kind == Expression ||
416 (Kind == Immediate && isInt<16>(getImm())); }
417 bool isS16ImmX4() const { return Kind == Expression ||
418 (Kind == Immediate && isInt<16>(getImm()) &&
419 (getImm() & 3) == 0); }
420 bool isS17Imm() const { return Kind == Expression ||
421 (Kind == Immediate && isInt<17>(getImm())); }
422 bool isTLSReg() const { return Kind == TLSRegister; }
423 bool isDirectBr() const { return Kind == Expression ||
424 (Kind == Immediate && isInt<26>(getImm()) &&
425 (getImm() & 3) == 0); }
426 bool isCondBr() const { return Kind == Expression ||
427 (Kind == Immediate && isInt<16>(getImm()) &&
428 (getImm() & 3) == 0); }
429 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
430 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
431 bool isCCRegNumber() const { return (Kind == Expression
432 && isUInt<3>(getExprCRVal())) ||
434 && isUInt<3>(getImm())); }
435 bool isCRBitNumber() const { return (Kind == Expression
436 && isUInt<5>(getExprCRVal())) ||
438 && isUInt<5>(getImm())); }
439 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
440 isPowerOf2_32(getImm()); }
441 bool isMem() const override { return false; }
442 bool isReg() const override { return false; }
444 void addRegOperands(MCInst &Inst, unsigned N) const {
445 llvm_unreachable("addRegOperands");
448 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
449 assert(N == 1 && "Invalid number of operands!");
450 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
453 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
454 assert(N == 1 && "Invalid number of operands!");
455 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
458 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
459 assert(N == 1 && "Invalid number of operands!");
460 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
463 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
464 assert(N == 1 && "Invalid number of operands!");
465 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
468 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
470 addRegG8RCOperands(Inst, N);
472 addRegGPRCOperands(Inst, N);
475 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
477 addRegG8RCNoX0Operands(Inst, N);
479 addRegGPRCNoR0Operands(Inst, N);
482 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
483 assert(N == 1 && "Invalid number of operands!");
484 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
487 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
488 assert(N == 1 && "Invalid number of operands!");
489 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
492 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
493 assert(N == 1 && "Invalid number of operands!");
494 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
497 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
498 assert(N == 1 && "Invalid number of operands!");
499 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
502 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
503 assert(N == 1 && "Invalid number of operands!");
504 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
507 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
508 assert(N == 1 && "Invalid number of operands!");
509 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
512 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
513 assert(N == 1 && "Invalid number of operands!");
514 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
517 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
518 assert(N == 1 && "Invalid number of operands!");
519 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
522 void addImmOperands(MCInst &Inst, unsigned N) const {
523 assert(N == 1 && "Invalid number of operands!");
524 if (Kind == Immediate)
525 Inst.addOperand(MCOperand::CreateImm(getImm()));
527 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
530 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
531 assert(N == 1 && "Invalid number of operands!");
532 if (Kind == Immediate)
533 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
535 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
538 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
539 assert(N == 1 && "Invalid number of operands!");
540 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
543 StringRef getToken() const {
544 assert(Kind == Token && "Invalid access!");
545 return StringRef(Tok.Data, Tok.Length);
548 void print(raw_ostream &OS) const override;
550 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
552 auto Op = make_unique<PPCOperand>(Token);
553 Op->Tok.Data = Str.data();
554 Op->Tok.Length = Str.size();
557 Op->IsPPC64 = IsPPC64;
561 static std::unique_ptr<PPCOperand>
562 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
563 // Allocate extra memory for the string and copy it.
564 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
565 // deleter which will destroy them by simply using "delete", not correctly
566 // calling operator delete on this extra memory after calling the dtor
568 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
569 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
570 Op->Tok.Data = (const char *)(Op.get() + 1);
571 Op->Tok.Length = Str.size();
572 std::memcpy((void *)Op->Tok.Data, Str.data(), Str.size());
575 Op->IsPPC64 = IsPPC64;
579 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
581 auto Op = make_unique<PPCOperand>(Immediate);
585 Op->IsPPC64 = IsPPC64;
589 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
590 SMLoc E, bool IsPPC64) {
591 auto Op = make_unique<PPCOperand>(Expression);
593 Op->Expr.CRVal = EvaluateCRExpr(Val);
596 Op->IsPPC64 = IsPPC64;
600 static std::unique_ptr<PPCOperand>
601 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
602 auto Op = make_unique<PPCOperand>(TLSRegister);
603 Op->TLSReg.Sym = Sym;
606 Op->IsPPC64 = IsPPC64;
610 static std::unique_ptr<PPCOperand>
611 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
612 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
613 return CreateImm(CE->getValue(), S, E, IsPPC64);
615 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
616 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
617 return CreateTLSReg(SRE, S, E, IsPPC64);
619 return CreateExpr(Val, S, E, IsPPC64);
623 } // end anonymous namespace.
625 void PPCOperand::print(raw_ostream &OS) const {
628 OS << "'" << getToken() << "'";
634 getExpr()->print(OS);
637 getTLSReg()->print(OS);
642 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
643 const OperandVector &Operands) {
644 int Opcode = Inst.getOpcode();
648 TmpInst.setOpcode(PPC::LA);
649 TmpInst.addOperand(Inst.getOperand(0));
650 TmpInst.addOperand(Inst.getOperand(2));
651 TmpInst.addOperand(Inst.getOperand(1));
657 int64_t N = Inst.getOperand(2).getImm();
658 TmpInst.setOpcode(PPC::ADDI);
659 TmpInst.addOperand(Inst.getOperand(0));
660 TmpInst.addOperand(Inst.getOperand(1));
661 TmpInst.addOperand(MCOperand::CreateImm(-N));
667 int64_t N = Inst.getOperand(2).getImm();
668 TmpInst.setOpcode(PPC::ADDIS);
669 TmpInst.addOperand(Inst.getOperand(0));
670 TmpInst.addOperand(Inst.getOperand(1));
671 TmpInst.addOperand(MCOperand::CreateImm(-N));
677 int64_t N = Inst.getOperand(2).getImm();
678 TmpInst.setOpcode(PPC::ADDIC);
679 TmpInst.addOperand(Inst.getOperand(0));
680 TmpInst.addOperand(Inst.getOperand(1));
681 TmpInst.addOperand(MCOperand::CreateImm(-N));
687 int64_t N = Inst.getOperand(2).getImm();
688 TmpInst.setOpcode(PPC::ADDICo);
689 TmpInst.addOperand(Inst.getOperand(0));
690 TmpInst.addOperand(Inst.getOperand(1));
691 TmpInst.addOperand(MCOperand::CreateImm(-N));
698 int64_t N = Inst.getOperand(2).getImm();
699 int64_t B = Inst.getOperand(3).getImm();
700 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
701 TmpInst.addOperand(Inst.getOperand(0));
702 TmpInst.addOperand(Inst.getOperand(1));
703 TmpInst.addOperand(MCOperand::CreateImm(B));
704 TmpInst.addOperand(MCOperand::CreateImm(0));
705 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
712 int64_t N = Inst.getOperand(2).getImm();
713 int64_t B = Inst.getOperand(3).getImm();
714 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
715 TmpInst.addOperand(Inst.getOperand(0));
716 TmpInst.addOperand(Inst.getOperand(1));
717 TmpInst.addOperand(MCOperand::CreateImm(B + N));
718 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
719 TmpInst.addOperand(MCOperand::CreateImm(31));
726 int64_t N = Inst.getOperand(2).getImm();
727 int64_t B = Inst.getOperand(3).getImm();
728 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
729 TmpInst.addOperand(Inst.getOperand(0));
730 TmpInst.addOperand(Inst.getOperand(0));
731 TmpInst.addOperand(Inst.getOperand(1));
732 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
733 TmpInst.addOperand(MCOperand::CreateImm(B));
734 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
741 int64_t N = Inst.getOperand(2).getImm();
742 int64_t B = Inst.getOperand(3).getImm();
743 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
744 TmpInst.addOperand(Inst.getOperand(0));
745 TmpInst.addOperand(Inst.getOperand(0));
746 TmpInst.addOperand(Inst.getOperand(1));
747 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
748 TmpInst.addOperand(MCOperand::CreateImm(B));
749 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
756 int64_t N = Inst.getOperand(2).getImm();
757 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
758 TmpInst.addOperand(Inst.getOperand(0));
759 TmpInst.addOperand(Inst.getOperand(1));
760 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
761 TmpInst.addOperand(MCOperand::CreateImm(0));
762 TmpInst.addOperand(MCOperand::CreateImm(31));
769 int64_t N = Inst.getOperand(2).getImm();
770 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
771 TmpInst.addOperand(Inst.getOperand(0));
772 TmpInst.addOperand(Inst.getOperand(1));
773 TmpInst.addOperand(MCOperand::CreateImm(N));
774 TmpInst.addOperand(MCOperand::CreateImm(0));
775 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
782 int64_t N = Inst.getOperand(2).getImm();
783 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
784 TmpInst.addOperand(Inst.getOperand(0));
785 TmpInst.addOperand(Inst.getOperand(1));
786 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
787 TmpInst.addOperand(MCOperand::CreateImm(N));
788 TmpInst.addOperand(MCOperand::CreateImm(31));
795 int64_t N = Inst.getOperand(2).getImm();
796 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
797 TmpInst.addOperand(Inst.getOperand(0));
798 TmpInst.addOperand(Inst.getOperand(1));
799 TmpInst.addOperand(MCOperand::CreateImm(0));
800 TmpInst.addOperand(MCOperand::CreateImm(0));
801 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
806 case PPC::CLRLSLWIo: {
808 int64_t B = Inst.getOperand(2).getImm();
809 int64_t N = Inst.getOperand(3).getImm();
810 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
811 TmpInst.addOperand(Inst.getOperand(0));
812 TmpInst.addOperand(Inst.getOperand(1));
813 TmpInst.addOperand(MCOperand::CreateImm(N));
814 TmpInst.addOperand(MCOperand::CreateImm(B - N));
815 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
822 int64_t N = Inst.getOperand(2).getImm();
823 int64_t B = Inst.getOperand(3).getImm();
824 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
825 TmpInst.addOperand(Inst.getOperand(0));
826 TmpInst.addOperand(Inst.getOperand(1));
827 TmpInst.addOperand(MCOperand::CreateImm(B));
828 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
835 int64_t N = Inst.getOperand(2).getImm();
836 int64_t B = Inst.getOperand(3).getImm();
837 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
838 TmpInst.addOperand(Inst.getOperand(0));
839 TmpInst.addOperand(Inst.getOperand(1));
840 TmpInst.addOperand(MCOperand::CreateImm(B + N));
841 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
848 int64_t N = Inst.getOperand(2).getImm();
849 int64_t B = Inst.getOperand(3).getImm();
850 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
851 TmpInst.addOperand(Inst.getOperand(0));
852 TmpInst.addOperand(Inst.getOperand(0));
853 TmpInst.addOperand(Inst.getOperand(1));
854 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
855 TmpInst.addOperand(MCOperand::CreateImm(B));
862 int64_t N = Inst.getOperand(2).getImm();
863 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
864 TmpInst.addOperand(Inst.getOperand(0));
865 TmpInst.addOperand(Inst.getOperand(1));
866 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
867 TmpInst.addOperand(MCOperand::CreateImm(0));
874 int64_t N = Inst.getOperand(2).getImm();
875 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
876 TmpInst.addOperand(Inst.getOperand(0));
877 TmpInst.addOperand(Inst.getOperand(1));
878 TmpInst.addOperand(MCOperand::CreateImm(N));
879 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
886 int64_t N = Inst.getOperand(2).getImm();
887 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
888 TmpInst.addOperand(Inst.getOperand(0));
889 TmpInst.addOperand(Inst.getOperand(1));
890 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
891 TmpInst.addOperand(MCOperand::CreateImm(N));
898 int64_t N = Inst.getOperand(2).getImm();
899 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
900 TmpInst.addOperand(Inst.getOperand(0));
901 TmpInst.addOperand(Inst.getOperand(1));
902 TmpInst.addOperand(MCOperand::CreateImm(0));
903 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
908 case PPC::CLRLSLDIo: {
910 int64_t B = Inst.getOperand(2).getImm();
911 int64_t N = Inst.getOperand(3).getImm();
912 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
913 TmpInst.addOperand(Inst.getOperand(0));
914 TmpInst.addOperand(Inst.getOperand(1));
915 TmpInst.addOperand(MCOperand::CreateImm(N));
916 TmpInst.addOperand(MCOperand::CreateImm(B - N));
923 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
924 OperandVector &Operands,
925 MCStreamer &Out, unsigned &ErrorInfo,
926 bool MatchingInlineAsm) {
929 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
932 // Post-process instructions (typically extended mnemonics)
933 ProcessInstruction(Inst, Operands);
935 Out.EmitInstruction(Inst, STI);
937 case Match_MissingFeature:
938 return Error(IDLoc, "instruction use requires an option to be enabled");
939 case Match_MnemonicFail:
940 return Error(IDLoc, "unrecognized instruction mnemonic");
941 case Match_InvalidOperand: {
942 SMLoc ErrorLoc = IDLoc;
943 if (ErrorInfo != ~0U) {
944 if (ErrorInfo >= Operands.size())
945 return Error(IDLoc, "too few operands for instruction");
947 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
948 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
951 return Error(ErrorLoc, "invalid operand for instruction");
955 llvm_unreachable("Implement any new match types added!");
959 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
960 if (Tok.is(AsmToken::Identifier)) {
961 StringRef Name = Tok.getString();
963 if (Name.equals_lower("lr")) {
964 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
967 } else if (Name.equals_lower("ctr")) {
968 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
971 } else if (Name.equals_lower("vrsave")) {
975 } else if (Name.startswith_lower("r") &&
976 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
977 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
979 } else if (Name.startswith_lower("f") &&
980 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
981 RegNo = FRegs[IntVal];
983 } else if (Name.startswith_lower("v") &&
984 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
985 RegNo = VRegs[IntVal];
987 } else if (Name.startswith_lower("cr") &&
988 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
989 RegNo = CRRegs[IntVal];
998 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
999 const AsmToken &Tok = Parser.getTok();
1000 StartLoc = Tok.getLoc();
1001 EndLoc = Tok.getEndLoc();
1005 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1006 Parser.Lex(); // Eat identifier token.
1010 return Error(StartLoc, "invalid register name");
1013 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1014 /// the expression and check for VK_PPC_LO/HI/HA
1015 /// symbol variants. If all symbols with modifier use the same
1016 /// variant, return the corresponding PPCMCExpr::VariantKind,
1017 /// and a modified expression using the default symbol variant.
1018 /// Otherwise, return NULL.
1019 const MCExpr *PPCAsmParser::
1020 ExtractModifierFromExpr(const MCExpr *E,
1021 PPCMCExpr::VariantKind &Variant) {
1022 MCContext &Context = getParser().getContext();
1023 Variant = PPCMCExpr::VK_PPC_None;
1025 switch (E->getKind()) {
1026 case MCExpr::Target:
1027 case MCExpr::Constant:
1030 case MCExpr::SymbolRef: {
1031 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1033 switch (SRE->getKind()) {
1034 case MCSymbolRefExpr::VK_PPC_LO:
1035 Variant = PPCMCExpr::VK_PPC_LO;
1037 case MCSymbolRefExpr::VK_PPC_HI:
1038 Variant = PPCMCExpr::VK_PPC_HI;
1040 case MCSymbolRefExpr::VK_PPC_HA:
1041 Variant = PPCMCExpr::VK_PPC_HA;
1043 case MCSymbolRefExpr::VK_PPC_HIGHER:
1044 Variant = PPCMCExpr::VK_PPC_HIGHER;
1046 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1047 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1049 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1050 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1052 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1053 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1059 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1062 case MCExpr::Unary: {
1063 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1064 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1067 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1070 case MCExpr::Binary: {
1071 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1072 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1073 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1074 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1079 if (!LHS) LHS = BE->getLHS();
1080 if (!RHS) RHS = BE->getRHS();
1082 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1083 Variant = RHSVariant;
1084 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1085 Variant = LHSVariant;
1086 else if (LHSVariant == RHSVariant)
1087 Variant = LHSVariant;
1091 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1095 llvm_unreachable("Invalid expression kind!");
1098 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1099 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1100 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1101 /// FIXME: This is a hack.
1102 const MCExpr *PPCAsmParser::
1103 FixupVariantKind(const MCExpr *E) {
1104 MCContext &Context = getParser().getContext();
1106 switch (E->getKind()) {
1107 case MCExpr::Target:
1108 case MCExpr::Constant:
1111 case MCExpr::SymbolRef: {
1112 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1113 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1115 switch (SRE->getKind()) {
1116 case MCSymbolRefExpr::VK_TLSGD:
1117 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1119 case MCSymbolRefExpr::VK_TLSLD:
1120 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1125 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1128 case MCExpr::Unary: {
1129 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1130 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1131 if (Sub == UE->getSubExpr())
1133 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1136 case MCExpr::Binary: {
1137 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1138 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1139 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1140 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1142 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1146 llvm_unreachable("Invalid expression kind!");
1149 /// ParseExpression. This differs from the default "parseExpression" in that
1150 /// it handles modifiers.
1152 ParseExpression(const MCExpr *&EVal) {
1155 return ParseDarwinExpression(EVal);
1158 // Handle \code @l/@ha \endcode
1159 if (getParser().parseExpression(EVal))
1162 EVal = FixupVariantKind(EVal);
1164 PPCMCExpr::VariantKind Variant;
1165 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1167 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1172 /// ParseDarwinExpression. (MachO Platforms)
1173 /// This differs from the default "parseExpression" in that it handles detection
1174 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1175 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1176 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1177 /// for this to be done at a higher level.
1179 ParseDarwinExpression(const MCExpr *&EVal) {
1180 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1181 switch (getLexer().getKind()) {
1184 case AsmToken::Identifier:
1185 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1186 // something starting with any other char should be part of the
1187 // asm syntax. If handwritten asm includes an identifier like lo16,
1188 // then all bets are off - but no-one would do that, right?
1189 StringRef poss = Parser.getTok().getString();
1190 if (poss.equals_lower("lo16")) {
1191 Variant = PPCMCExpr::VK_PPC_LO;
1192 } else if (poss.equals_lower("hi16")) {
1193 Variant = PPCMCExpr::VK_PPC_HI;
1194 } else if (poss.equals_lower("ha16")) {
1195 Variant = PPCMCExpr::VK_PPC_HA;
1197 if (Variant != PPCMCExpr::VK_PPC_None) {
1198 Parser.Lex(); // Eat the xx16
1199 if (getLexer().isNot(AsmToken::LParen))
1200 return Error(Parser.getTok().getLoc(), "expected '('");
1201 Parser.Lex(); // Eat the '('
1206 if (getParser().parseExpression(EVal))
1209 if (Variant != PPCMCExpr::VK_PPC_None) {
1210 if (getLexer().isNot(AsmToken::RParen))
1211 return Error(Parser.getTok().getLoc(), "expected ')'");
1212 Parser.Lex(); // Eat the ')'
1213 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1219 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1221 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1222 SMLoc S = Parser.getTok().getLoc();
1223 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1226 // Attempt to parse the next token as an immediate
1227 switch (getLexer().getKind()) {
1228 // Special handling for register names. These are interpreted
1229 // as immediates corresponding to the register number.
1230 case AsmToken::Percent:
1231 Parser.Lex(); // Eat the '%'.
1234 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1235 Parser.Lex(); // Eat the identifier token.
1236 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1239 return Error(S, "invalid register name");
1241 case AsmToken::Identifier:
1242 // Note that non-register-name identifiers from the compiler will begin
1243 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1244 // identifiers like r31foo - so we fall through in the event that parsing
1245 // a register name fails.
1249 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1250 Parser.Lex(); // Eat the identifier token.
1251 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1255 // Fall-through to process non-register-name identifiers as expression.
1256 // All other expressions
1257 case AsmToken::LParen:
1258 case AsmToken::Plus:
1259 case AsmToken::Minus:
1260 case AsmToken::Integer:
1262 case AsmToken::Dollar:
1263 case AsmToken::Exclaim:
1264 case AsmToken::Tilde:
1265 if (!ParseExpression(EVal))
1269 return Error(S, "unknown operand");
1272 // Push the parsed operand into the list of operands
1273 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1275 // Check whether this is a TLS call expression
1276 bool TLSCall = false;
1277 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1278 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1280 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1281 const MCExpr *TLSSym;
1283 Parser.Lex(); // Eat the '('.
1284 S = Parser.getTok().getLoc();
1285 if (ParseExpression(TLSSym))
1286 return Error(S, "invalid TLS call expression");
1287 if (getLexer().isNot(AsmToken::RParen))
1288 return Error(Parser.getTok().getLoc(), "missing ')'");
1289 E = Parser.getTok().getLoc();
1290 Parser.Lex(); // Eat the ')'.
1292 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1295 // Otherwise, check for D-form memory operands
1296 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1297 Parser.Lex(); // Eat the '('.
1298 S = Parser.getTok().getLoc();
1301 switch (getLexer().getKind()) {
1302 case AsmToken::Percent:
1303 Parser.Lex(); // Eat the '%'.
1305 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1306 return Error(S, "invalid register name");
1307 Parser.Lex(); // Eat the identifier token.
1310 case AsmToken::Integer:
1312 if (getParser().parseAbsoluteExpression(IntVal) ||
1313 IntVal < 0 || IntVal > 31)
1314 return Error(S, "invalid register number");
1316 return Error(S, "unexpected integer value");
1320 case AsmToken::Identifier:
1323 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1324 Parser.Lex(); // Eat the identifier token.
1331 return Error(S, "invalid memory operand");
1334 if (getLexer().isNot(AsmToken::RParen))
1335 return Error(Parser.getTok().getLoc(), "missing ')'");
1336 E = Parser.getTok().getLoc();
1337 Parser.Lex(); // Eat the ')'.
1339 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1345 /// Parse an instruction mnemonic followed by its operands.
1346 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1347 SMLoc NameLoc, OperandVector &Operands) {
1348 // The first operand is the token for the instruction name.
1349 // If the next character is a '+' or '-', we need to add it to the
1350 // instruction name, to match what TableGen is doing.
1351 std::string NewOpcode;
1352 if (getLexer().is(AsmToken::Plus)) {
1358 if (getLexer().is(AsmToken::Minus)) {
1364 // If the instruction ends in a '.', we need to create a separate
1365 // token for it, to match what TableGen is doing.
1366 size_t Dot = Name.find('.');
1367 StringRef Mnemonic = Name.slice(0, Dot);
1368 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1370 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1372 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1373 if (Dot != StringRef::npos) {
1374 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1375 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1376 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1378 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1380 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1383 // If there are no more operands then finish
1384 if (getLexer().is(AsmToken::EndOfStatement))
1387 // Parse the first operand
1388 if (ParseOperand(Operands))
1391 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1392 getLexer().is(AsmToken::Comma)) {
1393 // Consume the comma token
1396 // Parse the next operand
1397 if (ParseOperand(Operands))
1404 /// ParseDirective parses the PPC specific directives
1405 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1406 StringRef IDVal = DirectiveID.getIdentifier();
1408 if (IDVal == ".word")
1409 return ParseDirectiveWord(2, DirectiveID.getLoc());
1410 if (IDVal == ".llong")
1411 return ParseDirectiveWord(8, DirectiveID.getLoc());
1413 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1414 if (IDVal == ".machine")
1415 return ParseDirectiveMachine(DirectiveID.getLoc());
1416 if (IDVal == ".abiversion")
1417 return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1419 if (IDVal == ".machine")
1420 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1425 /// ParseDirectiveWord
1426 /// ::= .word [ expression (, expression)* ]
1427 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1428 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1430 const MCExpr *Value;
1431 if (getParser().parseExpression(Value))
1434 getParser().getStreamer().EmitValue(Value, Size);
1436 if (getLexer().is(AsmToken::EndOfStatement))
1439 if (getLexer().isNot(AsmToken::Comma))
1440 return Error(L, "unexpected token in directive");
1449 /// ParseDirectiveTC
1450 /// ::= .tc [ symbol (, expression)* ]
1451 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1452 // Skip TC symbol, which is only used with XCOFF.
1453 while (getLexer().isNot(AsmToken::EndOfStatement)
1454 && getLexer().isNot(AsmToken::Comma))
1456 if (getLexer().isNot(AsmToken::Comma)) {
1457 Error(L, "unexpected token in directive");
1462 // Align to word size.
1463 getParser().getStreamer().EmitValueToAlignment(Size);
1465 // Emit expressions.
1466 return ParseDirectiveWord(Size, L);
1469 /// ParseDirectiveMachine (ELF platforms)
1470 /// ::= .machine [ cpu | "push" | "pop" ]
1471 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1472 if (getLexer().isNot(AsmToken::Identifier) &&
1473 getLexer().isNot(AsmToken::String)) {
1474 Error(L, "unexpected token in directive");
1478 StringRef CPU = Parser.getTok().getIdentifier();
1481 // FIXME: Right now, the parser always allows any available
1482 // instruction, so the .machine directive is not useful.
1483 // Implement ".machine any" (by doing nothing) for the benefit
1484 // of existing assembler code. Likewise, we can then implement
1485 // ".machine push" and ".machine pop" as no-op.
1486 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1487 Error(L, "unrecognized machine type");
1491 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1492 Error(L, "unexpected token in directive");
1495 PPCTargetStreamer &TStreamer =
1496 *static_cast<PPCTargetStreamer *>(
1497 getParser().getStreamer().getTargetStreamer());
1498 TStreamer.emitMachine(CPU);
1503 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1504 /// ::= .machine cpu-identifier
1505 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1506 if (getLexer().isNot(AsmToken::Identifier) &&
1507 getLexer().isNot(AsmToken::String)) {
1508 Error(L, "unexpected token in directive");
1512 StringRef CPU = Parser.getTok().getIdentifier();
1515 // FIXME: this is only the 'default' set of cpu variants.
1516 // However we don't act on this information at present, this is simply
1517 // allowing parsing to proceed with minimal sanity checking.
1518 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1519 Error(L, "unrecognized cpu type");
1523 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1524 Error(L, "wrong cpu type specified for 64bit");
1527 if (!isPPC64() && CPU == "ppc64") {
1528 Error(L, "wrong cpu type specified for 32bit");
1532 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1533 Error(L, "unexpected token in directive");
1540 /// ParseDirectiveAbiVersion
1541 /// ::= .abiversion constant-expression
1542 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1544 if (getParser().parseAbsoluteExpression(AbiVersion)){
1545 Error(L, "expected constant expression");
1548 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1549 Error(L, "unexpected token in directive");
1553 PPCTargetStreamer &TStreamer =
1554 *static_cast<PPCTargetStreamer *>(
1555 getParser().getStreamer().getTargetStreamer());
1556 TStreamer.emitAbiVersion(AbiVersion);
1561 /// Force static initialization.
1562 extern "C" void LLVMInitializePowerPCAsmParser() {
1563 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1564 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1565 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1568 #define GET_REGISTER_MATCHER
1569 #define GET_MATCHER_IMPLEMENTATION
1570 #include "PPCGenAsmMatcher.inc"
1572 // Define this matcher function after the auto-generated include so we
1573 // have the match class enum definitions.
1574 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1576 // If the kind is a token for a literal immediate, check if our asm
1577 // operand matches. This is for InstAliases which have a fixed-value
1578 // immediate in the syntax.
1581 case MCK_0: ImmVal = 0; break;
1582 case MCK_1: ImmVal = 1; break;
1583 case MCK_2: ImmVal = 2; break;
1584 case MCK_3: ImmVal = 3; break;
1585 default: return Match_InvalidOperand;
1588 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1589 if (Op.isImm() && Op.getImm() == ImmVal)
1590 return Match_Success;
1592 return Match_InvalidOperand;
1596 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1597 MCSymbolRefExpr::VariantKind Variant,
1600 case MCSymbolRefExpr::VK_PPC_LO:
1601 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1602 case MCSymbolRefExpr::VK_PPC_HI:
1603 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1604 case MCSymbolRefExpr::VK_PPC_HA:
1605 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1606 case MCSymbolRefExpr::VK_PPC_HIGHER:
1607 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1608 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1609 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1610 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1611 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1612 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1613 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);