1 //===- NVPTXInstrInfo.td - NVPTX Instruction defs -------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "NVPTXInstrFormats.td"
17 def NOP : NVPTXInst<(outs), (ins), "", []>;
19 // List of vector specific properties
20 def isVecLD : VecInstTypeEnum<1>;
21 def isVecST : VecInstTypeEnum<2>;
22 def isVecBuild : VecInstTypeEnum<3>;
23 def isVecShuffle : VecInstTypeEnum<4>;
24 def isVecExtract : VecInstTypeEnum<5>;
25 def isVecInsert : VecInstTypeEnum<6>;
26 def isVecDest : VecInstTypeEnum<7>;
27 def isVecOther : VecInstTypeEnum<15>;
29 //===----------------------------------------------------------------------===//
30 // NVPTX Operand Definitions.
31 //===----------------------------------------------------------------------===//
33 def brtarget : Operand<OtherVT>;
35 // CVT conversion modes
36 // These must match the enum in NVPTX.h
37 def CvtNONE : PatLeaf<(i32 0x0)>;
38 def CvtRNI : PatLeaf<(i32 0x1)>;
39 def CvtRZI : PatLeaf<(i32 0x2)>;
40 def CvtRMI : PatLeaf<(i32 0x3)>;
41 def CvtRPI : PatLeaf<(i32 0x4)>;
42 def CvtRN : PatLeaf<(i32 0x5)>;
43 def CvtRZ : PatLeaf<(i32 0x6)>;
44 def CvtRM : PatLeaf<(i32 0x7)>;
45 def CvtRP : PatLeaf<(i32 0x8)>;
47 def CvtNONE_FTZ : PatLeaf<(i32 0x10)>;
48 def CvtRNI_FTZ : PatLeaf<(i32 0x11)>;
49 def CvtRZI_FTZ : PatLeaf<(i32 0x12)>;
50 def CvtRMI_FTZ : PatLeaf<(i32 0x13)>;
51 def CvtRPI_FTZ : PatLeaf<(i32 0x14)>;
52 def CvtRN_FTZ : PatLeaf<(i32 0x15)>;
53 def CvtRZ_FTZ : PatLeaf<(i32 0x16)>;
54 def CvtRM_FTZ : PatLeaf<(i32 0x17)>;
55 def CvtRP_FTZ : PatLeaf<(i32 0x18)>;
57 def CvtSAT : PatLeaf<(i32 0x20)>;
58 def CvtSAT_FTZ : PatLeaf<(i32 0x30)>;
60 def CvtMode : Operand<i32> {
61 let PrintMethod = "printCvtMode";
65 // These must match the enum in NVPTX.h
66 def CmpEQ : PatLeaf<(i32 0)>;
67 def CmpNE : PatLeaf<(i32 1)>;
68 def CmpLT : PatLeaf<(i32 2)>;
69 def CmpLE : PatLeaf<(i32 3)>;
70 def CmpGT : PatLeaf<(i32 4)>;
71 def CmpGE : PatLeaf<(i32 5)>;
72 def CmpLO : PatLeaf<(i32 6)>;
73 def CmpLS : PatLeaf<(i32 7)>;
74 def CmpHI : PatLeaf<(i32 8)>;
75 def CmpHS : PatLeaf<(i32 9)>;
76 def CmpEQU : PatLeaf<(i32 10)>;
77 def CmpNEU : PatLeaf<(i32 11)>;
78 def CmpLTU : PatLeaf<(i32 12)>;
79 def CmpLEU : PatLeaf<(i32 13)>;
80 def CmpGTU : PatLeaf<(i32 14)>;
81 def CmpGEU : PatLeaf<(i32 15)>;
82 def CmpNUM : PatLeaf<(i32 16)>;
83 def CmpNAN : PatLeaf<(i32 17)>;
85 def CmpEQ_FTZ : PatLeaf<(i32 0x100)>;
86 def CmpNE_FTZ : PatLeaf<(i32 0x101)>;
87 def CmpLT_FTZ : PatLeaf<(i32 0x102)>;
88 def CmpLE_FTZ : PatLeaf<(i32 0x103)>;
89 def CmpGT_FTZ : PatLeaf<(i32 0x104)>;
90 def CmpGE_FTZ : PatLeaf<(i32 0x105)>;
91 def CmpLO_FTZ : PatLeaf<(i32 0x106)>;
92 def CmpLS_FTZ : PatLeaf<(i32 0x107)>;
93 def CmpHI_FTZ : PatLeaf<(i32 0x108)>;
94 def CmpHS_FTZ : PatLeaf<(i32 0x109)>;
95 def CmpEQU_FTZ : PatLeaf<(i32 0x10A)>;
96 def CmpNEU_FTZ : PatLeaf<(i32 0x10B)>;
97 def CmpLTU_FTZ : PatLeaf<(i32 0x10C)>;
98 def CmpLEU_FTZ : PatLeaf<(i32 0x10D)>;
99 def CmpGTU_FTZ : PatLeaf<(i32 0x10E)>;
100 def CmpGEU_FTZ : PatLeaf<(i32 0x10F)>;
101 def CmpNUM_FTZ : PatLeaf<(i32 0x110)>;
102 def CmpNAN_FTZ : PatLeaf<(i32 0x111)>;
104 def CmpMode : Operand<i32> {
105 let PrintMethod = "printCmpMode";
108 def F32ConstZero : Operand<f32>, PatLeaf<(f32 fpimm)>, SDNodeXForm<fpimm, [{
109 return CurDAG->getTargetConstantFP(0.0, MVT::f32);
111 def F32ConstOne : Operand<f32>, PatLeaf<(f32 fpimm)>, SDNodeXForm<fpimm, [{
112 return CurDAG->getTargetConstantFP(1.0, MVT::f32);
115 //===----------------------------------------------------------------------===//
116 // NVPTX Instruction Predicate Definitions
117 //===----------------------------------------------------------------------===//
120 def hasAtomRedG32 : Predicate<"Subtarget.hasAtomRedG32()">;
121 def hasAtomRedS32 : Predicate<"Subtarget.hasAtomRedS32()">;
122 def hasAtomRedGen32 : Predicate<"Subtarget.hasAtomRedGen32()">;
123 def useAtomRedG32forGen32 :
124 Predicate<"!Subtarget.hasAtomRedGen32() && Subtarget.hasAtomRedG32()">;
125 def hasBrkPt : Predicate<"Subtarget.hasBrkPt()">;
126 def hasAtomRedG64 : Predicate<"Subtarget.hasAtomRedG64()">;
127 def hasAtomRedS64 : Predicate<"Subtarget.hasAtomRedS64()">;
128 def hasAtomRedGen64 : Predicate<"Subtarget.hasAtomRedGen64()">;
129 def useAtomRedG64forGen64 :
130 Predicate<"!Subtarget.hasAtomRedGen64() && Subtarget.hasAtomRedG64()">;
131 def hasAtomAddF32 : Predicate<"Subtarget.hasAtomAddF32()">;
132 def hasVote : Predicate<"Subtarget.hasVote()">;
133 def hasDouble : Predicate<"Subtarget.hasDouble()">;
134 def reqPTX20 : Predicate<"Subtarget.reqPTX20()">;
135 def hasLDG : Predicate<"Subtarget.hasLDG()">;
136 def hasLDU : Predicate<"Subtarget.hasLDU()">;
137 def hasGenericLdSt : Predicate<"Subtarget.hasGenericLdSt()">;
139 def doF32FTZ : Predicate<"useF32FTZ()">;
140 def doNoF32FTZ : Predicate<"!useF32FTZ()">;
142 def doMulWide : Predicate<"doMulWide">;
144 def allowFMA : Predicate<"allowFMA()">;
145 def noFMA : Predicate<"!allowFMA()">;
147 def do_DIVF32_APPROX : Predicate<"getDivF32Level()==0">;
148 def do_DIVF32_FULL : Predicate<"getDivF32Level()==1">;
150 def do_SQRTF32_APPROX : Predicate<"!usePrecSqrtF32()">;
151 def do_SQRTF32_RN : Predicate<"usePrecSqrtF32()">;
153 def hasHWROT32 : Predicate<"Subtarget.hasHWROT32()">;
154 def noHWROT32 : Predicate<"!Subtarget.hasHWROT32()">;
156 def true : Predicate<"1">;
158 def hasPTX31 : Predicate<"Subtarget.getPTXVersion() >= 31">;
161 //===----------------------------------------------------------------------===//
162 // Some Common Instruction Class Templates
163 //===----------------------------------------------------------------------===//
165 multiclass I3<string OpcStr, SDNode OpNode> {
166 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
167 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
168 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
170 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
171 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
172 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
173 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
174 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
175 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
177 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
178 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
179 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
180 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
181 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
182 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
184 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
185 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
186 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
189 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
190 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
192 !strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
193 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
195 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
196 !strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
197 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
200 multiclass F3<string OpcStr, SDNode OpNode> {
201 def f64rr : NVPTXInst<(outs Float64Regs:$dst),
202 (ins Float64Regs:$a, Float64Regs:$b),
203 !strconcat(OpcStr, ".f64 \t$dst, $a, $b;"),
204 [(set Float64Regs:$dst,
205 (OpNode Float64Regs:$a, Float64Regs:$b))]>,
206 Requires<[allowFMA]>;
207 def f64ri : NVPTXInst<(outs Float64Regs:$dst),
208 (ins Float64Regs:$a, f64imm:$b),
209 !strconcat(OpcStr, ".f64 \t$dst, $a, $b;"),
210 [(set Float64Regs:$dst,
211 (OpNode Float64Regs:$a, fpimm:$b))]>,
212 Requires<[allowFMA]>;
213 def f32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
214 (ins Float32Regs:$a, Float32Regs:$b),
215 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a, $b;"),
216 [(set Float32Regs:$dst,
217 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
218 Requires<[allowFMA, doF32FTZ]>;
219 def f32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
220 (ins Float32Regs:$a, f32imm:$b),
221 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a, $b;"),
222 [(set Float32Regs:$dst,
223 (OpNode Float32Regs:$a, fpimm:$b))]>,
224 Requires<[allowFMA, doF32FTZ]>;
225 def f32rr : NVPTXInst<(outs Float32Regs:$dst),
226 (ins Float32Regs:$a, Float32Regs:$b),
227 !strconcat(OpcStr, ".f32 \t$dst, $a, $b;"),
228 [(set Float32Regs:$dst,
229 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
230 Requires<[allowFMA]>;
231 def f32ri : NVPTXInst<(outs Float32Regs:$dst),
232 (ins Float32Regs:$a, f32imm:$b),
233 !strconcat(OpcStr, ".f32 \t$dst, $a, $b;"),
234 [(set Float32Regs:$dst,
235 (OpNode Float32Regs:$a, fpimm:$b))]>,
236 Requires<[allowFMA]>;
239 multiclass F3_rn<string OpcStr, SDNode OpNode> {
240 def f64rr : NVPTXInst<(outs Float64Regs:$dst),
241 (ins Float64Regs:$a, Float64Regs:$b),
242 !strconcat(OpcStr, ".rn.f64 \t$dst, $a, $b;"),
243 [(set Float64Regs:$dst,
244 (OpNode Float64Regs:$a, Float64Regs:$b))]>,
246 def f64ri : NVPTXInst<(outs Float64Regs:$dst),
247 (ins Float64Regs:$a, f64imm:$b),
248 !strconcat(OpcStr, ".rn.f64 \t$dst, $a, $b;"),
249 [(set Float64Regs:$dst,
250 (OpNode Float64Regs:$a, fpimm:$b))]>,
252 def f32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
253 (ins Float32Regs:$a, Float32Regs:$b),
254 !strconcat(OpcStr, ".rn.ftz.f32 \t$dst, $a, $b;"),
255 [(set Float32Regs:$dst,
256 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
257 Requires<[noFMA, doF32FTZ]>;
258 def f32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
259 (ins Float32Regs:$a, f32imm:$b),
260 !strconcat(OpcStr, ".rn.ftz.f32 \t$dst, $a, $b;"),
261 [(set Float32Regs:$dst,
262 (OpNode Float32Regs:$a, fpimm:$b))]>,
263 Requires<[noFMA, doF32FTZ]>;
264 def f32rr : NVPTXInst<(outs Float32Regs:$dst),
265 (ins Float32Regs:$a, Float32Regs:$b),
266 !strconcat(OpcStr, ".rn.f32 \t$dst, $a, $b;"),
267 [(set Float32Regs:$dst,
268 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
270 def f32ri : NVPTXInst<(outs Float32Regs:$dst),
271 (ins Float32Regs:$a, f32imm:$b),
272 !strconcat(OpcStr, ".rn.f32 \t$dst, $a, $b;"),
273 [(set Float32Regs:$dst,
274 (OpNode Float32Regs:$a, fpimm:$b))]>,
278 multiclass F2<string OpcStr, SDNode OpNode> {
279 def f64 : NVPTXInst<(outs Float64Regs:$dst), (ins Float64Regs:$a),
280 !strconcat(OpcStr, ".f64 \t$dst, $a;"),
281 [(set Float64Regs:$dst, (OpNode Float64Regs:$a))]>;
282 def f32_ftz : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$a),
283 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a;"),
284 [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>,
285 Requires<[doF32FTZ]>;
286 def f32 : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$a),
287 !strconcat(OpcStr, ".f32 \t$dst, $a;"),
288 [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>;
291 //===----------------------------------------------------------------------===//
292 // NVPTX Instructions.
293 //===----------------------------------------------------------------------===//
295 //-----------------------------------
296 // General Type Conversion
297 //-----------------------------------
299 let hasSideEffects = 0 in {
300 // Generate a cvt to the given type from all possible types.
301 // Each instance takes a CvtMode immediate that defines the conversion mode to
302 // use. It can be CvtNONE to omit a conversion mode.
303 multiclass CVT_FROM_ALL<string FromName, RegisterClass RC> {
304 def _s16 : NVPTXInst<(outs RC:$dst),
305 (ins Int16Regs:$src, CvtMode:$mode),
306 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
307 FromName, ".s16\t$dst, $src;"),
309 def _u16 : NVPTXInst<(outs RC:$dst),
310 (ins Int16Regs:$src, CvtMode:$mode),
311 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
312 FromName, ".u16\t$dst, $src;"),
314 def _f16 : NVPTXInst<(outs RC:$dst),
315 (ins Int16Regs:$src, CvtMode:$mode),
316 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
317 FromName, ".f16\t$dst, $src;"),
319 def _s32 : NVPTXInst<(outs RC:$dst),
320 (ins Int32Regs:$src, CvtMode:$mode),
321 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
322 FromName, ".s32\t$dst, $src;"),
324 def _u32 : NVPTXInst<(outs RC:$dst),
325 (ins Int32Regs:$src, CvtMode:$mode),
326 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
327 FromName, ".u32\t$dst, $src;"),
329 def _s64 : NVPTXInst<(outs RC:$dst),
330 (ins Int64Regs:$src, CvtMode:$mode),
331 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
332 FromName, ".s64\t$dst, $src;"),
334 def _u64 : NVPTXInst<(outs RC:$dst),
335 (ins Int64Regs:$src, CvtMode:$mode),
336 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
337 FromName, ".u64\t$dst, $src;"),
339 def _f32 : NVPTXInst<(outs RC:$dst),
340 (ins Float32Regs:$src, CvtMode:$mode),
341 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
342 FromName, ".f32\t$dst, $src;"),
344 def _f64 : NVPTXInst<(outs RC:$dst),
345 (ins Float64Regs:$src, CvtMode:$mode),
346 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
347 FromName, ".f64\t$dst, $src;"),
351 // Generate a cvt to all possible types.
352 defm CVT_s16 : CVT_FROM_ALL<"s16", Int16Regs>;
353 defm CVT_u16 : CVT_FROM_ALL<"u16", Int16Regs>;
354 defm CVT_f16 : CVT_FROM_ALL<"f16", Int16Regs>;
355 defm CVT_s32 : CVT_FROM_ALL<"s32", Int32Regs>;
356 defm CVT_u32 : CVT_FROM_ALL<"u32", Int32Regs>;
357 defm CVT_s64 : CVT_FROM_ALL<"s64", Int64Regs>;
358 defm CVT_u64 : CVT_FROM_ALL<"u64", Int64Regs>;
359 defm CVT_f32 : CVT_FROM_ALL<"f32", Float32Regs>;
360 defm CVT_f64 : CVT_FROM_ALL<"f64", Float64Regs>;
362 // This set of cvt is different from the above. The type of the source
363 // and target are the same.
365 def CVT_INREG_s16_s8 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
366 "cvt.s16.s8 \t$dst, $src;", []>;
367 def CVT_INREG_s32_s8 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
368 "cvt.s32.s8 \t$dst, $src;", []>;
369 def CVT_INREG_s32_s16 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
370 "cvt.s32.s16 \t$dst, $src;", []>;
371 def CVT_INREG_s64_s8 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
372 "cvt.s64.s8 \t$dst, $src;", []>;
373 def CVT_INREG_s64_s16 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
374 "cvt.s64.s16 \t$dst, $src;", []>;
375 def CVT_INREG_s64_s32 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
376 "cvt.s64.s32 \t$dst, $src;", []>;
379 //-----------------------------------
380 // Integer Arithmetic
381 //-----------------------------------
383 multiclass ADD_SUB_i1<SDNode OpNode> {
384 def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
385 "xor.pred \t$dst, $a, $b;",
386 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
387 def _ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
388 "xor.pred \t$dst, $a, $b;",
389 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, (imm):$b))]>;
392 defm ADD_i1 : ADD_SUB_i1<add>;
393 defm SUB_i1 : ADD_SUB_i1<sub>;
396 defm ADD : I3<"add.s", add>;
397 defm SUB : I3<"sub.s", sub>;
399 defm ADDCC : ADD_SUB_INT_32<"add.cc", addc>;
400 defm SUBCC : ADD_SUB_INT_32<"sub.cc", subc>;
402 defm ADDCCC : ADD_SUB_INT_32<"addc.cc", adde>;
403 defm SUBCCC : ADD_SUB_INT_32<"subc.cc", sube>;
405 //mul.wide PTX instruction
406 def SInt32Const : PatLeaf<(imm), [{
407 const APInt &v = N->getAPIntValue();
408 if (v.isSignedIntN(32))
413 def UInt32Const : PatLeaf<(imm), [{
414 const APInt &v = N->getAPIntValue();
420 def SInt16Const : PatLeaf<(imm), [{
421 const APInt &v = N->getAPIntValue();
422 if (v.isSignedIntN(16))
427 def UInt16Const : PatLeaf<(imm), [{
428 const APInt &v = N->getAPIntValue();
434 def Int5Const : PatLeaf<(imm), [{
435 const APInt &v = N->getAPIntValue();
436 // Check if 0 <= v < 32
437 // Only then the result from (x << v) will be i32
438 if (v.sge(0) && v.slt(32))
443 def Int4Const : PatLeaf<(imm), [{
444 const APInt &v = N->getAPIntValue();
445 // Check if 0 <= v < 16
446 // Only then the result from (x << v) will be i16
447 if (v.sge(0) && v.slt(16))
452 def SHL2MUL32 : SDNodeXForm<imm, [{
453 const APInt &v = N->getAPIntValue();
455 return CurDAG->getTargetConstant(temp.shl(v), MVT::i32);
458 def SHL2MUL16 : SDNodeXForm<imm, [{
459 const APInt &v = N->getAPIntValue();
461 return CurDAG->getTargetConstant(temp.shl(v), MVT::i16);
465 : NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
466 "mul.wide.s32 \t$dst, $a, $b;", []>;
468 : NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
469 "mul.wide.s32 \t$dst, $a, $b;", []>;
471 : NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, i64imm:$b),
472 "mul.wide.s32 \t$dst, $a, $b;", []>;
475 : NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
476 "mul.wide.u32 \t$dst, $a, $b;", []>;
478 : NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
479 "mul.wide.u32 \t$dst, $a, $b;", []>;
481 : NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, i64imm:$b),
482 "mul.wide.u32 \t$dst, $a, $b;", []>;
485 : NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
486 "mul.wide.s16 \t$dst, $a, $b;", []>;
488 : NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
489 "mul.wide.s16 \t$dst, $a, $b;", []>;
491 : NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
492 "mul.wide.s16 \t$dst, $a, $b;", []>;
495 : NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
496 "mul.wide.u16 \t$dst, $a, $b;", []>;
498 : NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
499 "mul.wide.u16 \t$dst, $a, $b;", []>;
501 : NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
502 "mul.wide.u16 \t$dst, $a, $b;", []>;
504 def : Pat<(shl (sext Int32Regs:$a), (i32 Int5Const:$b)),
505 (MULWIDES64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
506 Requires<[doMulWide]>;
507 def : Pat<(shl (zext Int32Regs:$a), (i32 Int5Const:$b)),
508 (MULWIDEU64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
509 Requires<[doMulWide]>;
511 def : Pat<(shl (sext Int16Regs:$a), (i16 Int4Const:$b)),
512 (MULWIDES32Imm Int16Regs:$a, (SHL2MUL16 node:$b))>,
513 Requires<[doMulWide]>;
514 def : Pat<(shl (zext Int16Regs:$a), (i16 Int4Const:$b)),
515 (MULWIDEU32Imm Int16Regs:$a, (SHL2MUL16 node:$b))>,
516 Requires<[doMulWide]>;
518 def : Pat<(mul (sext Int32Regs:$a), (sext Int32Regs:$b)),
519 (MULWIDES64 Int32Regs:$a, Int32Regs:$b)>,
520 Requires<[doMulWide]>;
521 def : Pat<(mul (sext Int32Regs:$a), (i64 SInt32Const:$b)),
522 (MULWIDES64Imm64 Int32Regs:$a, (i64 SInt32Const:$b))>,
523 Requires<[doMulWide]>;
525 def : Pat<(mul (zext Int32Regs:$a), (zext Int32Regs:$b)),
526 (MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>,
527 Requires<[doMulWide]>;
528 def : Pat<(mul (zext Int32Regs:$a), (i64 UInt32Const:$b)),
529 (MULWIDEU64Imm64 Int32Regs:$a, (i64 UInt32Const:$b))>,
530 Requires<[doMulWide]>;
532 def : Pat<(mul (sext Int16Regs:$a), (sext Int16Regs:$b)),
533 (MULWIDES32 Int16Regs:$a, Int16Regs:$b)>,
534 Requires<[doMulWide]>;
535 def : Pat<(mul (sext Int16Regs:$a), (i32 SInt16Const:$b)),
536 (MULWIDES32Imm32 Int16Regs:$a, (i32 SInt16Const:$b))>,
537 Requires<[doMulWide]>;
539 def : Pat<(mul (zext Int16Regs:$a), (zext Int16Regs:$b)),
540 (MULWIDEU32 Int16Regs:$a, Int16Regs:$b)>,
541 Requires<[doMulWide]>;
542 def : Pat<(mul (zext Int16Regs:$a), (i32 UInt16Const:$b)),
543 (MULWIDEU32Imm32 Int16Regs:$a, (i32 UInt16Const:$b))>,
544 Requires<[doMulWide]>;
548 : SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>]>;
550 : SDNode<"NVPTXISD::MUL_WIDE_SIGNED", SDTMulWide>;
551 def mul_wide_unsigned
552 : SDNode<"NVPTXISD::MUL_WIDE_UNSIGNED", SDTMulWide>;
554 def : Pat<(i32 (mul_wide_signed Int16Regs:$a, Int16Regs:$b)),
555 (MULWIDES32 Int16Regs:$a, Int16Regs:$b)>,
556 Requires<[doMulWide]>;
557 def : Pat<(i32 (mul_wide_signed Int16Regs:$a, imm:$b)),
558 (MULWIDES32Imm Int16Regs:$a, imm:$b)>,
559 Requires<[doMulWide]>;
560 def : Pat<(i32 (mul_wide_unsigned Int16Regs:$a, Int16Regs:$b)),
561 (MULWIDEU32 Int16Regs:$a, Int16Regs:$b)>,
562 Requires<[doMulWide]>;
563 def : Pat<(i32 (mul_wide_unsigned Int16Regs:$a, imm:$b)),
564 (MULWIDEU32Imm Int16Regs:$a, imm:$b)>,
565 Requires<[doMulWide]>;
568 def : Pat<(i64 (mul_wide_signed Int32Regs:$a, Int32Regs:$b)),
569 (MULWIDES64 Int32Regs:$a, Int32Regs:$b)>,
570 Requires<[doMulWide]>;
571 def : Pat<(i64 (mul_wide_signed Int32Regs:$a, imm:$b)),
572 (MULWIDES64Imm Int32Regs:$a, imm:$b)>,
573 Requires<[doMulWide]>;
574 def : Pat<(i64 (mul_wide_unsigned Int32Regs:$a, Int32Regs:$b)),
575 (MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>,
576 Requires<[doMulWide]>;
577 def : Pat<(i64 (mul_wide_unsigned Int32Regs:$a, imm:$b)),
578 (MULWIDEU64Imm Int32Regs:$a, imm:$b)>,
579 Requires<[doMulWide]>;
581 defm MULT : I3<"mul.lo.s", mul>;
583 defm MULTHS : I3<"mul.hi.s", mulhs>;
584 defm MULTHU : I3<"mul.hi.u", mulhu>;
586 defm SDIV : I3<"div.s", sdiv>;
587 defm UDIV : I3<"div.u", udiv>;
589 defm SREM : I3<"rem.s", srem>;
590 // The ri version will not be selected as DAGCombiner::visitSREM will lower it.
591 defm UREM : I3<"rem.u", urem>;
592 // The ri version will not be selected as DAGCombiner::visitUREM will lower it.
595 : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>,
596 SDTCisInt<2>, SDTCisSameAs<0, 2>,
597 SDTCisSameAs<0, 3>]>;
599 : SDNode<"NVPTXISD::IMAD", SDTIMAD>;
601 def MAD16rrr : NVPTXInst<(outs Int16Regs:$dst),
602 (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
603 "mad.lo.s16 \t$dst, $a, $b, $c;",
604 [(set Int16Regs:$dst,
605 (imad Int16Regs:$a, Int16Regs:$b, Int16Regs:$c))]>;
606 def MAD16rri : NVPTXInst<(outs Int16Regs:$dst),
607 (ins Int16Regs:$a, Int16Regs:$b, i16imm:$c),
608 "mad.lo.s16 \t$dst, $a, $b, $c;",
609 [(set Int16Regs:$dst,
610 (imad Int16Regs:$a, Int16Regs:$b, imm:$c))]>;
611 def MAD16rir : NVPTXInst<(outs Int16Regs:$dst),
612 (ins Int16Regs:$a, i16imm:$b, Int16Regs:$c),
613 "mad.lo.s16 \t$dst, $a, $b, $c;",
614 [(set Int16Regs:$dst,
615 (imad Int16Regs:$a, imm:$b, Int16Regs:$c))]>;
616 def MAD16rii : NVPTXInst<(outs Int16Regs:$dst),
617 (ins Int16Regs:$a, i16imm:$b, i16imm:$c),
618 "mad.lo.s16 \t$dst, $a, $b, $c;",
619 [(set Int16Regs:$dst,
620 (imad Int16Regs:$a, imm:$b, imm:$c))]>;
622 def MAD32rrr : NVPTXInst<(outs Int32Regs:$dst),
623 (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
624 "mad.lo.s32 \t$dst, $a, $b, $c;",
625 [(set Int32Regs:$dst,
626 (imad Int32Regs:$a, Int32Regs:$b, Int32Regs:$c))]>;
627 def MAD32rri : NVPTXInst<(outs Int32Regs:$dst),
628 (ins Int32Regs:$a, Int32Regs:$b, i32imm:$c),
629 "mad.lo.s32 \t$dst, $a, $b, $c;",
630 [(set Int32Regs:$dst,
631 (imad Int32Regs:$a, Int32Regs:$b, imm:$c))]>;
632 def MAD32rir : NVPTXInst<(outs Int32Regs:$dst),
633 (ins Int32Regs:$a, i32imm:$b, Int32Regs:$c),
634 "mad.lo.s32 \t$dst, $a, $b, $c;",
635 [(set Int32Regs:$dst,
636 (imad Int32Regs:$a, imm:$b, Int32Regs:$c))]>;
637 def MAD32rii : NVPTXInst<(outs Int32Regs:$dst),
638 (ins Int32Regs:$a, i32imm:$b, i32imm:$c),
639 "mad.lo.s32 \t$dst, $a, $b, $c;",
640 [(set Int32Regs:$dst,
641 (imad Int32Regs:$a, imm:$b, imm:$c))]>;
643 def MAD64rrr : NVPTXInst<(outs Int64Regs:$dst),
644 (ins Int64Regs:$a, Int64Regs:$b, Int64Regs:$c),
645 "mad.lo.s64 \t$dst, $a, $b, $c;",
646 [(set Int64Regs:$dst,
647 (imad Int64Regs:$a, Int64Regs:$b, Int64Regs:$c))]>;
648 def MAD64rri : NVPTXInst<(outs Int64Regs:$dst),
649 (ins Int64Regs:$a, Int64Regs:$b, i64imm:$c),
650 "mad.lo.s64 \t$dst, $a, $b, $c;",
651 [(set Int64Regs:$dst,
652 (imad Int64Regs:$a, Int64Regs:$b, imm:$c))]>;
653 def MAD64rir : NVPTXInst<(outs Int64Regs:$dst),
654 (ins Int64Regs:$a, i64imm:$b, Int64Regs:$c),
655 "mad.lo.s64 \t$dst, $a, $b, $c;",
656 [(set Int64Regs:$dst,
657 (imad Int64Regs:$a, imm:$b, Int64Regs:$c))]>;
658 def MAD64rii : NVPTXInst<(outs Int64Regs:$dst),
659 (ins Int64Regs:$a, i64imm:$b, i64imm:$c),
660 "mad.lo.s64 \t$dst, $a, $b, $c;",
661 [(set Int64Regs:$dst,
662 (imad Int64Regs:$a, imm:$b, imm:$c))]>;
664 def INEG16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
665 "neg.s16 \t$dst, $src;",
666 [(set Int16Regs:$dst, (ineg Int16Regs:$src))]>;
667 def INEG32 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
668 "neg.s32 \t$dst, $src;",
669 [(set Int32Regs:$dst, (ineg Int32Regs:$src))]>;
670 def INEG64 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
671 "neg.s64 \t$dst, $src;",
672 [(set Int64Regs:$dst, (ineg Int64Regs:$src))]>;
674 //-----------------------------------
675 // Floating Point Arithmetic
676 //-----------------------------------
679 def FloatConst1 : PatLeaf<(fpimm), [{
680 if (&(N->getValueAPF().getSemantics()) != &llvm::APFloat::IEEEsingle)
682 float f = (float)N->getValueAPF().convertToFloat();
685 // Constand (double)1.0
686 def DoubleConst1 : PatLeaf<(fpimm), [{
687 if (&(N->getValueAPF().getSemantics()) != &llvm::APFloat::IEEEdouble)
689 double d = (double)N->getValueAPF().convertToDouble();
693 defm FADD : F3<"add", fadd>;
694 defm FSUB : F3<"sub", fsub>;
695 defm FMUL : F3<"mul", fmul>;
697 defm FADD_rn : F3_rn<"add", fadd>;
698 defm FSUB_rn : F3_rn<"sub", fsub>;
699 defm FMUL_rn : F3_rn<"mul", fmul>;
701 defm FABS : F2<"abs", fabs>;
702 defm FNEG : F2<"neg", fneg>;
703 defm FSQRT : F2<"sqrt.rn", fsqrt>;
708 def FDIV641r : NVPTXInst<(outs Float64Regs:$dst),
709 (ins f64imm:$a, Float64Regs:$b),
710 "rcp.rn.f64 \t$dst, $b;",
711 [(set Float64Regs:$dst,
712 (fdiv DoubleConst1:$a, Float64Regs:$b))]>;
713 def FDIV64rr : NVPTXInst<(outs Float64Regs:$dst),
714 (ins Float64Regs:$a, Float64Regs:$b),
715 "div.rn.f64 \t$dst, $a, $b;",
716 [(set Float64Regs:$dst,
717 (fdiv Float64Regs:$a, Float64Regs:$b))]>;
718 def FDIV64ri : NVPTXInst<(outs Float64Regs:$dst),
719 (ins Float64Regs:$a, f64imm:$b),
720 "div.rn.f64 \t$dst, $a, $b;",
721 [(set Float64Regs:$dst,
722 (fdiv Float64Regs:$a, fpimm:$b))]>;
725 // F32 Approximate reciprocal
727 def FDIV321r_ftz : NVPTXInst<(outs Float32Regs:$dst),
728 (ins f32imm:$a, Float32Regs:$b),
729 "rcp.approx.ftz.f32 \t$dst, $b;",
730 [(set Float32Regs:$dst,
731 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
732 Requires<[do_DIVF32_APPROX, doF32FTZ]>;
733 def FDIV321r : NVPTXInst<(outs Float32Regs:$dst),
734 (ins f32imm:$a, Float32Regs:$b),
735 "rcp.approx.f32 \t$dst, $b;",
736 [(set Float32Regs:$dst,
737 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
738 Requires<[do_DIVF32_APPROX]>;
740 // F32 Approximate division
742 def FDIV32approxrr_ftz : NVPTXInst<(outs Float32Regs:$dst),
743 (ins Float32Regs:$a, Float32Regs:$b),
744 "div.approx.ftz.f32 \t$dst, $a, $b;",
745 [(set Float32Regs:$dst,
746 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
747 Requires<[do_DIVF32_APPROX, doF32FTZ]>;
748 def FDIV32approxri_ftz : NVPTXInst<(outs Float32Regs:$dst),
749 (ins Float32Regs:$a, f32imm:$b),
750 "div.approx.ftz.f32 \t$dst, $a, $b;",
751 [(set Float32Regs:$dst,
752 (fdiv Float32Regs:$a, fpimm:$b))]>,
753 Requires<[do_DIVF32_APPROX, doF32FTZ]>;
754 def FDIV32approxrr : NVPTXInst<(outs Float32Regs:$dst),
755 (ins Float32Regs:$a, Float32Regs:$b),
756 "div.approx.f32 \t$dst, $a, $b;",
757 [(set Float32Regs:$dst,
758 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
759 Requires<[do_DIVF32_APPROX]>;
760 def FDIV32approxri : NVPTXInst<(outs Float32Regs:$dst),
761 (ins Float32Regs:$a, f32imm:$b),
762 "div.approx.f32 \t$dst, $a, $b;",
763 [(set Float32Regs:$dst,
764 (fdiv Float32Regs:$a, fpimm:$b))]>,
765 Requires<[do_DIVF32_APPROX]>;
767 // F32 Semi-accurate reciprocal
769 // rcp.approx gives the same result as div.full(1.0f, a) and is faster.
771 def FDIV321r_approx_ftz : NVPTXInst<(outs Float32Regs:$dst),
772 (ins f32imm:$a, Float32Regs:$b),
773 "rcp.approx.ftz.f32 \t$dst, $b;",
774 [(set Float32Regs:$dst,
775 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
776 Requires<[do_DIVF32_FULL, doF32FTZ]>;
777 def FDIV321r_approx : NVPTXInst<(outs Float32Regs:$dst),
778 (ins f32imm:$a, Float32Regs:$b),
779 "rcp.approx.f32 \t$dst, $b;",
780 [(set Float32Regs:$dst,
781 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
782 Requires<[do_DIVF32_FULL]>;
784 // F32 Semi-accurate division
786 def FDIV32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
787 (ins Float32Regs:$a, Float32Regs:$b),
788 "div.full.ftz.f32 \t$dst, $a, $b;",
789 [(set Float32Regs:$dst,
790 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
791 Requires<[do_DIVF32_FULL, doF32FTZ]>;
792 def FDIV32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
793 (ins Float32Regs:$a, f32imm:$b),
794 "div.full.ftz.f32 \t$dst, $a, $b;",
795 [(set Float32Regs:$dst,
796 (fdiv Float32Regs:$a, fpimm:$b))]>,
797 Requires<[do_DIVF32_FULL, doF32FTZ]>;
798 def FDIV32rr : NVPTXInst<(outs Float32Regs:$dst),
799 (ins Float32Regs:$a, Float32Regs:$b),
800 "div.full.f32 \t$dst, $a, $b;",
801 [(set Float32Regs:$dst,
802 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
803 Requires<[do_DIVF32_FULL]>;
804 def FDIV32ri : NVPTXInst<(outs Float32Regs:$dst),
805 (ins Float32Regs:$a, f32imm:$b),
806 "div.full.f32 \t$dst, $a, $b;",
807 [(set Float32Regs:$dst,
808 (fdiv Float32Regs:$a, fpimm:$b))]>,
809 Requires<[do_DIVF32_FULL]>;
811 // F32 Accurate reciprocal
813 def FDIV321r_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
814 (ins f32imm:$a, Float32Regs:$b),
815 "rcp.rn.ftz.f32 \t$dst, $b;",
816 [(set Float32Regs:$dst,
817 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
818 Requires<[reqPTX20, doF32FTZ]>;
819 def FDIV321r_prec : NVPTXInst<(outs Float32Regs:$dst),
820 (ins f32imm:$a, Float32Regs:$b),
821 "rcp.rn.f32 \t$dst, $b;",
822 [(set Float32Regs:$dst,
823 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
824 Requires<[reqPTX20]>;
826 // F32 Accurate division
828 def FDIV32rr_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
829 (ins Float32Regs:$a, Float32Regs:$b),
830 "div.rn.ftz.f32 \t$dst, $a, $b;",
831 [(set Float32Regs:$dst,
832 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
833 Requires<[doF32FTZ, reqPTX20]>;
834 def FDIV32ri_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
835 (ins Float32Regs:$a, f32imm:$b),
836 "div.rn.ftz.f32 \t$dst, $a, $b;",
837 [(set Float32Regs:$dst,
838 (fdiv Float32Regs:$a, fpimm:$b))]>,
839 Requires<[doF32FTZ, reqPTX20]>;
840 def FDIV32rr_prec : NVPTXInst<(outs Float32Regs:$dst),
841 (ins Float32Regs:$a, Float32Regs:$b),
842 "div.rn.f32 \t$dst, $a, $b;",
843 [(set Float32Regs:$dst,
844 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
845 Requires<[reqPTX20]>;
846 def FDIV32ri_prec : NVPTXInst<(outs Float32Regs:$dst),
847 (ins Float32Regs:$a, f32imm:$b),
848 "div.rn.f32 \t$dst, $a, $b;",
849 [(set Float32Regs:$dst,
850 (fdiv Float32Regs:$a, fpimm:$b))]>,
851 Requires<[reqPTX20]>;
857 def RSQRTF32approx1r : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$b),
858 "rsqrt.approx.f32 \t$dst, $b;", []>;
860 def: Pat<(fdiv FloatConst1, (int_nvvm_sqrt_f Float32Regs:$b)),
861 (RSQRTF32approx1r Float32Regs:$b)>,
862 Requires<[do_DIVF32_FULL, do_SQRTF32_APPROX, doNoF32FTZ]>;
864 multiclass FPCONTRACT32<string OpcStr, Predicate Pred> {
865 def rrr : NVPTXInst<(outs Float32Regs:$dst),
866 (ins Float32Regs:$a, Float32Regs:$b, Float32Regs:$c),
867 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
868 [(set Float32Regs:$dst,
869 (fma Float32Regs:$a, Float32Regs:$b, Float32Regs:$c))]>,
871 def rri : NVPTXInst<(outs Float32Regs:$dst),
872 (ins Float32Regs:$a, Float32Regs:$b, f32imm:$c),
873 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
874 [(set Float32Regs:$dst,
875 (fma Float32Regs:$a, Float32Regs:$b, fpimm:$c))]>,
877 def rir : NVPTXInst<(outs Float32Regs:$dst),
878 (ins Float32Regs:$a, f32imm:$b, Float32Regs:$c),
879 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
880 [(set Float32Regs:$dst,
881 (fma Float32Regs:$a, fpimm:$b, Float32Regs:$c))]>,
883 def rii : NVPTXInst<(outs Float32Regs:$dst),
884 (ins Float32Regs:$a, f32imm:$b, f32imm:$c),
885 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
886 [(set Float32Regs:$dst,
887 (fma Float32Regs:$a, fpimm:$b, fpimm:$c))]>,
891 multiclass FPCONTRACT64<string OpcStr, Predicate Pred> {
892 def rrr : NVPTXInst<(outs Float64Regs:$dst),
893 (ins Float64Regs:$a, Float64Regs:$b, Float64Regs:$c),
894 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
895 [(set Float64Regs:$dst,
896 (fma Float64Regs:$a, Float64Regs:$b, Float64Regs:$c))]>,
898 def rri : NVPTXInst<(outs Float64Regs:$dst),
899 (ins Float64Regs:$a, Float64Regs:$b, f64imm:$c),
900 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
901 [(set Float64Regs:$dst,
902 (fma Float64Regs:$a, Float64Regs:$b, fpimm:$c))]>,
904 def rir : NVPTXInst<(outs Float64Regs:$dst),
905 (ins Float64Regs:$a, f64imm:$b, Float64Regs:$c),
906 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
907 [(set Float64Regs:$dst,
908 (fma Float64Regs:$a, fpimm:$b, Float64Regs:$c))]>,
910 def rii : NVPTXInst<(outs Float64Regs:$dst),
911 (ins Float64Regs:$a, f64imm:$b, f64imm:$c),
912 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
913 [(set Float64Regs:$dst,
914 (fma Float64Regs:$a, fpimm:$b, fpimm:$c))]>,
918 defm FMA32_ftz : FPCONTRACT32<"fma.rn.ftz.f32", doF32FTZ>;
919 defm FMA32 : FPCONTRACT32<"fma.rn.f32", true>;
920 defm FMA64 : FPCONTRACT64<"fma.rn.f64", true>;
922 def SINF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
923 "sin.approx.f32 \t$dst, $src;",
924 [(set Float32Regs:$dst, (fsin Float32Regs:$src))]>;
925 def COSF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
926 "cos.approx.f32 \t$dst, $src;",
927 [(set Float32Regs:$dst, (fcos Float32Regs:$src))]>;
929 // Lower (frem x, y) into (sub x, (mul (floor (div x, y)) y))
930 // e.g. "poor man's fmod()"
933 def : Pat<(frem Float32Regs:$x, Float32Regs:$y),
934 (FSUBf32rr_ftz Float32Regs:$x, (FMULf32rr_ftz (CVT_f32_f32
935 (FDIV32rr_prec_ftz Float32Regs:$x, Float32Regs:$y), CvtRMI_FTZ),
937 Requires<[doF32FTZ]>;
938 def : Pat<(frem Float32Regs:$x, fpimm:$y),
939 (FSUBf32rr_ftz Float32Regs:$x, (FMULf32ri_ftz (CVT_f32_f32
940 (FDIV32ri_prec_ftz Float32Regs:$x, fpimm:$y), CvtRMI_FTZ),
942 Requires<[doF32FTZ]>;
945 def : Pat<(frem Float32Regs:$x, Float32Regs:$y),
946 (FSUBf32rr Float32Regs:$x, (FMULf32rr (CVT_f32_f32
947 (FDIV32rr_prec Float32Regs:$x, Float32Regs:$y), CvtRMI),
949 def : Pat<(frem Float32Regs:$x, fpimm:$y),
950 (FSUBf32rr Float32Regs:$x, (FMULf32ri (CVT_f32_f32
951 (FDIV32ri_prec Float32Regs:$x, fpimm:$y), CvtRMI),
955 def : Pat<(frem Float64Regs:$x, Float64Regs:$y),
956 (FSUBf64rr Float64Regs:$x, (FMULf64rr (CVT_f64_f64
957 (FDIV64rr Float64Regs:$x, Float64Regs:$y), CvtRMI),
959 def : Pat<(frem Float64Regs:$x, fpimm:$y),
960 (FSUBf64rr Float64Regs:$x, (FMULf64ri (CVT_f64_f64
961 (FDIV64ri Float64Regs:$x, fpimm:$y), CvtRMI),
964 //-----------------------------------
965 // Logical Arithmetic
966 //-----------------------------------
968 multiclass LOG_FORMAT<string OpcStr, SDNode OpNode> {
969 def b1rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
970 !strconcat(OpcStr, ".pred \t$dst, $a, $b;"),
971 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
972 def b1ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
973 !strconcat(OpcStr, ".pred \t$dst, $a, $b;"),
974 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, imm:$b))]>;
975 def b16rr: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
976 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
977 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
979 def b16ri: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
980 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
981 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, imm:$b))]>;
982 def b32rr: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
983 !strconcat(OpcStr, ".b32 \t$dst, $a, $b;"),
984 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
986 def b32ri: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
987 !strconcat(OpcStr, ".b32 \t$dst, $a, $b;"),
988 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
989 def b64rr: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
990 !strconcat(OpcStr, ".b64 \t$dst, $a, $b;"),
991 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
993 def b64ri: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
994 !strconcat(OpcStr, ".b64 \t$dst, $a, $b;"),
995 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
998 defm OR : LOG_FORMAT<"or", or>;
999 defm AND : LOG_FORMAT<"and", and>;
1000 defm XOR : LOG_FORMAT<"xor", xor>;
1002 def NOT1: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$src),
1003 "not.pred \t$dst, $src;",
1004 [(set Int1Regs:$dst, (not Int1Regs:$src))]>;
1005 def NOT16: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
1006 "not.b16 \t$dst, $src;",
1007 [(set Int16Regs:$dst, (not Int16Regs:$src))]>;
1008 def NOT32: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
1009 "not.b32 \t$dst, $src;",
1010 [(set Int32Regs:$dst, (not Int32Regs:$src))]>;
1011 def NOT64: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
1012 "not.b64 \t$dst, $src;",
1013 [(set Int64Regs:$dst, (not Int64Regs:$src))]>;
1015 // For shifts, the second src operand must be 32-bit value
1016 multiclass LSHIFT_FORMAT<string OpcStr, SDNode OpNode> {
1017 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a,
1019 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1020 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1022 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
1023 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1024 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1026 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
1028 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1029 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1031 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
1032 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1033 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1035 def i32ii : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
1036 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1037 [(set Int32Regs:$dst, (OpNode (i32 imm:$a),
1039 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a,
1041 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1042 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1044 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
1045 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1046 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1050 defm SHL : LSHIFT_FORMAT<"shl.b", shl>;
1052 // For shifts, the second src operand must be 32-bit value
1053 // Need to add cvt for the 8-bits.
1054 multiclass RSHIFT_FORMAT<string OpcStr, SDNode OpNode> {
1055 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a,
1057 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1058 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1060 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
1061 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1062 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1064 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
1066 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1067 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1069 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
1070 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1071 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1073 def i32ii : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
1074 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1075 [(set Int32Regs:$dst, (OpNode (i32 imm:$a),
1077 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a,
1079 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1080 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1082 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
1083 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1084 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1088 defm SRA : RSHIFT_FORMAT<"shr.s", sra>;
1089 defm SRL : RSHIFT_FORMAT<"shr.u", srl>;
1092 // Rotate: use ptx shf instruction if available.
1095 // 32 bit r2 = rotl r1, n
1097 // r2 = shf.l r1, r1, n
1098 def ROTL32imm_hw : NVPTXInst<(outs Int32Regs:$dst),
1099 (ins Int32Regs:$src, i32imm:$amt),
1100 "shf.l.wrap.b32 \t$dst, $src, $src, $amt;",
1101 [(set Int32Regs:$dst, (rotl Int32Regs:$src, (i32 imm:$amt)))]>,
1102 Requires<[hasHWROT32]> ;
1104 def ROTL32reg_hw : NVPTXInst<(outs Int32Regs:$dst),
1105 (ins Int32Regs:$src, Int32Regs:$amt),
1106 "shf.l.wrap.b32 \t$dst, $src, $src, $amt;",
1107 [(set Int32Regs:$dst, (rotl Int32Regs:$src, Int32Regs:$amt))]>,
1108 Requires<[hasHWROT32]>;
1110 // 32 bit r2 = rotr r1, n
1112 // r2 = shf.r r1, r1, n
1113 def ROTR32imm_hw : NVPTXInst<(outs Int32Regs:$dst),
1114 (ins Int32Regs:$src, i32imm:$amt),
1115 "shf.r.wrap.b32 \t$dst, $src, $src, $amt;",
1116 [(set Int32Regs:$dst, (rotr Int32Regs:$src, (i32 imm:$amt)))]>,
1117 Requires<[hasHWROT32]>;
1119 def ROTR32reg_hw : NVPTXInst<(outs Int32Regs:$dst),
1120 (ins Int32Regs:$src, Int32Regs:$amt),
1121 "shf.r.wrap.b32 \t$dst, $src, $src, $amt;",
1122 [(set Int32Regs:$dst, (rotr Int32Regs:$src, Int32Regs:$amt))]>,
1123 Requires<[hasHWROT32]>;
1126 // Rotate: if ptx shf instruction is not available, then use shift+add
1129 def ROT32imm_sw : NVPTXInst<(outs Int32Regs:$dst),
1130 (ins Int32Regs:$src, i32imm:$amt1, i32imm:$amt2),
1131 !strconcat("{{\n\t",
1132 !strconcat(".reg .b32 %lhs;\n\t",
1133 !strconcat(".reg .b32 %rhs;\n\t",
1134 !strconcat("shl.b32 \t%lhs, $src, $amt1;\n\t",
1135 !strconcat("shr.b32 \t%rhs, $src, $amt2;\n\t",
1136 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1137 !strconcat("}}", ""))))))),
1140 def SUB_FRM_32 : SDNodeXForm<imm, [{
1141 return CurDAG->getTargetConstant(32-N->getZExtValue(), MVT::i32);
1144 def : Pat<(rotl Int32Regs:$src, (i32 imm:$amt)),
1145 (ROT32imm_sw Int32Regs:$src, imm:$amt, (SUB_FRM_32 node:$amt))>,
1146 Requires<[noHWROT32]>;
1147 def : Pat<(rotr Int32Regs:$src, (i32 imm:$amt)),
1148 (ROT32imm_sw Int32Regs:$src, (SUB_FRM_32 node:$amt), imm:$amt)>,
1149 Requires<[noHWROT32]>;
1151 def ROTL32reg_sw : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src,
1153 !strconcat("{{\n\t",
1154 !strconcat(".reg .b32 %lhs;\n\t",
1155 !strconcat(".reg .b32 %rhs;\n\t",
1156 !strconcat(".reg .b32 %amt2;\n\t",
1157 !strconcat("shl.b32 \t%lhs, $src, $amt;\n\t",
1158 !strconcat("sub.s32 \t%amt2, 32, $amt;\n\t",
1159 !strconcat("shr.b32 \t%rhs, $src, %amt2;\n\t",
1160 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1161 !strconcat("}}", ""))))))))),
1162 [(set Int32Regs:$dst, (rotl Int32Regs:$src, Int32Regs:$amt))]>,
1163 Requires<[noHWROT32]>;
1165 def ROTR32reg_sw : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src,
1167 !strconcat("{{\n\t",
1168 !strconcat(".reg .b32 %lhs;\n\t",
1169 !strconcat(".reg .b32 %rhs;\n\t",
1170 !strconcat(".reg .b32 %amt2;\n\t",
1171 !strconcat("shr.b32 \t%lhs, $src, $amt;\n\t",
1172 !strconcat("sub.s32 \t%amt2, 32, $amt;\n\t",
1173 !strconcat("shl.b32 \t%rhs, $src, %amt2;\n\t",
1174 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1175 !strconcat("}}", ""))))))))),
1176 [(set Int32Regs:$dst, (rotr Int32Regs:$src, Int32Regs:$amt))]>,
1177 Requires<[noHWROT32]>;
1180 def ROT64imm_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1181 i32imm:$amt1, i32imm:$amt2),
1182 !strconcat("{{\n\t",
1183 !strconcat(".reg .b64 %lhs;\n\t",
1184 !strconcat(".reg .b64 %rhs;\n\t",
1185 !strconcat("shl.b64 \t%lhs, $src, $amt1;\n\t",
1186 !strconcat("shr.b64 \t%rhs, $src, $amt2;\n\t",
1187 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1188 !strconcat("}}", ""))))))),
1191 def SUB_FRM_64 : SDNodeXForm<imm, [{
1192 return CurDAG->getTargetConstant(64-N->getZExtValue(), MVT::i32);
1195 def : Pat<(rotl Int64Regs:$src, (i32 imm:$amt)),
1196 (ROT64imm_sw Int64Regs:$src, imm:$amt, (SUB_FRM_64 node:$amt))>;
1197 def : Pat<(rotr Int64Regs:$src, (i32 imm:$amt)),
1198 (ROT64imm_sw Int64Regs:$src, (SUB_FRM_64 node:$amt), imm:$amt)>;
1200 def ROTL64reg_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1202 !strconcat("{{\n\t",
1203 !strconcat(".reg .b64 %lhs;\n\t",
1204 !strconcat(".reg .b64 %rhs;\n\t",
1205 !strconcat(".reg .u32 %amt2;\n\t",
1206 !strconcat("shl.b64 \t%lhs, $src, $amt;\n\t",
1207 !strconcat("sub.u32 \t%amt2, 64, $amt;\n\t",
1208 !strconcat("shr.b64 \t%rhs, $src, %amt2;\n\t",
1209 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1210 !strconcat("}}", ""))))))))),
1211 [(set Int64Regs:$dst, (rotl Int64Regs:$src, Int32Regs:$amt))]>;
1213 def ROTR64reg_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1215 !strconcat("{{\n\t",
1216 !strconcat(".reg .b64 %lhs;\n\t",
1217 !strconcat(".reg .b64 %rhs;\n\t",
1218 !strconcat(".reg .u32 %amt2;\n\t",
1219 !strconcat("shr.b64 \t%lhs, $src, $amt;\n\t",
1220 !strconcat("sub.u32 \t%amt2, 64, $amt;\n\t",
1221 !strconcat("shl.b64 \t%rhs, $src, %amt2;\n\t",
1222 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1223 !strconcat("}}", ""))))))))),
1224 [(set Int64Regs:$dst, (rotr Int64Regs:$src, Int32Regs:$amt))]>;
1226 // BFE - bit-field extract
1228 multiclass BFE<string TyStr, RegisterClass RC> {
1229 // BFE supports both 32-bit and 64-bit values, but the start and length
1230 // operands are always 32-bit
1232 : NVPTXInst<(outs RC:$d),
1233 (ins RC:$a, Int32Regs:$b, Int32Regs:$c),
1234 !strconcat("bfe.", TyStr, " \t$d, $a, $b, $c;"), []>;
1236 : NVPTXInst<(outs RC:$d),
1237 (ins RC:$a, Int32Regs:$b, i32imm:$c),
1238 !strconcat("bfe.", TyStr, " \t$d, $a, $b, $c;"), []>;
1240 : NVPTXInst<(outs RC:$d),
1241 (ins RC:$a, i32imm:$b, i32imm:$c),
1242 !strconcat("bfe.", TyStr, " \t$d, $a, $b, $c;"), []>;
1245 defm BFE_S32 : BFE<"s32", Int32Regs>;
1246 defm BFE_U32 : BFE<"u32", Int32Regs>;
1247 defm BFE_S64 : BFE<"s64", Int64Regs>;
1248 defm BFE_U64 : BFE<"u64", Int64Regs>;
1250 //-----------------------------------
1251 // General Comparison
1252 //-----------------------------------
1254 // General setp instructions
1255 multiclass SETP<string TypeStr, RegisterClass RC, Operand ImmCls> {
1256 def rr : NVPTXInst<(outs Int1Regs:$dst),
1257 (ins RC:$a, RC:$b, CmpMode:$cmp),
1258 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1260 def ri : NVPTXInst<(outs Int1Regs:$dst),
1261 (ins RC:$a, ImmCls:$b, CmpMode:$cmp),
1262 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1264 def ir : NVPTXInst<(outs Int1Regs:$dst),
1265 (ins ImmCls:$a, RC:$b, CmpMode:$cmp),
1266 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1270 defm SETP_b16 : SETP<"b16", Int16Regs, i16imm>;
1271 defm SETP_s16 : SETP<"s16", Int16Regs, i16imm>;
1272 defm SETP_u16 : SETP<"u16", Int16Regs, i16imm>;
1273 defm SETP_b32 : SETP<"b32", Int32Regs, i32imm>;
1274 defm SETP_s32 : SETP<"s32", Int32Regs, i32imm>;
1275 defm SETP_u32 : SETP<"u32", Int32Regs, i32imm>;
1276 defm SETP_b64 : SETP<"b64", Int64Regs, i64imm>;
1277 defm SETP_s64 : SETP<"s64", Int64Regs, i64imm>;
1278 defm SETP_u64 : SETP<"u64", Int64Regs, i64imm>;
1279 defm SETP_f32 : SETP<"f32", Float32Regs, f32imm>;
1280 defm SETP_f64 : SETP<"f64", Float64Regs, f64imm>;
1282 // General set instructions
1283 multiclass SET<string TypeStr, RegisterClass RC, Operand ImmCls> {
1284 def rr : NVPTXInst<(outs Int32Regs:$dst),
1285 (ins RC:$a, RC:$b, CmpMode:$cmp),
1286 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1287 def ri : NVPTXInst<(outs Int32Regs:$dst),
1288 (ins RC:$a, ImmCls:$b, CmpMode:$cmp),
1289 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1290 def ir : NVPTXInst<(outs Int32Regs:$dst),
1291 (ins ImmCls:$a, RC:$b, CmpMode:$cmp),
1292 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1295 defm SET_b16 : SET<"b16", Int16Regs, i16imm>;
1296 defm SET_s16 : SET<"s16", Int16Regs, i16imm>;
1297 defm SET_u16 : SET<"u16", Int16Regs, i16imm>;
1298 defm SET_b32 : SET<"b32", Int32Regs, i32imm>;
1299 defm SET_s32 : SET<"s32", Int32Regs, i32imm>;
1300 defm SET_u32 : SET<"u32", Int32Regs, i32imm>;
1301 defm SET_b64 : SET<"b64", Int64Regs, i64imm>;
1302 defm SET_s64 : SET<"s64", Int64Regs, i64imm>;
1303 defm SET_u64 : SET<"u64", Int64Regs, i64imm>;
1304 defm SET_f32 : SET<"f32", Float32Regs, f32imm>;
1305 defm SET_f64 : SET<"f64", Float64Regs, f64imm>;
1307 //-----------------------------------
1308 // General Selection
1309 //-----------------------------------
1311 // General selp instructions
1312 multiclass SELP<string TypeStr, RegisterClass RC, Operand ImmCls> {
1313 def rr : NVPTXInst<(outs RC:$dst),
1314 (ins RC:$a, RC:$b, Int1Regs:$p),
1315 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1316 def ri : NVPTXInst<(outs RC:$dst),
1317 (ins RC:$a, ImmCls:$b, Int1Regs:$p),
1318 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1319 def ir : NVPTXInst<(outs RC:$dst),
1320 (ins ImmCls:$a, RC:$b, Int1Regs:$p),
1321 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1322 def ii : NVPTXInst<(outs RC:$dst),
1323 (ins ImmCls:$a, ImmCls:$b, Int1Regs:$p),
1324 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1327 multiclass SELP_PATTERN<string TypeStr, RegisterClass RC, Operand ImmCls,
1329 def rr : NVPTXInst<(outs RC:$dst),
1330 (ins RC:$a, RC:$b, Int1Regs:$p),
1331 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1332 [(set RC:$dst, (select Int1Regs:$p, RC:$a, RC:$b))]>;
1333 def ri : NVPTXInst<(outs RC:$dst),
1334 (ins RC:$a, ImmCls:$b, Int1Regs:$p),
1335 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1336 [(set RC:$dst, (select Int1Regs:$p, RC:$a, ImmNode:$b))]>;
1337 def ir : NVPTXInst<(outs RC:$dst),
1338 (ins ImmCls:$a, RC:$b, Int1Regs:$p),
1339 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1340 [(set RC:$dst, (select Int1Regs:$p, ImmNode:$a, RC:$b))]>;
1341 def ii : NVPTXInst<(outs RC:$dst),
1342 (ins ImmCls:$a, ImmCls:$b, Int1Regs:$p),
1343 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1344 [(set RC:$dst, (select Int1Regs:$p, ImmNode:$a, ImmNode:$b))]>;
1347 defm SELP_b16 : SELP_PATTERN<"b16", Int16Regs, i16imm, imm>;
1348 defm SELP_s16 : SELP<"s16", Int16Regs, i16imm>;
1349 defm SELP_u16 : SELP<"u16", Int16Regs, i16imm>;
1350 defm SELP_b32 : SELP_PATTERN<"b32", Int32Regs, i32imm, imm>;
1351 defm SELP_s32 : SELP<"s32", Int32Regs, i32imm>;
1352 defm SELP_u32 : SELP<"u32", Int32Regs, i32imm>;
1353 defm SELP_b64 : SELP_PATTERN<"b64", Int64Regs, i64imm, imm>;
1354 defm SELP_s64 : SELP<"s64", Int64Regs, i64imm>;
1355 defm SELP_u64 : SELP<"u64", Int64Regs, i64imm>;
1356 defm SELP_f32 : SELP_PATTERN<"f32", Float32Regs, f32imm, fpimm>;
1357 defm SELP_f64 : SELP_PATTERN<"f64", Float64Regs, f64imm, fpimm>;
1359 // Special select for predicate operands
1360 def : Pat<(i1 (select Int1Regs:$p, Int1Regs:$a, Int1Regs:$b)),
1361 (ORb1rr (ANDb1rr Int1Regs:$p, Int1Regs:$a),
1362 (ANDb1rr (NOT1 Int1Regs:$p), Int1Regs:$b))>;
1365 // Funnnel shift in clamp mode
1367 // - SDNodes are created so they can be used in the DAG code,
1368 // e.g. NVPTXISelLowering (LowerShiftLeftParts and LowerShiftRightParts)
1370 def SDTIntShiftDOp: SDTypeProfile<1, 3,
1371 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
1372 SDTCisInt<0>, SDTCisInt<3>]>;
1373 def FUN_SHFL_CLAMP : SDNode<"NVPTXISD::FUN_SHFL_CLAMP", SDTIntShiftDOp, []>;
1374 def FUN_SHFR_CLAMP : SDNode<"NVPTXISD::FUN_SHFR_CLAMP", SDTIntShiftDOp, []>;
1376 def FUNSHFLCLAMP : NVPTXInst<(outs Int32Regs:$dst),
1377 (ins Int32Regs:$lo, Int32Regs:$hi, Int32Regs:$amt),
1378 "shf.l.clamp.b32 \t$dst, $lo, $hi, $amt;",
1379 [(set Int32Regs:$dst,
1380 (FUN_SHFL_CLAMP Int32Regs:$lo,
1381 Int32Regs:$hi, Int32Regs:$amt))]>;
1383 def FUNSHFRCLAMP : NVPTXInst<(outs Int32Regs:$dst),
1384 (ins Int32Regs:$lo, Int32Regs:$hi, Int32Regs:$amt),
1385 "shf.r.clamp.b32 \t$dst, $lo, $hi, $amt;",
1386 [(set Int32Regs:$dst,
1387 (FUN_SHFR_CLAMP Int32Regs:$lo,
1388 Int32Regs:$hi, Int32Regs:$amt))]>;
1390 //-----------------------------------
1391 // Data Movement (Load / Store, Move)
1392 //-----------------------------------
1394 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex],
1396 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri64", [frameindex],
1399 def MEMri : Operand<i32> {
1400 let PrintMethod = "printMemOperand";
1401 let MIOperandInfo = (ops Int32Regs, i32imm);
1403 def MEMri64 : Operand<i64> {
1404 let PrintMethod = "printMemOperand";
1405 let MIOperandInfo = (ops Int64Regs, i64imm);
1408 def imem : Operand<iPTR> {
1409 let PrintMethod = "printOperand";
1412 def imemAny : Operand<iPTRAny> {
1413 let PrintMethod = "printOperand";
1416 def LdStCode : Operand<i32> {
1417 let PrintMethod = "printLdStCode";
1420 def SDTWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
1421 def Wrapper : SDNode<"NVPTXISD::Wrapper", SDTWrapper>;
1423 def MOV_ADDR : NVPTXInst<(outs Int32Regs:$dst), (ins imem:$a),
1424 "mov.u32 \t$dst, $a;",
1425 [(set Int32Regs:$dst, (Wrapper tglobaladdr:$a))]>;
1427 def MOV_ADDR64 : NVPTXInst<(outs Int64Regs:$dst), (ins imem:$a),
1428 "mov.u64 \t$dst, $a;",
1429 [(set Int64Regs:$dst, (Wrapper tglobaladdr:$a))]>;
1431 // Get pointer to local stack
1433 : NVPTXInst<(outs Int32Regs:$d), (ins i32imm:$num),
1434 "mov.u32 \t$d, __local_depot$num;", []>;
1435 def MOV_DEPOT_ADDR_64
1436 : NVPTXInst<(outs Int64Regs:$d), (ins i32imm:$num),
1437 "mov.u64 \t$d, __local_depot$num;", []>;
1440 // copyPhysreg is hard-coded in NVPTXInstrInfo.cpp
1441 let IsSimpleMove=1 in {
1442 def IMOV1rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$sss),
1443 "mov.pred \t$dst, $sss;", []>;
1444 def IMOV16rr: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$sss),
1445 "mov.u16 \t$dst, $sss;", []>;
1446 def IMOV32rr: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$sss),
1447 "mov.u32 \t$dst, $sss;", []>;
1448 def IMOV64rr: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$sss),
1449 "mov.u64 \t$dst, $sss;", []>;
1451 def FMOV32rr: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
1452 "mov.f32 \t$dst, $src;", []>;
1453 def FMOV64rr: NVPTXInst<(outs Float64Regs:$dst), (ins Float64Regs:$src),
1454 "mov.f64 \t$dst, $src;", []>;
1456 def IMOV1ri: NVPTXInst<(outs Int1Regs:$dst), (ins i1imm:$src),
1457 "mov.pred \t$dst, $src;",
1458 [(set Int1Regs:$dst, imm:$src)]>;
1459 def IMOV16ri: NVPTXInst<(outs Int16Regs:$dst), (ins i16imm:$src),
1460 "mov.u16 \t$dst, $src;",
1461 [(set Int16Regs:$dst, imm:$src)]>;
1462 def IMOV32ri: NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$src),
1463 "mov.u32 \t$dst, $src;",
1464 [(set Int32Regs:$dst, imm:$src)]>;
1465 def IMOV64i: NVPTXInst<(outs Int64Regs:$dst), (ins i64imm:$src),
1466 "mov.u64 \t$dst, $src;",
1467 [(set Int64Regs:$dst, imm:$src)]>;
1469 def FMOV32ri: NVPTXInst<(outs Float32Regs:$dst), (ins f32imm:$src),
1470 "mov.f32 \t$dst, $src;",
1471 [(set Float32Regs:$dst, fpimm:$src)]>;
1472 def FMOV64ri: NVPTXInst<(outs Float64Regs:$dst), (ins f64imm:$src),
1473 "mov.f64 \t$dst, $src;",
1474 [(set Float64Regs:$dst, fpimm:$src)]>;
1476 def : Pat<(i32 (Wrapper texternalsym:$dst)), (IMOV32ri texternalsym:$dst)>;
1478 //---- Copy Frame Index ----
1479 def LEA_ADDRi : NVPTXInst<(outs Int32Regs:$dst), (ins MEMri:$addr),
1480 "add.u32 \t$dst, ${addr:add};",
1481 [(set Int32Regs:$dst, ADDRri:$addr)]>;
1482 def LEA_ADDRi64 : NVPTXInst<(outs Int64Regs:$dst), (ins MEMri64:$addr),
1483 "add.u64 \t$dst, ${addr:add};",
1484 [(set Int64Regs:$dst, ADDRri64:$addr)]>;
1486 //-----------------------------------
1487 // Comparison and Selection
1488 //-----------------------------------
1490 multiclass ISET_FORMAT<PatFrag OpNode, PatLeaf Mode,
1491 Instruction setp_16rr,
1492 Instruction setp_16ri,
1493 Instruction setp_16ir,
1494 Instruction setp_32rr,
1495 Instruction setp_32ri,
1496 Instruction setp_32ir,
1497 Instruction setp_64rr,
1498 Instruction setp_64ri,
1499 Instruction setp_64ir,
1500 Instruction set_16rr,
1501 Instruction set_16ri,
1502 Instruction set_16ir,
1503 Instruction set_32rr,
1504 Instruction set_32ri,
1505 Instruction set_32ir,
1506 Instruction set_64rr,
1507 Instruction set_64ri,
1508 Instruction set_64ir> {
1510 def : Pat<(i1 (OpNode Int16Regs:$a, Int16Regs:$b)),
1511 (setp_16rr Int16Regs:$a, Int16Regs:$b, Mode)>;
1512 def : Pat<(i1 (OpNode Int16Regs:$a, imm:$b)),
1513 (setp_16ri Int16Regs:$a, imm:$b, Mode)>;
1514 def : Pat<(i1 (OpNode imm:$a, Int16Regs:$b)),
1515 (setp_16ir imm:$a, Int16Regs:$b, Mode)>;
1517 def : Pat<(i1 (OpNode Int32Regs:$a, Int32Regs:$b)),
1518 (setp_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
1519 def : Pat<(i1 (OpNode Int32Regs:$a, imm:$b)),
1520 (setp_32ri Int32Regs:$a, imm:$b, Mode)>;
1521 def : Pat<(i1 (OpNode imm:$a, Int32Regs:$b)),
1522 (setp_32ir imm:$a, Int32Regs:$b, Mode)>;
1524 def : Pat<(i1 (OpNode Int64Regs:$a, Int64Regs:$b)),
1525 (setp_64rr Int64Regs:$a, Int64Regs:$b, Mode)>;
1526 def : Pat<(i1 (OpNode Int64Regs:$a, imm:$b)),
1527 (setp_64ri Int64Regs:$a, imm:$b, Mode)>;
1528 def : Pat<(i1 (OpNode imm:$a, Int64Regs:$b)),
1529 (setp_64ir imm:$a, Int64Regs:$b, Mode)>;
1532 def : Pat<(i32 (OpNode Int16Regs:$a, Int16Regs:$b)),
1533 (set_16rr Int16Regs:$a, Int16Regs:$b, Mode)>;
1534 def : Pat<(i32 (OpNode Int16Regs:$a, imm:$b)),
1535 (set_16ri Int16Regs:$a, imm:$b, Mode)>;
1536 def : Pat<(i32 (OpNode imm:$a, Int16Regs:$b)),
1537 (set_16ir imm:$a, Int16Regs:$b, Mode)>;
1539 def : Pat<(i32 (OpNode Int32Regs:$a, Int32Regs:$b)),
1540 (set_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
1541 def : Pat<(i32 (OpNode Int32Regs:$a, imm:$b)),
1542 (set_32ri Int32Regs:$a, imm:$b, Mode)>;
1543 def : Pat<(i32 (OpNode imm:$a, Int32Regs:$b)),
1544 (set_32ir imm:$a, Int32Regs:$b, Mode)>;
1546 def : Pat<(i32 (OpNode Int64Regs:$a, Int64Regs:$b)),
1547 (set_64rr Int64Regs:$a, Int64Regs:$b, Mode)>;
1548 def : Pat<(i32 (OpNode Int64Regs:$a, imm:$b)),
1549 (set_64ri Int64Regs:$a, imm:$b, Mode)>;
1550 def : Pat<(i32 (OpNode imm:$a, Int64Regs:$b)),
1551 (set_64ir imm:$a, Int64Regs:$b, Mode)>;
1554 multiclass ISET_FORMAT_SIGNED<PatFrag OpNode, PatLeaf Mode>
1555 : ISET_FORMAT<OpNode, Mode,
1556 SETP_s16rr, SETP_s16ri, SETP_s16ir,
1557 SETP_s32rr, SETP_s32ri, SETP_s32ir,
1558 SETP_s64rr, SETP_s64ri, SETP_s64ir,
1559 SET_s16rr, SET_s16ri, SET_s16ir,
1560 SET_s32rr, SET_s32ri, SET_s32ir,
1561 SET_s64rr, SET_s64ri, SET_s64ir> {
1562 // TableGen doesn't like empty multiclasses
1563 def : PatLeaf<(i32 0)>;
1566 multiclass ISET_FORMAT_UNSIGNED<PatFrag OpNode, PatLeaf Mode>
1567 : ISET_FORMAT<OpNode, Mode,
1568 SETP_u16rr, SETP_u16ri, SETP_u16ir,
1569 SETP_u32rr, SETP_u32ri, SETP_u32ir,
1570 SETP_u64rr, SETP_u64ri, SETP_u64ir,
1571 SET_u16rr, SET_u16ri, SET_u16ir,
1572 SET_u32rr, SET_u32ri, SET_u32ir,
1573 SET_u64rr, SET_u64ri, SET_u64ir> {
1574 // TableGen doesn't like empty multiclasses
1575 def : PatLeaf<(i32 0)>;
1578 defm : ISET_FORMAT_SIGNED<setgt, CmpGT>;
1579 defm : ISET_FORMAT_UNSIGNED<setugt, CmpGT>;
1580 defm : ISET_FORMAT_SIGNED<setlt, CmpLT>;
1581 defm : ISET_FORMAT_UNSIGNED<setult, CmpLT>;
1582 defm : ISET_FORMAT_SIGNED<setge, CmpGE>;
1583 defm : ISET_FORMAT_UNSIGNED<setuge, CmpGE>;
1584 defm : ISET_FORMAT_SIGNED<setle, CmpLE>;
1585 defm : ISET_FORMAT_UNSIGNED<setule, CmpLE>;
1586 defm : ISET_FORMAT_SIGNED<seteq, CmpEQ>;
1587 defm : ISET_FORMAT_UNSIGNED<setueq, CmpEQ>;
1588 defm : ISET_FORMAT_SIGNED<setne, CmpNE>;
1589 defm : ISET_FORMAT_UNSIGNED<setune, CmpNE>;
1592 def : Pat<(setne Int1Regs:$a, Int1Regs:$b),
1593 (XORb1rr Int1Regs:$a, Int1Regs:$b)>;
1594 def : Pat<(setune Int1Regs:$a, Int1Regs:$b),
1595 (XORb1rr Int1Regs:$a, Int1Regs:$b)>;
1597 def : Pat<(seteq Int1Regs:$a, Int1Regs:$b),
1598 (NOT1 (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1599 def : Pat<(setueq Int1Regs:$a, Int1Regs:$b),
1600 (NOT1 (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1602 // i1 compare -> i32
1603 def : Pat<(i32 (setne Int1Regs:$a, Int1Regs:$b)),
1604 (SELP_u32ii -1, 0, (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1605 def : Pat<(i32 (setne Int1Regs:$a, Int1Regs:$b)),
1606 (SELP_u32ii 0, -1, (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1610 multiclass FSET_FORMAT<PatFrag OpNode, PatLeaf Mode, PatLeaf ModeFTZ> {
1612 def : Pat<(i1 (OpNode Float32Regs:$a, Float32Regs:$b)),
1613 (SETP_f32rr Float32Regs:$a, Float32Regs:$b, ModeFTZ)>,
1614 Requires<[doF32FTZ]>;
1615 def : Pat<(i1 (OpNode Float32Regs:$a, Float32Regs:$b)),
1616 (SETP_f32rr Float32Regs:$a, Float32Regs:$b, Mode)>;
1617 def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
1618 (SETP_f32ri Float32Regs:$a, fpimm:$b, ModeFTZ)>,
1619 Requires<[doF32FTZ]>;
1620 def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
1621 (SETP_f32ri Float32Regs:$a, fpimm:$b, Mode)>;
1622 def : Pat<(i1 (OpNode fpimm:$a, Float32Regs:$b)),
1623 (SETP_f32ir fpimm:$a, Float32Regs:$b, ModeFTZ)>,
1624 Requires<[doF32FTZ]>;
1625 def : Pat<(i1 (OpNode fpimm:$a, Float32Regs:$b)),
1626 (SETP_f32ir fpimm:$a, Float32Regs:$b, Mode)>;
1629 def : Pat<(i1 (OpNode Float64Regs:$a, Float64Regs:$b)),
1630 (SETP_f64rr Float64Regs:$a, Float64Regs:$b, Mode)>;
1631 def : Pat<(i1 (OpNode Float64Regs:$a, fpimm:$b)),
1632 (SETP_f64ri Float64Regs:$a, fpimm:$b, Mode)>;
1633 def : Pat<(i1 (OpNode fpimm:$a, Float64Regs:$b)),
1634 (SETP_f64ir fpimm:$a, Float64Regs:$b, Mode)>;
1637 def : Pat<(i32 (OpNode Float32Regs:$a, Float32Regs:$b)),
1638 (SET_f32rr Float32Regs:$a, Float32Regs:$b, ModeFTZ)>,
1639 Requires<[doF32FTZ]>;
1640 def : Pat<(i32 (OpNode Float32Regs:$a, Float32Regs:$b)),
1641 (SET_f32rr Float32Regs:$a, Float32Regs:$b, Mode)>;
1642 def : Pat<(i32 (OpNode Float32Regs:$a, fpimm:$b)),
1643 (SET_f32ri Float32Regs:$a, fpimm:$b, ModeFTZ)>,
1644 Requires<[doF32FTZ]>;
1645 def : Pat<(i32 (OpNode Float32Regs:$a, fpimm:$b)),
1646 (SET_f32ri Float32Regs:$a, fpimm:$b, Mode)>;
1647 def : Pat<(i32 (OpNode fpimm:$a, Float32Regs:$b)),
1648 (SET_f32ir fpimm:$a, Float32Regs:$b, ModeFTZ)>,
1649 Requires<[doF32FTZ]>;
1650 def : Pat<(i32 (OpNode fpimm:$a, Float32Regs:$b)),
1651 (SET_f32ir fpimm:$a, Float32Regs:$b, Mode)>;
1654 def : Pat<(i32 (OpNode Float64Regs:$a, Float64Regs:$b)),
1655 (SET_f64rr Float64Regs:$a, Float64Regs:$b, Mode)>;
1656 def : Pat<(i32 (OpNode Float64Regs:$a, fpimm:$b)),
1657 (SET_f64ri Float64Regs:$a, fpimm:$b, Mode)>;
1658 def : Pat<(i32 (OpNode fpimm:$a, Float64Regs:$b)),
1659 (SET_f64ir fpimm:$a, Float64Regs:$b, Mode)>;
1662 defm FSetOGT : FSET_FORMAT<setogt, CmpGT, CmpGT_FTZ>;
1663 defm FSetOLT : FSET_FORMAT<setolt, CmpLT, CmpLT_FTZ>;
1664 defm FSetOGE : FSET_FORMAT<setoge, CmpGE, CmpGE_FTZ>;
1665 defm FSetOLE : FSET_FORMAT<setole, CmpLE, CmpLE_FTZ>;
1666 defm FSetOEQ : FSET_FORMAT<setoeq, CmpEQ, CmpEQ_FTZ>;
1667 defm FSetONE : FSET_FORMAT<setone, CmpNE, CmpNE_FTZ>;
1669 defm FSetUGT : FSET_FORMAT<setugt, CmpGTU, CmpGTU_FTZ>;
1670 defm FSetULT : FSET_FORMAT<setult, CmpLTU, CmpLTU_FTZ>;
1671 defm FSetUGE : FSET_FORMAT<setuge, CmpGEU, CmpGEU_FTZ>;
1672 defm FSetULE : FSET_FORMAT<setule, CmpLEU, CmpLEU_FTZ>;
1673 defm FSetUEQ : FSET_FORMAT<setueq, CmpEQU, CmpEQU_FTZ>;
1674 defm FSetUNE : FSET_FORMAT<setune, CmpNEU, CmpNEU_FTZ>;
1676 defm FSetGT : FSET_FORMAT<setgt, CmpGT, CmpGT_FTZ>;
1677 defm FSetLT : FSET_FORMAT<setlt, CmpLT, CmpLT_FTZ>;
1678 defm FSetGE : FSET_FORMAT<setge, CmpGE, CmpGE_FTZ>;
1679 defm FSetLE : FSET_FORMAT<setle, CmpLE, CmpLE_FTZ>;
1680 defm FSetEQ : FSET_FORMAT<seteq, CmpEQ, CmpEQ_FTZ>;
1681 defm FSetNE : FSET_FORMAT<setne, CmpNE, CmpNE_FTZ>;
1683 defm FSetNUM : FSET_FORMAT<seto, CmpNUM, CmpNUM_FTZ>;
1684 defm FSetNAN : FSET_FORMAT<setuo, CmpNAN, CmpNAN_FTZ>;
1686 //def ld_param : SDNode<"NVPTXISD::LOAD_PARAM", SDTLoad,
1687 // [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1689 def SDTDeclareParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
1691 def SDTDeclareScalarParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>,
1692 SDTCisInt<1>, SDTCisInt<2>]>;
1693 def SDTLoadParamProfile : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
1694 def SDTLoadParamV2Profile : SDTypeProfile<2, 2, [SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisInt<3>]>;
1695 def SDTLoadParamV4Profile : SDTypeProfile<4, 2, [SDTCisInt<4>, SDTCisInt<5>]>;
1696 def SDTPrintCallProfile : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
1697 def SDTPrintCallUniProfile : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
1698 def SDTStoreParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>]>;
1699 def SDTStoreParamV2Profile : SDTypeProfile<0, 4, [SDTCisInt<0>, SDTCisInt<1>]>;
1700 def SDTStoreParamV4Profile : SDTypeProfile<0, 6, [SDTCisInt<0>, SDTCisInt<1>]>;
1701 def SDTStoreParam32Profile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>]>;
1702 def SDTCallArgProfile : SDTypeProfile<0, 2, [SDTCisInt<0>]>;
1703 def SDTCallArgMarkProfile : SDTypeProfile<0, 0, []>;
1704 def SDTCallVoidProfile : SDTypeProfile<0, 1, []>;
1705 def SDTCallValProfile : SDTypeProfile<1, 0, []>;
1706 def SDTMoveParamProfile : SDTypeProfile<1, 1, []>;
1707 def SDTStoreRetvalProfile : SDTypeProfile<0, 2, [SDTCisInt<0>]>;
1708 def SDTStoreRetvalV2Profile : SDTypeProfile<0, 3, [SDTCisInt<0>]>;
1709 def SDTStoreRetvalV4Profile : SDTypeProfile<0, 5, [SDTCisInt<0>]>;
1710 def SDTPseudoUseParamProfile : SDTypeProfile<0, 1, []>;
1712 def DeclareParam : SDNode<"NVPTXISD::DeclareParam", SDTDeclareParamProfile,
1713 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1714 def DeclareScalarParam : SDNode<"NVPTXISD::DeclareScalarParam",
1715 SDTDeclareScalarParamProfile,
1716 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1717 def DeclareRetParam : SDNode<"NVPTXISD::DeclareRetParam",
1718 SDTDeclareParamProfile,
1719 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1720 def DeclareRet : SDNode<"NVPTXISD::DeclareRet", SDTDeclareScalarParamProfile,
1721 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1722 def LoadParam : SDNode<"NVPTXISD::LoadParam", SDTLoadParamProfile,
1723 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1724 def LoadParamV2 : SDNode<"NVPTXISD::LoadParamV2", SDTLoadParamV2Profile,
1725 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1726 def LoadParamV4 : SDNode<"NVPTXISD::LoadParamV4", SDTLoadParamV4Profile,
1727 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1728 def PrintCall : SDNode<"NVPTXISD::PrintCall", SDTPrintCallProfile,
1729 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1730 def PrintCallUni : SDNode<"NVPTXISD::PrintCallUni", SDTPrintCallUniProfile,
1731 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1732 def StoreParam : SDNode<"NVPTXISD::StoreParam", SDTStoreParamProfile,
1733 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1734 def StoreParamV2 : SDNode<"NVPTXISD::StoreParamV2", SDTStoreParamV2Profile,
1735 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1736 def StoreParamV4 : SDNode<"NVPTXISD::StoreParamV4", SDTStoreParamV4Profile,
1737 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1738 def StoreParamU32 : SDNode<"NVPTXISD::StoreParamU32", SDTStoreParam32Profile,
1739 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1740 def StoreParamS32 : SDNode<"NVPTXISD::StoreParamS32", SDTStoreParam32Profile,
1741 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1742 def CallArgBegin : SDNode<"NVPTXISD::CallArgBegin", SDTCallArgMarkProfile,
1743 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1744 def CallArg : SDNode<"NVPTXISD::CallArg", SDTCallArgProfile,
1745 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1746 def LastCallArg : SDNode<"NVPTXISD::LastCallArg", SDTCallArgProfile,
1747 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1748 def CallArgEnd : SDNode<"NVPTXISD::CallArgEnd", SDTCallVoidProfile,
1749 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1750 def CallVoid : SDNode<"NVPTXISD::CallVoid", SDTCallVoidProfile,
1751 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1752 def Prototype : SDNode<"NVPTXISD::Prototype", SDTCallVoidProfile,
1753 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1754 def CallVal : SDNode<"NVPTXISD::CallVal", SDTCallValProfile,
1755 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1756 def MoveParam : SDNode<"NVPTXISD::MoveParam", SDTMoveParamProfile,
1758 def StoreRetval : SDNode<"NVPTXISD::StoreRetval", SDTStoreRetvalProfile,
1759 [SDNPHasChain, SDNPSideEffect]>;
1760 def StoreRetvalV2 : SDNode<"NVPTXISD::StoreRetvalV2", SDTStoreRetvalV2Profile,
1761 [SDNPHasChain, SDNPSideEffect]>;
1762 def StoreRetvalV4 : SDNode<"NVPTXISD::StoreRetvalV4", SDTStoreRetvalV4Profile,
1763 [SDNPHasChain, SDNPSideEffect]>;
1764 def PseudoUseParam : SDNode<"NVPTXISD::PseudoUseParam",
1765 SDTPseudoUseParamProfile,
1766 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1767 def RETURNNode : SDNode<"NVPTXISD::RETURN", SDTCallArgMarkProfile,
1768 [SDNPHasChain, SDNPSideEffect]>;
1770 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1771 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1772 !strconcat(!strconcat("ld.param", opstr),
1773 "\t$dst, [retval0+$b];"),
1776 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1777 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1778 !strconcat(!strconcat("mov", opstr),
1779 "\t$dst, retval$b;"),
1780 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
1782 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1783 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1784 !strconcat(!strconcat("ld.param.v2", opstr),
1785 "\t{{$dst, $dst2}}, [retval0+$b];"), []>;
1787 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1788 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1791 !strconcat(!strconcat("ld.param.v4", opstr),
1792 "\t{{$dst, $dst2, $dst3, $dst4}}, [retval0+$b];"), []>;
1794 class StoreParamInst<NVPTXRegClass regclass, string opstr> :
1795 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a, i32imm:$b),
1796 !strconcat(!strconcat("st.param", opstr),
1797 "\t[param$a+$b], $val;"),
1800 class StoreParamV2Inst<NVPTXRegClass regclass, string opstr> :
1801 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2,
1802 i32imm:$a, i32imm:$b),
1803 !strconcat(!strconcat("st.param.v2", opstr),
1804 "\t[param$a+$b], {{$val, $val2}};"),
1807 class StoreParamV4Inst<NVPTXRegClass regclass, string opstr> :
1808 NVPTXInst<(outs), (ins regclass:$val, regclass:$val1, regclass:$val2,
1809 regclass:$val3, i32imm:$a, i32imm:$b),
1810 !strconcat(!strconcat("st.param.v4", opstr),
1811 "\t[param$a+$b], {{$val, $val2, $val3, $val4}};"),
1814 class StoreRetvalInst<NVPTXRegClass regclass, string opstr> :
1815 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a),
1816 !strconcat(!strconcat("st.param", opstr),
1817 "\t[func_retval0+$a], $val;"),
1820 class StoreRetvalV2Inst<NVPTXRegClass regclass, string opstr> :
1821 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2, i32imm:$a),
1822 !strconcat(!strconcat("st.param.v2", opstr),
1823 "\t[func_retval0+$a], {{$val, $val2}};"),
1826 class StoreRetvalV4Inst<NVPTXRegClass regclass, string opstr> :
1828 (ins regclass:$val, regclass:$val2, regclass:$val3,
1829 regclass:$val4, i32imm:$a),
1830 !strconcat(!strconcat("st.param.v4", opstr),
1831 "\t[func_retval0+$a], {{$val, $val2, $val3, $val4}};"),
1834 def PrintCallRetInst1 : NVPTXInst<(outs), (ins),
1836 [(PrintCall (i32 1))]>;
1837 def PrintCallRetInst2 : NVPTXInst<(outs), (ins),
1838 "call (retval0, retval1), ",
1839 [(PrintCall (i32 2))]>;
1840 def PrintCallRetInst3 : NVPTXInst<(outs), (ins),
1841 "call (retval0, retval1, retval2), ",
1842 [(PrintCall (i32 3))]>;
1843 def PrintCallRetInst4 : NVPTXInst<(outs), (ins),
1844 "call (retval0, retval1, retval2, retval3), ",
1845 [(PrintCall (i32 4))]>;
1846 def PrintCallRetInst5 : NVPTXInst<(outs), (ins),
1847 "call (retval0, retval1, retval2, retval3, retval4), ",
1848 [(PrintCall (i32 5))]>;
1849 def PrintCallRetInst6 : NVPTXInst<(outs), (ins),
1850 "call (retval0, retval1, retval2, retval3, retval4, retval5), ",
1851 [(PrintCall (i32 6))]>;
1852 def PrintCallRetInst7 : NVPTXInst<(outs), (ins),
1853 "call (retval0, retval1, retval2, retval3, retval4, retval5, retval6), ",
1854 [(PrintCall (i32 7))]>;
1855 def PrintCallRetInst8 : NVPTXInst<(outs), (ins),
1856 !strconcat("call (retval0, retval1, retval2, retval3, retval4",
1857 ", retval5, retval6, retval7), "),
1858 [(PrintCall (i32 8))]>;
1860 def PrintCallNoRetInst : NVPTXInst<(outs), (ins), "call ",
1861 [(PrintCall (i32 0))]>;
1863 def PrintCallUniRetInst1 : NVPTXInst<(outs), (ins),
1864 "call.uni (retval0), ",
1865 [(PrintCallUni (i32 1))]>;
1866 def PrintCallUniRetInst2 : NVPTXInst<(outs), (ins),
1867 "call.uni (retval0, retval1), ",
1868 [(PrintCallUni (i32 2))]>;
1869 def PrintCallUniRetInst3 : NVPTXInst<(outs), (ins),
1870 "call.uni (retval0, retval1, retval2), ",
1871 [(PrintCallUni (i32 3))]>;
1872 def PrintCallUniRetInst4 : NVPTXInst<(outs), (ins),
1873 "call.uni (retval0, retval1, retval2, retval3), ",
1874 [(PrintCallUni (i32 4))]>;
1875 def PrintCallUniRetInst5 : NVPTXInst<(outs), (ins),
1876 "call.uni (retval0, retval1, retval2, retval3, retval4), ",
1877 [(PrintCallUni (i32 5))]>;
1878 def PrintCallUniRetInst6 : NVPTXInst<(outs), (ins),
1879 "call.uni (retval0, retval1, retval2, retval3, retval4, retval5), ",
1880 [(PrintCallUni (i32 6))]>;
1881 def PrintCallUniRetInst7 : NVPTXInst<(outs), (ins),
1882 "call.uni (retval0, retval1, retval2, retval3, retval4, retval5, retval6), ",
1883 [(PrintCallUni (i32 7))]>;
1884 def PrintCallUniRetInst8 : NVPTXInst<(outs), (ins),
1885 !strconcat("call.uni (retval0, retval1, retval2, retval3, retval4",
1886 ", retval5, retval6, retval7), "),
1887 [(PrintCallUni (i32 8))]>;
1889 def PrintCallUniNoRetInst : NVPTXInst<(outs), (ins), "call.uni ",
1890 [(PrintCallUni (i32 0))]>;
1892 def LoadParamMemI64 : LoadParamMemInst<Int64Regs, ".b64">;
1893 def LoadParamMemI32 : LoadParamMemInst<Int32Regs, ".b32">;
1894 def LoadParamMemI16 : LoadParamMemInst<Int16Regs, ".b16">;
1895 def LoadParamMemI8 : LoadParamMemInst<Int16Regs, ".b8">;
1896 def LoadParamMemV2I64 : LoadParamV2MemInst<Int64Regs, ".b64">;
1897 def LoadParamMemV2I32 : LoadParamV2MemInst<Int32Regs, ".b32">;
1898 def LoadParamMemV2I16 : LoadParamV2MemInst<Int16Regs, ".b16">;
1899 def LoadParamMemV2I8 : LoadParamV2MemInst<Int16Regs, ".b8">;
1900 def LoadParamMemV4I32 : LoadParamV4MemInst<Int32Regs, ".b32">;
1901 def LoadParamMemV4I16 : LoadParamV4MemInst<Int16Regs, ".b16">;
1902 def LoadParamMemV4I8 : LoadParamV4MemInst<Int16Regs, ".b8">;
1903 def LoadParamMemF32 : LoadParamMemInst<Float32Regs, ".f32">;
1904 def LoadParamMemF64 : LoadParamMemInst<Float64Regs, ".f64">;
1905 def LoadParamMemV2F32 : LoadParamV2MemInst<Float32Regs, ".f32">;
1906 def LoadParamMemV2F64 : LoadParamV2MemInst<Float64Regs, ".f64">;
1907 def LoadParamMemV4F32 : LoadParamV4MemInst<Float32Regs, ".f32">;
1909 def StoreParamI64 : StoreParamInst<Int64Regs, ".b64">;
1910 def StoreParamI32 : StoreParamInst<Int32Regs, ".b32">;
1912 def StoreParamI16 : StoreParamInst<Int16Regs, ".b16">;
1913 def StoreParamI8 : StoreParamInst<Int16Regs, ".b8">;
1914 def StoreParamV2I64 : StoreParamV2Inst<Int64Regs, ".b64">;
1915 def StoreParamV2I32 : StoreParamV2Inst<Int32Regs, ".b32">;
1916 def StoreParamV2I16 : StoreParamV2Inst<Int16Regs, ".b16">;
1917 def StoreParamV2I8 : StoreParamV2Inst<Int16Regs, ".b8">;
1919 // FIXME: StoreParamV4Inst crashes llvm-tblgen :(
1920 //def StoreParamV4I32 : StoreParamV4Inst<Int32Regs, ".b32">;
1921 def StoreParamV4I32 : NVPTXInst<(outs), (ins Int32Regs:$val, Int32Regs:$val2,
1922 Int32Regs:$val3, Int32Regs:$val4,
1923 i32imm:$a, i32imm:$b),
1924 "st.param.v4.b32\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1927 def StoreParamV4I16 : NVPTXInst<(outs), (ins Int16Regs:$val, Int16Regs:$val2,
1928 Int16Regs:$val3, Int16Regs:$val4,
1929 i32imm:$a, i32imm:$b),
1930 "st.param.v4.b16\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1933 def StoreParamV4I8 : NVPTXInst<(outs), (ins Int16Regs:$val, Int16Regs:$val2,
1934 Int16Regs:$val3, Int16Regs:$val4,
1935 i32imm:$a, i32imm:$b),
1936 "st.param.v4.b8\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1939 def StoreParamF32 : StoreParamInst<Float32Regs, ".f32">;
1940 def StoreParamF64 : StoreParamInst<Float64Regs, ".f64">;
1941 def StoreParamV2F32 : StoreParamV2Inst<Float32Regs, ".f32">;
1942 def StoreParamV2F64 : StoreParamV2Inst<Float64Regs, ".f64">;
1943 // FIXME: StoreParamV4Inst crashes llvm-tblgen :(
1944 //def StoreParamV4F32 : StoreParamV4Inst<Float32Regs, ".f32">;
1945 def StoreParamV4F32 : NVPTXInst<(outs),
1946 (ins Float32Regs:$val, Float32Regs:$val2,
1947 Float32Regs:$val3, Float32Regs:$val4,
1948 i32imm:$a, i32imm:$b),
1949 "st.param.v4.f32\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1953 def StoreRetvalI64 : StoreRetvalInst<Int64Regs, ".b64">;
1954 def StoreRetvalI32 : StoreRetvalInst<Int32Regs, ".b32">;
1955 def StoreRetvalI16 : StoreRetvalInst<Int16Regs, ".b16">;
1956 def StoreRetvalI8 : StoreRetvalInst<Int16Regs, ".b8">;
1957 def StoreRetvalV2I64 : StoreRetvalV2Inst<Int64Regs, ".b64">;
1958 def StoreRetvalV2I32 : StoreRetvalV2Inst<Int32Regs, ".b32">;
1959 def StoreRetvalV2I16 : StoreRetvalV2Inst<Int16Regs, ".b16">;
1960 def StoreRetvalV2I8 : StoreRetvalV2Inst<Int16Regs, ".b8">;
1961 def StoreRetvalV4I32 : StoreRetvalV4Inst<Int32Regs, ".b32">;
1962 def StoreRetvalV4I16 : StoreRetvalV4Inst<Int16Regs, ".b16">;
1963 def StoreRetvalV4I8 : StoreRetvalV4Inst<Int16Regs, ".b8">;
1965 def StoreRetvalF64 : StoreRetvalInst<Float64Regs, ".f64">;
1966 def StoreRetvalF32 : StoreRetvalInst<Float32Regs, ".f32">;
1967 def StoreRetvalV2F64 : StoreRetvalV2Inst<Float64Regs, ".f64">;
1968 def StoreRetvalV2F32 : StoreRetvalV2Inst<Float32Regs, ".f32">;
1969 def StoreRetvalV4F32 : StoreRetvalV4Inst<Float32Regs, ".f32">;
1971 def CallArgBeginInst : NVPTXInst<(outs), (ins), "(", [(CallArgBegin)]>;
1972 def CallArgEndInst1 : NVPTXInst<(outs), (ins), ");", [(CallArgEnd (i32 1))]>;
1973 def CallArgEndInst0 : NVPTXInst<(outs), (ins), ")", [(CallArgEnd (i32 0))]>;
1974 def RETURNInst : NVPTXInst<(outs), (ins), "ret;", [(RETURNNode)]>;
1976 class CallArgInst<NVPTXRegClass regclass> :
1977 NVPTXInst<(outs), (ins regclass:$a), "$a, ",
1978 [(CallArg (i32 0), regclass:$a)]>;
1980 class LastCallArgInst<NVPTXRegClass regclass> :
1981 NVPTXInst<(outs), (ins regclass:$a), "$a",
1982 [(LastCallArg (i32 0), regclass:$a)]>;
1984 def CallArgI64 : CallArgInst<Int64Regs>;
1985 def CallArgI32 : CallArgInst<Int32Regs>;
1986 def CallArgI16 : CallArgInst<Int16Regs>;
1988 def CallArgF64 : CallArgInst<Float64Regs>;
1989 def CallArgF32 : CallArgInst<Float32Regs>;
1991 def LastCallArgI64 : LastCallArgInst<Int64Regs>;
1992 def LastCallArgI32 : LastCallArgInst<Int32Regs>;
1993 def LastCallArgI16 : LastCallArgInst<Int16Regs>;
1995 def LastCallArgF64 : LastCallArgInst<Float64Regs>;
1996 def LastCallArgF32 : LastCallArgInst<Float32Regs>;
1998 def CallArgI32imm : NVPTXInst<(outs), (ins i32imm:$a), "$a, ",
1999 [(CallArg (i32 0), (i32 imm:$a))]>;
2000 def LastCallArgI32imm : NVPTXInst<(outs), (ins i32imm:$a), "$a",
2001 [(LastCallArg (i32 0), (i32 imm:$a))]>;
2003 def CallArgParam : NVPTXInst<(outs), (ins i32imm:$a), "param$a, ",
2004 [(CallArg (i32 1), (i32 imm:$a))]>;
2005 def LastCallArgParam : NVPTXInst<(outs), (ins i32imm:$a), "param$a",
2006 [(LastCallArg (i32 1), (i32 imm:$a))]>;
2008 def CallVoidInst : NVPTXInst<(outs), (ins imem:$addr),
2010 [(CallVoid (Wrapper tglobaladdr:$addr))]>;
2011 def CallVoidInstReg : NVPTXInst<(outs), (ins Int32Regs:$addr),
2013 [(CallVoid Int32Regs:$addr)]>;
2014 def CallVoidInstReg64 : NVPTXInst<(outs), (ins Int64Regs:$addr),
2016 [(CallVoid Int64Regs:$addr)]>;
2017 def PrototypeInst : NVPTXInst<(outs), (ins i32imm:$val),
2018 ", prototype_$val;",
2019 [(Prototype (i32 imm:$val))]>;
2021 def DeclareRetMemInst : NVPTXInst<(outs),
2022 (ins i32imm:$align, i32imm:$size, i32imm:$num),
2023 ".param .align $align .b8 retval$num[$size];",
2024 [(DeclareRetParam (i32 imm:$align), (i32 imm:$size), (i32 imm:$num))]>;
2025 def DeclareRetScalarInst : NVPTXInst<(outs), (ins i32imm:$size, i32imm:$num),
2026 ".param .b$size retval$num;",
2027 [(DeclareRet (i32 1), (i32 imm:$size), (i32 imm:$num))]>;
2028 def DeclareRetRegInst : NVPTXInst<(outs), (ins i32imm:$size, i32imm:$num),
2029 ".reg .b$size retval$num;",
2030 [(DeclareRet (i32 2), (i32 imm:$size), (i32 imm:$num))]>;
2032 def DeclareParamInst : NVPTXInst<(outs),
2033 (ins i32imm:$align, i32imm:$a, i32imm:$size),
2034 ".param .align $align .b8 param$a[$size];",
2035 [(DeclareParam (i32 imm:$align), (i32 imm:$a), (i32 imm:$size))]>;
2036 def DeclareScalarParamInst : NVPTXInst<(outs), (ins i32imm:$a, i32imm:$size),
2037 ".param .b$size param$a;",
2038 [(DeclareScalarParam (i32 imm:$a), (i32 imm:$size), (i32 0))]>;
2039 def DeclareScalarRegInst : NVPTXInst<(outs), (ins i32imm:$a, i32imm:$size),
2040 ".reg .b$size param$a;",
2041 [(DeclareScalarParam (i32 imm:$a), (i32 imm:$size), (i32 1))]>;
2043 class MoveParamInst<NVPTXRegClass regclass, string asmstr> :
2044 NVPTXInst<(outs regclass:$dst), (ins regclass:$src),
2045 !strconcat(!strconcat("mov", asmstr), "\t$dst, $src;"),
2046 [(set regclass:$dst, (MoveParam regclass:$src))]>;
2048 def MoveParamI64 : MoveParamInst<Int64Regs, ".b64">;
2049 def MoveParamI32 : MoveParamInst<Int32Regs, ".b32">;
2050 def MoveParamI16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
2051 "cvt.u16.u32\t$dst, $src;",
2052 [(set Int16Regs:$dst, (MoveParam Int16Regs:$src))]>;
2053 def MoveParamF64 : MoveParamInst<Float64Regs, ".f64">;
2054 def MoveParamF32 : MoveParamInst<Float32Regs, ".f32">;
2056 class PseudoUseParamInst<NVPTXRegClass regclass> :
2057 NVPTXInst<(outs), (ins regclass:$src),
2058 "// Pseudo use of $src",
2059 [(PseudoUseParam regclass:$src)]>;
2061 def PseudoUseParamI64 : PseudoUseParamInst<Int64Regs>;
2062 def PseudoUseParamI32 : PseudoUseParamInst<Int32Regs>;
2063 def PseudoUseParamI16 : PseudoUseParamInst<Int16Regs>;
2064 def PseudoUseParamF64 : PseudoUseParamInst<Float64Regs>;
2065 def PseudoUseParamF32 : PseudoUseParamInst<Float32Regs>;
2069 // Load / Store Handling
2071 multiclass LD<NVPTXRegClass regclass> {
2072 def _avar : NVPTXInst<(outs regclass:$dst),
2073 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2074 i32imm:$fromWidth, imem:$addr),
2075 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2076 "$fromWidth \t$dst, [$addr];"), []>;
2077 def _areg : NVPTXInst<(outs regclass:$dst),
2078 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2079 i32imm:$fromWidth, Int32Regs:$addr),
2080 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2081 "$fromWidth \t$dst, [$addr];"), []>;
2082 def _areg_64 : NVPTXInst<(outs regclass:$dst),
2083 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2084 i32imm:$fromWidth, Int64Regs:$addr),
2085 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$fromWidth",
2086 " \t$dst, [$addr];"), []>;
2087 def _ari : NVPTXInst<(outs regclass:$dst),
2088 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2089 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2090 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2091 "$fromWidth \t$dst, [$addr+$offset];"), []>;
2092 def _ari_64 : NVPTXInst<(outs regclass:$dst),
2093 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2094 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2095 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$fromWidth",
2096 " \t$dst, [$addr+$offset];"), []>;
2097 def _asi : NVPTXInst<(outs regclass:$dst),
2098 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2099 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2100 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2101 "$fromWidth \t$dst, [$addr+$offset];"), []>;
2104 let mayLoad=1, hasSideEffects=0 in {
2105 defm LD_i8 : LD<Int16Regs>;
2106 defm LD_i16 : LD<Int16Regs>;
2107 defm LD_i32 : LD<Int32Regs>;
2108 defm LD_i64 : LD<Int64Regs>;
2109 defm LD_f32 : LD<Float32Regs>;
2110 defm LD_f64 : LD<Float64Regs>;
2113 multiclass ST<NVPTXRegClass regclass> {
2114 def _avar : NVPTXInst<(outs),
2115 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2116 LdStCode:$Sign, i32imm:$toWidth, imem:$addr),
2117 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2118 " \t[$addr], $src;"), []>;
2119 def _areg : NVPTXInst<(outs),
2120 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2121 LdStCode:$Sign, i32imm:$toWidth, Int32Regs:$addr),
2122 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2123 " \t[$addr], $src;"), []>;
2124 def _areg_64 : NVPTXInst<(outs),
2125 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2126 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr),
2127 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth ",
2128 "\t[$addr], $src;"), []>;
2129 def _ari : NVPTXInst<(outs),
2130 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2131 LdStCode:$Sign, i32imm:$toWidth, Int32Regs:$addr, i32imm:$offset),
2132 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2133 " \t[$addr+$offset], $src;"), []>;
2134 def _ari_64 : NVPTXInst<(outs),
2135 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2136 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr, i32imm:$offset),
2137 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth ",
2138 "\t[$addr+$offset], $src;"), []>;
2139 def _asi : NVPTXInst<(outs),
2140 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2141 LdStCode:$Sign, i32imm:$toWidth, imem:$addr, i32imm:$offset),
2142 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2143 " \t[$addr+$offset], $src;"), []>;
2146 let mayStore=1, hasSideEffects=0 in {
2147 defm ST_i8 : ST<Int16Regs>;
2148 defm ST_i16 : ST<Int16Regs>;
2149 defm ST_i32 : ST<Int32Regs>;
2150 defm ST_i64 : ST<Int64Regs>;
2151 defm ST_f32 : ST<Float32Regs>;
2152 defm ST_f64 : ST<Float64Regs>;
2155 // The following is used only in and after vector elementizations.
2156 // Vector elementization happens at the machine instruction level, so the
2157 // following instruction
2158 // never appears in the DAG.
2159 multiclass LD_VEC<NVPTXRegClass regclass> {
2160 def _v2_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2161 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2162 i32imm:$fromWidth, imem:$addr),
2163 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2164 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2165 def _v2_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2166 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2167 i32imm:$fromWidth, Int32Regs:$addr),
2168 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2169 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2170 def _v2_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2171 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2172 i32imm:$fromWidth, Int64Regs:$addr),
2173 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2174 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2175 def _v2_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2176 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2177 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2178 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2179 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2180 def _v2_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2181 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2182 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2183 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2184 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2185 def _v2_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2186 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2187 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2188 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2189 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2190 def _v4_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2191 regclass:$dst3, regclass:$dst4),
2192 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2193 i32imm:$fromWidth, imem:$addr),
2194 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2195 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2196 def _v4_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2198 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2199 i32imm:$fromWidth, Int32Regs:$addr),
2200 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2201 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2202 def _v4_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2203 regclass:$dst3, regclass:$dst4),
2204 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2205 i32imm:$fromWidth, Int64Regs:$addr),
2206 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2207 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2208 def _v4_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2210 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2211 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2212 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2213 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2215 def _v4_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2216 regclass:$dst3, regclass:$dst4),
2217 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2218 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2219 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2220 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2222 def _v4_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2224 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2225 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2226 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2227 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2230 let mayLoad=1, hasSideEffects=0 in {
2231 defm LDV_i8 : LD_VEC<Int16Regs>;
2232 defm LDV_i16 : LD_VEC<Int16Regs>;
2233 defm LDV_i32 : LD_VEC<Int32Regs>;
2234 defm LDV_i64 : LD_VEC<Int64Regs>;
2235 defm LDV_f32 : LD_VEC<Float32Regs>;
2236 defm LDV_f64 : LD_VEC<Float64Regs>;
2239 multiclass ST_VEC<NVPTXRegClass regclass> {
2240 def _v2_avar : NVPTXInst<(outs),
2241 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2242 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, imem:$addr),
2243 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2244 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2245 def _v2_areg : NVPTXInst<(outs),
2246 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2247 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int32Regs:$addr),
2248 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2249 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2250 def _v2_areg_64 : NVPTXInst<(outs),
2251 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2252 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int64Regs:$addr),
2253 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2254 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2255 def _v2_ari : NVPTXInst<(outs),
2256 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2257 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int32Regs:$addr,
2259 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2260 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2261 def _v2_ari_64 : NVPTXInst<(outs),
2262 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2263 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int64Regs:$addr,
2265 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2266 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2267 def _v2_asi : NVPTXInst<(outs),
2268 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2269 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, imem:$addr,
2271 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2272 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2273 def _v4_avar : NVPTXInst<(outs),
2274 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2275 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2276 i32imm:$fromWidth, imem:$addr),
2277 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2278 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2279 def _v4_areg : NVPTXInst<(outs),
2280 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2281 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2282 i32imm:$fromWidth, Int32Regs:$addr),
2283 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2284 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2285 def _v4_areg_64 : NVPTXInst<(outs),
2286 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2287 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2288 i32imm:$fromWidth, Int64Regs:$addr),
2289 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2290 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2291 def _v4_ari : NVPTXInst<(outs),
2292 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2293 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2294 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2295 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2296 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2298 def _v4_ari_64 : NVPTXInst<(outs),
2299 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2300 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2301 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2302 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2303 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2305 def _v4_asi : NVPTXInst<(outs),
2306 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2307 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2308 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2309 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2310 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2313 let mayStore=1, hasSideEffects=0 in {
2314 defm STV_i8 : ST_VEC<Int16Regs>;
2315 defm STV_i16 : ST_VEC<Int16Regs>;
2316 defm STV_i32 : ST_VEC<Int32Regs>;
2317 defm STV_i64 : ST_VEC<Int64Regs>;
2318 defm STV_f32 : ST_VEC<Float32Regs>;
2319 defm STV_f64 : ST_VEC<Float64Regs>;
2323 //---- Conversion ----
2325 class F_BITCONVERT<string SzStr, NVPTXRegClass regclassIn,
2326 NVPTXRegClass regclassOut> :
2327 NVPTXInst<(outs regclassOut:$d), (ins regclassIn:$a),
2328 !strconcat("mov.b", !strconcat(SzStr, " \t $d, $a;")),
2329 [(set regclassOut:$d, (bitconvert regclassIn:$a))]>;
2331 def BITCONVERT_32_I2F : F_BITCONVERT<"32", Int32Regs, Float32Regs>;
2332 def BITCONVERT_32_F2I : F_BITCONVERT<"32", Float32Regs, Int32Regs>;
2333 def BITCONVERT_64_I2F : F_BITCONVERT<"64", Int64Regs, Float64Regs>;
2334 def BITCONVERT_64_F2I : F_BITCONVERT<"64", Float64Regs, Int64Regs>;
2336 // NOTE: pred->fp are currently sub-optimal due to an issue in TableGen where
2337 // we cannot specify floating-point literals in isel patterns. Therefore, we
2338 // use an integer selp to select either 1 or 0 and then cvt to floating-point.
2341 def : Pat<(f32 (sint_to_fp Int1Regs:$a)),
2342 (CVT_f32_s32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2343 def : Pat<(f32 (sint_to_fp Int16Regs:$a)),
2344 (CVT_f32_s16 Int16Regs:$a, CvtRN)>;
2345 def : Pat<(f32 (sint_to_fp Int32Regs:$a)),
2346 (CVT_f32_s32 Int32Regs:$a, CvtRN)>;
2347 def : Pat<(f32 (sint_to_fp Int64Regs:$a)),
2348 (CVT_f32_s64 Int64Regs:$a, CvtRN)>;
2351 def : Pat<(f32 (uint_to_fp Int1Regs:$a)),
2352 (CVT_f32_u32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2353 def : Pat<(f32 (uint_to_fp Int16Regs:$a)),
2354 (CVT_f32_u16 Int16Regs:$a, CvtRN)>;
2355 def : Pat<(f32 (uint_to_fp Int32Regs:$a)),
2356 (CVT_f32_u32 Int32Regs:$a, CvtRN)>;
2357 def : Pat<(f32 (uint_to_fp Int64Regs:$a)),
2358 (CVT_f32_u64 Int64Regs:$a, CvtRN)>;
2361 def : Pat<(f64 (sint_to_fp Int1Regs:$a)),
2362 (CVT_f64_s32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2363 def : Pat<(f64 (sint_to_fp Int16Regs:$a)),
2364 (CVT_f64_s16 Int16Regs:$a, CvtRN)>;
2365 def : Pat<(f64 (sint_to_fp Int32Regs:$a)),
2366 (CVT_f64_s32 Int32Regs:$a, CvtRN)>;
2367 def : Pat<(f64 (sint_to_fp Int64Regs:$a)),
2368 (CVT_f64_s64 Int64Regs:$a, CvtRN)>;
2371 def : Pat<(f64 (uint_to_fp Int1Regs:$a)),
2372 (CVT_f64_u32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2373 def : Pat<(f64 (uint_to_fp Int16Regs:$a)),
2374 (CVT_f64_u16 Int16Regs:$a, CvtRN)>;
2375 def : Pat<(f64 (uint_to_fp Int32Regs:$a)),
2376 (CVT_f64_u32 Int32Regs:$a, CvtRN)>;
2377 def : Pat<(f64 (uint_to_fp Int64Regs:$a)),
2378 (CVT_f64_u64 Int64Regs:$a, CvtRN)>;
2382 def : Pat<(i1 (fp_to_sint Float32Regs:$a)),
2383 (SETP_b32ri (BITCONVERT_32_F2I Float32Regs:$a), 0, CmpEQ)>;
2384 def : Pat<(i16 (fp_to_sint Float32Regs:$a)),
2385 (CVT_s16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2386 def : Pat<(i16 (fp_to_sint Float32Regs:$a)),
2387 (CVT_s16_f32 Float32Regs:$a, CvtRZI)>;
2388 def : Pat<(i32 (fp_to_sint Float32Regs:$a)),
2389 (CVT_s32_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2390 def : Pat<(i32 (fp_to_sint Float32Regs:$a)),
2391 (CVT_s32_f32 Float32Regs:$a, CvtRZI)>;
2392 def : Pat<(i64 (fp_to_sint Float32Regs:$a)),
2393 (CVT_s64_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2394 def : Pat<(i64 (fp_to_sint Float32Regs:$a)),
2395 (CVT_s64_f32 Float32Regs:$a, CvtRZI)>;
2398 def : Pat<(i1 (fp_to_uint Float32Regs:$a)),
2399 (SETP_b32ri (BITCONVERT_32_F2I Float32Regs:$a), 0, CmpEQ)>;
2400 def : Pat<(i16 (fp_to_uint Float32Regs:$a)),
2401 (CVT_u16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2402 def : Pat<(i16 (fp_to_uint Float32Regs:$a)),
2403 (CVT_u16_f32 Float32Regs:$a, CvtRZI)>;
2404 def : Pat<(i32 (fp_to_uint Float32Regs:$a)),
2405 (CVT_u32_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2406 def : Pat<(i32 (fp_to_uint Float32Regs:$a)),
2407 (CVT_u32_f32 Float32Regs:$a, CvtRZI)>;
2408 def : Pat<(i64 (fp_to_uint Float32Regs:$a)),
2409 (CVT_u64_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2410 def : Pat<(i64 (fp_to_uint Float32Regs:$a)),
2411 (CVT_u64_f32 Float32Regs:$a, CvtRZI)>;
2414 def : Pat<(i1 (fp_to_sint Float64Regs:$a)),
2415 (SETP_b64ri (BITCONVERT_64_F2I Float64Regs:$a), 0, CmpEQ)>;
2416 def : Pat<(i16 (fp_to_sint Float64Regs:$a)),
2417 (CVT_s16_f64 Float64Regs:$a, CvtRZI)>;
2418 def : Pat<(i32 (fp_to_sint Float64Regs:$a)),
2419 (CVT_s32_f64 Float64Regs:$a, CvtRZI)>;
2420 def : Pat<(i64 (fp_to_sint Float64Regs:$a)),
2421 (CVT_s64_f64 Float64Regs:$a, CvtRZI)>;
2424 def : Pat<(i1 (fp_to_uint Float64Regs:$a)),
2425 (SETP_b64ri (BITCONVERT_64_F2I Float64Regs:$a), 0, CmpEQ)>;
2426 def : Pat<(i16 (fp_to_uint Float64Regs:$a)),
2427 (CVT_u16_f64 Float64Regs:$a, CvtRZI)>;
2428 def : Pat<(i32 (fp_to_uint Float64Regs:$a)),
2429 (CVT_u32_f64 Float64Regs:$a, CvtRZI)>;
2430 def : Pat<(i64 (fp_to_uint Float64Regs:$a)),
2431 (CVT_u64_f64 Float64Regs:$a, CvtRZI)>;
2434 def : Pat<(i16 (sext Int1Regs:$a)),
2435 (SELP_s16ii -1, 0, Int1Regs:$a)>;
2436 def : Pat<(i32 (sext Int1Regs:$a)),
2437 (SELP_s32ii -1, 0, Int1Regs:$a)>;
2438 def : Pat<(i64 (sext Int1Regs:$a)),
2439 (SELP_s64ii -1, 0, Int1Regs:$a)>;
2442 def : Pat<(i16 (zext Int1Regs:$a)),
2443 (SELP_u16ii 1, 0, Int1Regs:$a)>;
2444 def : Pat<(i32 (zext Int1Regs:$a)),
2445 (SELP_u32ii 1, 0, Int1Regs:$a)>;
2446 def : Pat<(i64 (zext Int1Regs:$a)),
2447 (SELP_u64ii 1, 0, Int1Regs:$a)>;
2450 def : Pat<(i16 (anyext Int1Regs:$a)),
2451 (SELP_u16ii -1, 0, Int1Regs:$a)>;
2452 def : Pat<(i32 (anyext Int1Regs:$a)),
2453 (SELP_u32ii -1, 0, Int1Regs:$a)>;
2454 def : Pat<(i64 (anyext Int1Regs:$a)),
2455 (SELP_u64ii -1, 0, Int1Regs:$a)>;
2458 def : Pat<(i32 (sext Int16Regs:$a)),
2459 (CVT_s32_s16 Int16Regs:$a, CvtNONE)>;
2460 def : Pat<(i64 (sext Int16Regs:$a)),
2461 (CVT_s64_s16 Int16Regs:$a, CvtNONE)>;
2464 def : Pat<(i32 (zext Int16Regs:$a)),
2465 (CVT_u32_u16 Int16Regs:$a, CvtNONE)>;
2466 def : Pat<(i64 (zext Int16Regs:$a)),
2467 (CVT_u64_u16 Int16Regs:$a, CvtNONE)>;
2470 def : Pat<(i32 (anyext Int16Regs:$a)),
2471 (CVT_u32_u16 Int16Regs:$a, CvtNONE)>;
2472 def : Pat<(i64 (anyext Int16Regs:$a)),
2473 (CVT_u64_u16 Int16Regs:$a, CvtNONE)>;
2476 def : Pat<(i64 (sext Int32Regs:$a)),
2477 (CVT_s64_s32 Int32Regs:$a, CvtNONE)>;
2480 def : Pat<(i64 (zext Int32Regs:$a)),
2481 (CVT_u64_u32 Int32Regs:$a, CvtNONE)>;
2484 def : Pat<(i64 (anyext Int32Regs:$a)),
2485 (CVT_u64_u32 Int32Regs:$a, CvtNONE)>;
2489 def : Pat<(i32 (trunc Int64Regs:$a)),
2490 (CVT_u32_u64 Int64Regs:$a, CvtNONE)>;
2491 def : Pat<(i16 (trunc Int64Regs:$a)),
2492 (CVT_u16_u64 Int64Regs:$a, CvtNONE)>;
2493 def : Pat<(i1 (trunc Int64Regs:$a)),
2494 (SETP_b64ri (ANDb64ri Int64Regs:$a, 1), 1, CmpEQ)>;
2497 def : Pat<(i16 (trunc Int32Regs:$a)),
2498 (CVT_u16_u32 Int32Regs:$a, CvtNONE)>;
2499 def : Pat<(i1 (trunc Int32Regs:$a)),
2500 (SETP_b32ri (ANDb32ri Int32Regs:$a, 1), 1, CmpEQ)>;
2503 def : Pat<(i1 (trunc Int16Regs:$a)),
2504 (SETP_b16ri (ANDb16ri Int16Regs:$a, 1), 1, CmpEQ)>;
2507 def : Pat<(sext_inreg Int16Regs:$a, i8), (CVT_INREG_s16_s8 Int16Regs:$a)>;
2508 def : Pat<(sext_inreg Int32Regs:$a, i8), (CVT_INREG_s32_s8 Int32Regs:$a)>;
2509 def : Pat<(sext_inreg Int32Regs:$a, i16), (CVT_INREG_s32_s16 Int32Regs:$a)>;
2510 def : Pat<(sext_inreg Int64Regs:$a, i8), (CVT_INREG_s64_s8 Int64Regs:$a)>;
2511 def : Pat<(sext_inreg Int64Regs:$a, i16), (CVT_INREG_s64_s16 Int64Regs:$a)>;
2512 def : Pat<(sext_inreg Int64Regs:$a, i32), (CVT_INREG_s64_s32 Int64Regs:$a)>;
2515 // Select instructions with 32-bit predicates
2516 def : Pat<(select Int32Regs:$pred, Int16Regs:$a, Int16Regs:$b),
2517 (SELP_b16rr Int16Regs:$a, Int16Regs:$b,
2518 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2519 def : Pat<(select Int32Regs:$pred, Int32Regs:$a, Int32Regs:$b),
2520 (SELP_b32rr Int32Regs:$a, Int32Regs:$b,
2521 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2522 def : Pat<(select Int32Regs:$pred, Int64Regs:$a, Int64Regs:$b),
2523 (SELP_b64rr Int64Regs:$a, Int64Regs:$b,
2524 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2525 def : Pat<(select Int32Regs:$pred, Float32Regs:$a, Float32Regs:$b),
2526 (SELP_f32rr Float32Regs:$a, Float32Regs:$b,
2527 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2528 def : Pat<(select Int32Regs:$pred, Float64Regs:$a, Float64Regs:$b),
2529 (SELP_f64rr Float64Regs:$a, Float64Regs:$b,
2530 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2533 // pack a set of smaller int registers to a larger int register
2534 def V4I16toI64 : NVPTXInst<(outs Int64Regs:$d),
2535 (ins Int16Regs:$s1, Int16Regs:$s2,
2536 Int16Regs:$s3, Int16Regs:$s4),
2537 "mov.b64\t$d, {{$s1, $s2, $s3, $s4}};",
2539 def V2I16toI32 : NVPTXInst<(outs Int32Regs:$d),
2540 (ins Int16Regs:$s1, Int16Regs:$s2),
2541 "mov.b32\t$d, {{$s1, $s2}};",
2543 def V2I32toI64 : NVPTXInst<(outs Int64Regs:$d),
2544 (ins Int32Regs:$s1, Int32Regs:$s2),
2545 "mov.b64\t$d, {{$s1, $s2}};",
2547 def V2F32toF64 : NVPTXInst<(outs Float64Regs:$d),
2548 (ins Float32Regs:$s1, Float32Regs:$s2),
2549 "mov.b64\t$d, {{$s1, $s2}};",
2552 // unpack a larger int register to a set of smaller int registers
2553 def I64toV4I16 : NVPTXInst<(outs Int16Regs:$d1, Int16Regs:$d2,
2554 Int16Regs:$d3, Int16Regs:$d4),
2556 "mov.b64\t{{$d1, $d2, $d3, $d4}}, $s;",
2558 def I32toV2I16 : NVPTXInst<(outs Int16Regs:$d1, Int16Regs:$d2),
2560 "mov.b32\t{{$d1, $d2}}, $s;",
2562 def I64toV2I32 : NVPTXInst<(outs Int32Regs:$d1, Int32Regs:$d2),
2564 "mov.b64\t{{$d1, $d2}}, $s;",
2566 def F64toV2F32 : NVPTXInst<(outs Float32Regs:$d1, Float32Regs:$d2),
2567 (ins Float64Regs:$s),
2568 "mov.b64\t{{$d1, $d2}}, $s;",
2571 // Count leading zeros
2572 def CLZr32 : NVPTXInst<(outs Int32Regs:$d), (ins Int32Regs:$a),
2575 def CLZr64 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2579 // 32-bit has a direct PTX instruction
2580 def : Pat<(ctlz Int32Regs:$a),
2581 (CLZr32 Int32Regs:$a)>;
2582 def : Pat<(ctlz_zero_undef Int32Regs:$a),
2583 (CLZr32 Int32Regs:$a)>;
2585 // For 64-bit, the result in PTX is actually 32-bit so we zero-extend
2586 // to 64-bit to match the LLVM semantics
2587 def : Pat<(ctlz Int64Regs:$a),
2588 (CVT_u64_u32 (CLZr64 Int64Regs:$a), CvtNONE)>;
2589 def : Pat<(ctlz_zero_undef Int64Regs:$a),
2590 (CVT_u64_u32 (CLZr64 Int64Regs:$a), CvtNONE)>;
2592 // For 16-bit, we zero-extend to 32-bit, then trunc the result back
2593 // to 16-bits (ctlz of a 16-bit value is guaranteed to require less
2594 // than 16 bits to store). We also need to subtract 16 because the
2595 // high-order 16 zeros were counted.
2596 def : Pat<(ctlz Int16Regs:$a),
2597 (SUBi16ri (CVT_u16_u32 (CLZr32
2598 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2600 def : Pat<(ctlz_zero_undef Int16Regs:$a),
2601 (SUBi16ri (CVT_u16_u32 (CLZr32
2602 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2606 def POPCr32 : NVPTXInst<(outs Int32Regs:$d), (ins Int32Regs:$a),
2607 "popc.b32\t$d, $a;",
2609 def POPCr64 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2610 "popc.b64\t$d, $a;",
2613 // 32-bit has a direct PTX instruction
2614 def : Pat<(ctpop Int32Regs:$a),
2615 (POPCr32 Int32Regs:$a)>;
2617 // For 64-bit, the result in PTX is actually 32-bit so we zero-extend
2618 // to 64-bit to match the LLVM semantics
2619 def : Pat<(ctpop Int64Regs:$a),
2620 (CVT_u64_u32 (POPCr64 Int64Regs:$a), CvtNONE)>;
2622 // For 16-bit, we zero-extend to 32-bit, then trunc the result back
2623 // to 16-bits (ctpop of a 16-bit value is guaranteed to require less
2624 // than 16 bits to store)
2625 def : Pat<(ctpop Int16Regs:$a),
2626 (CVT_u16_u32 (POPCr32 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2629 // fround f64 -> f32
2630 def : Pat<(f32 (fround Float64Regs:$a)),
2631 (CVT_f32_f64 Float64Regs:$a, CvtRN_FTZ)>, Requires<[doF32FTZ]>;
2632 def : Pat<(f32 (fround Float64Regs:$a)),
2633 (CVT_f32_f64 Float64Regs:$a, CvtRN)>;
2635 // fextend f32 -> f64
2636 def : Pat<(f64 (fextend Float32Regs:$a)),
2637 (CVT_f64_f32 Float32Regs:$a, CvtNONE_FTZ)>, Requires<[doF32FTZ]>;
2638 def : Pat<(f64 (fextend Float32Regs:$a)),
2639 (CVT_f64_f32 Float32Regs:$a, CvtNONE)>;
2641 def retflag : SDNode<"NVPTXISD::RET_FLAG", SDTNone,
2642 [SDNPHasChain, SDNPOptInGlue]>;
2644 //-----------------------------------
2646 //-----------------------------------
2648 let isTerminator=1 in {
2649 let isReturn=1, isBarrier=1 in
2650 def Return : NVPTXInst<(outs), (ins), "ret;", [(retflag)]>;
2653 def CBranch : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2654 "@$a bra \t$target;",
2655 [(brcond Int1Regs:$a, bb:$target)]>;
2657 def CBranchOther : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2658 "@!$a bra \t$target;",
2661 let isBranch=1, isBarrier=1 in
2662 def GOTO : NVPTXInst<(outs), (ins brtarget:$target),
2663 "bra.uni \t$target;",
2667 def : Pat<(brcond Int32Regs:$a, bb:$target),
2668 (CBranch (SETP_u32ri Int32Regs:$a, 0, CmpNE), bb:$target)>;
2670 // SelectionDAGBuilder::visitSWitchCase() will invert the condition of a
2671 // conditional branch if
2672 // the target block is the next block so that the code can fall through to the
2674 // The invertion is done by 'xor condition, 1', which will be translated to
2675 // (setne condition, -1).
2676 // Since ptx supports '@!pred bra target', we should use it.
2677 def : Pat<(brcond (i1 (setne Int1Regs:$a, -1)), bb:$target),
2678 (CBranchOther Int1Regs:$a, bb:$target)>;
2681 def SDT_NVPTXCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2682 def SDT_NVPTXCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2683 SDTCisVT<1, i32> ]>;
2685 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_NVPTXCallSeqStart,
2686 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
2687 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_NVPTXCallSeqEnd,
2688 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
2691 def SDT_NVPTXCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2692 def call : SDNode<"NVPTXISD::CALL", SDT_NVPTXCall,
2693 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2694 def calltarget : Operand<i32>;
2696 def CALL : NVPTXInst<(outs), (ins calltarget:$dst),
2697 "call \t$dst, (1);", []>;
2700 def : Pat<(call tglobaladdr:$dst),
2701 (CALL tglobaladdr:$dst)>;
2702 def : Pat<(call texternalsym:$dst),
2703 (CALL texternalsym:$dst)>;
2705 // Pseudo instructions.
2706 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
2707 : NVPTXInst<outs, ins, asmstr, pattern>;
2709 // @TODO: We use some tricks here to emit curly braces. Can we clean this up
2710 // a bit without TableGen modifications?
2711 def Callseq_Start : NVPTXInst<(outs), (ins i32imm:$amt),
2712 "// Callseq Start $amt\n\t{{\n\t.reg .b32 temp_param_reg;\n\t// <end>}}",
2713 [(callseq_start timm:$amt)]>;
2714 def Callseq_End : NVPTXInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2715 "\n\t//{{\n\t}}// Callseq End $amt1",
2716 [(callseq_end timm:$amt1, timm:$amt2)]>;
2720 def trapinst : NVPTXInst<(outs), (ins),
2724 // Call prototype wrapper
2725 def SDTCallPrototype : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
2727 : SDNode<"NVPTXISD::CallPrototype", SDTCallPrototype,
2728 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
2729 def ProtoIdent : Operand<i32> {
2730 let PrintMethod = "printProtoIdent";
2733 : NVPTXInst<(outs), (ins ProtoIdent:$ident),
2734 "$ident", [(CallPrototype (i32 texternalsym:$ident))]>;
2738 include "NVPTXIntrinsics.td"
2741 //-----------------------------------
2743 //-----------------------------------
2744 // BSWAP is currently expanded. The following is a more efficient
2745 // - for < sm_20, use vector scalar mov, as tesla support native 16-bit register
2746 // - for sm_20, use pmpt (use vector scalar mov to get the pack and
2747 // unpack). sm_20 supports native 32-bit register, but not native 16-bit