2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelLowering.h"
16 #include "NVPTXTargetMachine.h"
17 #include "NVPTXTargetObjectFile.h"
18 #include "NVPTXUtilities.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/IR/CallSite.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/IntrinsicInst.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/MC/MCSectionELF.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
41 #define DEBUG_TYPE "nvptx-lower"
45 static unsigned int uniqueCallSite = 0;
47 static cl::opt<bool> sched4reg(
49 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
51 static cl::opt<unsigned>
52 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
53 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
54 " 1: do it 2: do it aggressively"),
57 static bool IsPTXVectorType(MVT VT) {
58 switch (VT.SimpleTy) {
77 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
78 /// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
79 /// into their primitive components.
80 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
82 /// LowerCall, and LowerReturn.
83 static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty,
84 SmallVectorImpl<EVT> &ValueVTs,
85 SmallVectorImpl<uint64_t> *Offsets = nullptr,
86 uint64_t StartingOffset = 0) {
87 SmallVector<EVT, 16> TempVTs;
88 SmallVector<uint64_t, 16> TempOffsets;
90 ComputeValueVTs(TLI, Ty, TempVTs, &TempOffsets, StartingOffset);
91 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
93 uint64_t Off = TempOffsets[i];
95 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
96 ValueVTs.push_back(VT.getVectorElementType());
98 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
101 ValueVTs.push_back(VT);
103 Offsets->push_back(Off);
108 // NVPTXTargetLowering Constructor.
109 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
110 const NVPTXSubtarget &STI)
111 : TargetLowering(TM), nvTM(&TM), STI(STI) {
113 // always lower memset, memcpy, and memmove intrinsics to load/store
114 // instructions, rather
115 // then generating calls to memset, mempcy or memmove.
116 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
117 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
118 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
120 setBooleanContents(ZeroOrNegativeOneBooleanContent);
121 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
123 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
124 // condition branches.
125 setJumpIsExpensive(true);
127 // By default, use the Source scheduling
129 setSchedulingPreference(Sched::RegPressure);
131 setSchedulingPreference(Sched::Source);
133 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
134 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
135 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
136 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
137 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
138 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
140 // Operations not directly supported by NVPTX.
141 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
143 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
144 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
145 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
146 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
147 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
148 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
149 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
150 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
151 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
152 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
153 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
154 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
155 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
156 // For others we will expand to a SHL/SRA pair.
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
163 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
164 setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
165 setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
166 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
167 setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
168 setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
170 if (STI.hasROT64()) {
171 setOperationAction(ISD::ROTL, MVT::i64, Legal);
172 setOperationAction(ISD::ROTR, MVT::i64, Legal);
174 setOperationAction(ISD::ROTL, MVT::i64, Expand);
175 setOperationAction(ISD::ROTR, MVT::i64, Expand);
177 if (STI.hasROT32()) {
178 setOperationAction(ISD::ROTL, MVT::i32, Legal);
179 setOperationAction(ISD::ROTR, MVT::i32, Legal);
181 setOperationAction(ISD::ROTL, MVT::i32, Expand);
182 setOperationAction(ISD::ROTR, MVT::i32, Expand);
185 setOperationAction(ISD::ROTL, MVT::i16, Expand);
186 setOperationAction(ISD::ROTR, MVT::i16, Expand);
187 setOperationAction(ISD::ROTL, MVT::i8, Expand);
188 setOperationAction(ISD::ROTR, MVT::i8, Expand);
189 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
190 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
191 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
193 // Indirect branch is not supported.
194 // This also disables Jump Table creation.
195 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
196 setOperationAction(ISD::BRIND, MVT::Other, Expand);
198 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
199 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
201 // We want to legalize constant related memmove and memcopy
203 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
205 // Turn FP extload into load/fextend
206 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
207 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
208 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
209 // Turn FP truncstore into trunc + store.
210 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
211 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
212 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
214 // PTX does not support load / store predicate registers
215 setOperationAction(ISD::LOAD, MVT::i1, Custom);
216 setOperationAction(ISD::STORE, MVT::i1, Custom);
218 for (MVT VT : MVT::integer_valuetypes()) {
219 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
220 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
221 setTruncStoreAction(VT, MVT::i1, Expand);
224 // This is legal in NVPTX
225 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
226 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
228 // TRAP can be lowered to PTX trap
229 setOperationAction(ISD::TRAP, MVT::Other, Legal);
231 setOperationAction(ISD::ADDC, MVT::i64, Expand);
232 setOperationAction(ISD::ADDE, MVT::i64, Expand);
234 // Register custom handling for vector loads/stores
235 for (MVT VT : MVT::vector_valuetypes()) {
236 if (IsPTXVectorType(VT)) {
237 setOperationAction(ISD::LOAD, VT, Custom);
238 setOperationAction(ISD::STORE, VT, Custom);
239 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
243 // Custom handling for i8 intrinsics
244 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
246 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
247 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
248 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
249 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
250 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
251 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
252 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
253 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
254 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
255 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
256 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
257 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
258 setOperationAction(ISD::CTPOP, MVT::i16, Legal);
259 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
260 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
262 // PTX does not directly support SELP of i1, so promote to i32 first
263 setOperationAction(ISD::SELECT, MVT::i1, Custom);
265 // We have some custom DAG combine patterns for these nodes
266 setTargetDAGCombine(ISD::ADD);
267 setTargetDAGCombine(ISD::AND);
268 setTargetDAGCombine(ISD::FADD);
269 setTargetDAGCombine(ISD::MUL);
270 setTargetDAGCombine(ISD::SHL);
272 // Now deduce the information based on the above mentioned
274 computeRegisterProperties(STI.getRegisterInfo());
277 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
282 return "NVPTXISD::CALL";
283 case NVPTXISD::RET_FLAG:
284 return "NVPTXISD::RET_FLAG";
285 case NVPTXISD::Wrapper:
286 return "NVPTXISD::Wrapper";
287 case NVPTXISD::DeclareParam:
288 return "NVPTXISD::DeclareParam";
289 case NVPTXISD::DeclareScalarParam:
290 return "NVPTXISD::DeclareScalarParam";
291 case NVPTXISD::DeclareRet:
292 return "NVPTXISD::DeclareRet";
293 case NVPTXISD::DeclareRetParam:
294 return "NVPTXISD::DeclareRetParam";
295 case NVPTXISD::PrintCall:
296 return "NVPTXISD::PrintCall";
297 case NVPTXISD::LoadParam:
298 return "NVPTXISD::LoadParam";
299 case NVPTXISD::LoadParamV2:
300 return "NVPTXISD::LoadParamV2";
301 case NVPTXISD::LoadParamV4:
302 return "NVPTXISD::LoadParamV4";
303 case NVPTXISD::StoreParam:
304 return "NVPTXISD::StoreParam";
305 case NVPTXISD::StoreParamV2:
306 return "NVPTXISD::StoreParamV2";
307 case NVPTXISD::StoreParamV4:
308 return "NVPTXISD::StoreParamV4";
309 case NVPTXISD::StoreParamS32:
310 return "NVPTXISD::StoreParamS32";
311 case NVPTXISD::StoreParamU32:
312 return "NVPTXISD::StoreParamU32";
313 case NVPTXISD::CallArgBegin:
314 return "NVPTXISD::CallArgBegin";
315 case NVPTXISD::CallArg:
316 return "NVPTXISD::CallArg";
317 case NVPTXISD::LastCallArg:
318 return "NVPTXISD::LastCallArg";
319 case NVPTXISD::CallArgEnd:
320 return "NVPTXISD::CallArgEnd";
321 case NVPTXISD::CallVoid:
322 return "NVPTXISD::CallVoid";
323 case NVPTXISD::CallVal:
324 return "NVPTXISD::CallVal";
325 case NVPTXISD::CallSymbol:
326 return "NVPTXISD::CallSymbol";
327 case NVPTXISD::Prototype:
328 return "NVPTXISD::Prototype";
329 case NVPTXISD::MoveParam:
330 return "NVPTXISD::MoveParam";
331 case NVPTXISD::StoreRetval:
332 return "NVPTXISD::StoreRetval";
333 case NVPTXISD::StoreRetvalV2:
334 return "NVPTXISD::StoreRetvalV2";
335 case NVPTXISD::StoreRetvalV4:
336 return "NVPTXISD::StoreRetvalV4";
337 case NVPTXISD::PseudoUseParam:
338 return "NVPTXISD::PseudoUseParam";
339 case NVPTXISD::RETURN:
340 return "NVPTXISD::RETURN";
341 case NVPTXISD::CallSeqBegin:
342 return "NVPTXISD::CallSeqBegin";
343 case NVPTXISD::CallSeqEnd:
344 return "NVPTXISD::CallSeqEnd";
345 case NVPTXISD::CallPrototype:
346 return "NVPTXISD::CallPrototype";
347 case NVPTXISD::LoadV2:
348 return "NVPTXISD::LoadV2";
349 case NVPTXISD::LoadV4:
350 return "NVPTXISD::LoadV4";
351 case NVPTXISD::LDGV2:
352 return "NVPTXISD::LDGV2";
353 case NVPTXISD::LDGV4:
354 return "NVPTXISD::LDGV4";
355 case NVPTXISD::LDUV2:
356 return "NVPTXISD::LDUV2";
357 case NVPTXISD::LDUV4:
358 return "NVPTXISD::LDUV4";
359 case NVPTXISD::StoreV2:
360 return "NVPTXISD::StoreV2";
361 case NVPTXISD::StoreV4:
362 return "NVPTXISD::StoreV4";
363 case NVPTXISD::FUN_SHFL_CLAMP:
364 return "NVPTXISD::FUN_SHFL_CLAMP";
365 case NVPTXISD::FUN_SHFR_CLAMP:
366 return "NVPTXISD::FUN_SHFR_CLAMP";
368 return "NVPTXISD::IMAD";
369 case NVPTXISD::MUL_WIDE_SIGNED:
370 return "NVPTXISD::MUL_WIDE_SIGNED";
371 case NVPTXISD::MUL_WIDE_UNSIGNED:
372 return "NVPTXISD::MUL_WIDE_UNSIGNED";
373 case NVPTXISD::Tex1DFloatS32: return "NVPTXISD::Tex1DFloatS32";
374 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
375 case NVPTXISD::Tex1DFloatFloatLevel:
376 return "NVPTXISD::Tex1DFloatFloatLevel";
377 case NVPTXISD::Tex1DFloatFloatGrad:
378 return "NVPTXISD::Tex1DFloatFloatGrad";
379 case NVPTXISD::Tex1DS32S32: return "NVPTXISD::Tex1DS32S32";
380 case NVPTXISD::Tex1DS32Float: return "NVPTXISD::Tex1DS32Float";
381 case NVPTXISD::Tex1DS32FloatLevel:
382 return "NVPTXISD::Tex1DS32FloatLevel";
383 case NVPTXISD::Tex1DS32FloatGrad:
384 return "NVPTXISD::Tex1DS32FloatGrad";
385 case NVPTXISD::Tex1DU32S32: return "NVPTXISD::Tex1DU32S32";
386 case NVPTXISD::Tex1DU32Float: return "NVPTXISD::Tex1DU32Float";
387 case NVPTXISD::Tex1DU32FloatLevel:
388 return "NVPTXISD::Tex1DU32FloatLevel";
389 case NVPTXISD::Tex1DU32FloatGrad:
390 return "NVPTXISD::Tex1DU32FloatGrad";
391 case NVPTXISD::Tex1DArrayFloatS32: return "NVPTXISD::Tex1DArrayFloatS32";
392 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
393 case NVPTXISD::Tex1DArrayFloatFloatLevel:
394 return "NVPTXISD::Tex1DArrayFloatFloatLevel";
395 case NVPTXISD::Tex1DArrayFloatFloatGrad:
396 return "NVPTXISD::Tex1DArrayFloatFloatGrad";
397 case NVPTXISD::Tex1DArrayS32S32: return "NVPTXISD::Tex1DArrayS32S32";
398 case NVPTXISD::Tex1DArrayS32Float: return "NVPTXISD::Tex1DArrayS32Float";
399 case NVPTXISD::Tex1DArrayS32FloatLevel:
400 return "NVPTXISD::Tex1DArrayS32FloatLevel";
401 case NVPTXISD::Tex1DArrayS32FloatGrad:
402 return "NVPTXISD::Tex1DArrayS32FloatGrad";
403 case NVPTXISD::Tex1DArrayU32S32: return "NVPTXISD::Tex1DArrayU32S32";
404 case NVPTXISD::Tex1DArrayU32Float: return "NVPTXISD::Tex1DArrayU32Float";
405 case NVPTXISD::Tex1DArrayU32FloatLevel:
406 return "NVPTXISD::Tex1DArrayU32FloatLevel";
407 case NVPTXISD::Tex1DArrayU32FloatGrad:
408 return "NVPTXISD::Tex1DArrayU32FloatGrad";
409 case NVPTXISD::Tex2DFloatS32: return "NVPTXISD::Tex2DFloatS32";
410 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
411 case NVPTXISD::Tex2DFloatFloatLevel:
412 return "NVPTXISD::Tex2DFloatFloatLevel";
413 case NVPTXISD::Tex2DFloatFloatGrad:
414 return "NVPTXISD::Tex2DFloatFloatGrad";
415 case NVPTXISD::Tex2DS32S32: return "NVPTXISD::Tex2DS32S32";
416 case NVPTXISD::Tex2DS32Float: return "NVPTXISD::Tex2DS32Float";
417 case NVPTXISD::Tex2DS32FloatLevel:
418 return "NVPTXISD::Tex2DS32FloatLevel";
419 case NVPTXISD::Tex2DS32FloatGrad:
420 return "NVPTXISD::Tex2DS32FloatGrad";
421 case NVPTXISD::Tex2DU32S32: return "NVPTXISD::Tex2DU32S32";
422 case NVPTXISD::Tex2DU32Float: return "NVPTXISD::Tex2DU32Float";
423 case NVPTXISD::Tex2DU32FloatLevel:
424 return "NVPTXISD::Tex2DU32FloatLevel";
425 case NVPTXISD::Tex2DU32FloatGrad:
426 return "NVPTXISD::Tex2DU32FloatGrad";
427 case NVPTXISD::Tex2DArrayFloatS32: return "NVPTXISD::Tex2DArrayFloatS32";
428 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
429 case NVPTXISD::Tex2DArrayFloatFloatLevel:
430 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
431 case NVPTXISD::Tex2DArrayFloatFloatGrad:
432 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
433 case NVPTXISD::Tex2DArrayS32S32: return "NVPTXISD::Tex2DArrayS32S32";
434 case NVPTXISD::Tex2DArrayS32Float: return "NVPTXISD::Tex2DArrayS32Float";
435 case NVPTXISD::Tex2DArrayS32FloatLevel:
436 return "NVPTXISD::Tex2DArrayS32FloatLevel";
437 case NVPTXISD::Tex2DArrayS32FloatGrad:
438 return "NVPTXISD::Tex2DArrayS32FloatGrad";
439 case NVPTXISD::Tex2DArrayU32S32: return "NVPTXISD::Tex2DArrayU32S32";
440 case NVPTXISD::Tex2DArrayU32Float: return "NVPTXISD::Tex2DArrayU32Float";
441 case NVPTXISD::Tex2DArrayU32FloatLevel:
442 return "NVPTXISD::Tex2DArrayU32FloatLevel";
443 case NVPTXISD::Tex2DArrayU32FloatGrad:
444 return "NVPTXISD::Tex2DArrayU32FloatGrad";
445 case NVPTXISD::Tex3DFloatS32: return "NVPTXISD::Tex3DFloatS32";
446 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
447 case NVPTXISD::Tex3DFloatFloatLevel:
448 return "NVPTXISD::Tex3DFloatFloatLevel";
449 case NVPTXISD::Tex3DFloatFloatGrad:
450 return "NVPTXISD::Tex3DFloatFloatGrad";
451 case NVPTXISD::Tex3DS32S32: return "NVPTXISD::Tex3DS32S32";
452 case NVPTXISD::Tex3DS32Float: return "NVPTXISD::Tex3DS32Float";
453 case NVPTXISD::Tex3DS32FloatLevel:
454 return "NVPTXISD::Tex3DS32FloatLevel";
455 case NVPTXISD::Tex3DS32FloatGrad:
456 return "NVPTXISD::Tex3DS32FloatGrad";
457 case NVPTXISD::Tex3DU32S32: return "NVPTXISD::Tex3DU32S32";
458 case NVPTXISD::Tex3DU32Float: return "NVPTXISD::Tex3DU32Float";
459 case NVPTXISD::Tex3DU32FloatLevel:
460 return "NVPTXISD::Tex3DU32FloatLevel";
461 case NVPTXISD::Tex3DU32FloatGrad:
462 return "NVPTXISD::Tex3DU32FloatGrad";
463 case NVPTXISD::TexCubeFloatFloat: return "NVPTXISD::TexCubeFloatFloat";
464 case NVPTXISD::TexCubeFloatFloatLevel:
465 return "NVPTXISD::TexCubeFloatFloatLevel";
466 case NVPTXISD::TexCubeS32Float: return "NVPTXISD::TexCubeS32Float";
467 case NVPTXISD::TexCubeS32FloatLevel:
468 return "NVPTXISD::TexCubeS32FloatLevel";
469 case NVPTXISD::TexCubeU32Float: return "NVPTXISD::TexCubeU32Float";
470 case NVPTXISD::TexCubeU32FloatLevel:
471 return "NVPTXISD::TexCubeU32FloatLevel";
472 case NVPTXISD::TexCubeArrayFloatFloat:
473 return "NVPTXISD::TexCubeArrayFloatFloat";
474 case NVPTXISD::TexCubeArrayFloatFloatLevel:
475 return "NVPTXISD::TexCubeArrayFloatFloatLevel";
476 case NVPTXISD::TexCubeArrayS32Float:
477 return "NVPTXISD::TexCubeArrayS32Float";
478 case NVPTXISD::TexCubeArrayS32FloatLevel:
479 return "NVPTXISD::TexCubeArrayS32FloatLevel";
480 case NVPTXISD::TexCubeArrayU32Float:
481 return "NVPTXISD::TexCubeArrayU32Float";
482 case NVPTXISD::TexCubeArrayU32FloatLevel:
483 return "NVPTXISD::TexCubeArrayU32FloatLevel";
484 case NVPTXISD::Tld4R2DFloatFloat:
485 return "NVPTXISD::Tld4R2DFloatFloat";
486 case NVPTXISD::Tld4G2DFloatFloat:
487 return "NVPTXISD::Tld4G2DFloatFloat";
488 case NVPTXISD::Tld4B2DFloatFloat:
489 return "NVPTXISD::Tld4B2DFloatFloat";
490 case NVPTXISD::Tld4A2DFloatFloat:
491 return "NVPTXISD::Tld4A2DFloatFloat";
492 case NVPTXISD::Tld4R2DS64Float:
493 return "NVPTXISD::Tld4R2DS64Float";
494 case NVPTXISD::Tld4G2DS64Float:
495 return "NVPTXISD::Tld4G2DS64Float";
496 case NVPTXISD::Tld4B2DS64Float:
497 return "NVPTXISD::Tld4B2DS64Float";
498 case NVPTXISD::Tld4A2DS64Float:
499 return "NVPTXISD::Tld4A2DS64Float";
500 case NVPTXISD::Tld4R2DU64Float:
501 return "NVPTXISD::Tld4R2DU64Float";
502 case NVPTXISD::Tld4G2DU64Float:
503 return "NVPTXISD::Tld4G2DU64Float";
504 case NVPTXISD::Tld4B2DU64Float:
505 return "NVPTXISD::Tld4B2DU64Float";
506 case NVPTXISD::Tld4A2DU64Float:
507 return "NVPTXISD::Tld4A2DU64Float";
509 case NVPTXISD::TexUnified1DFloatS32:
510 return "NVPTXISD::TexUnified1DFloatS32";
511 case NVPTXISD::TexUnified1DFloatFloat:
512 return "NVPTXISD::TexUnified1DFloatFloat";
513 case NVPTXISD::TexUnified1DFloatFloatLevel:
514 return "NVPTXISD::TexUnified1DFloatFloatLevel";
515 case NVPTXISD::TexUnified1DFloatFloatGrad:
516 return "NVPTXISD::TexUnified1DFloatFloatGrad";
517 case NVPTXISD::TexUnified1DS32S32:
518 return "NVPTXISD::TexUnified1DS32S32";
519 case NVPTXISD::TexUnified1DS32Float:
520 return "NVPTXISD::TexUnified1DS32Float";
521 case NVPTXISD::TexUnified1DS32FloatLevel:
522 return "NVPTXISD::TexUnified1DS32FloatLevel";
523 case NVPTXISD::TexUnified1DS32FloatGrad:
524 return "NVPTXISD::TexUnified1DS32FloatGrad";
525 case NVPTXISD::TexUnified1DU32S32:
526 return "NVPTXISD::TexUnified1DU32S32";
527 case NVPTXISD::TexUnified1DU32Float:
528 return "NVPTXISD::TexUnified1DU32Float";
529 case NVPTXISD::TexUnified1DU32FloatLevel:
530 return "NVPTXISD::TexUnified1DU32FloatLevel";
531 case NVPTXISD::TexUnified1DU32FloatGrad:
532 return "NVPTXISD::TexUnified1DU32FloatGrad";
533 case NVPTXISD::TexUnified1DArrayFloatS32:
534 return "NVPTXISD::TexUnified1DArrayFloatS32";
535 case NVPTXISD::TexUnified1DArrayFloatFloat:
536 return "NVPTXISD::TexUnified1DArrayFloatFloat";
537 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
538 return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
539 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
540 return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
541 case NVPTXISD::TexUnified1DArrayS32S32:
542 return "NVPTXISD::TexUnified1DArrayS32S32";
543 case NVPTXISD::TexUnified1DArrayS32Float:
544 return "NVPTXISD::TexUnified1DArrayS32Float";
545 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
546 return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
547 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
548 return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
549 case NVPTXISD::TexUnified1DArrayU32S32:
550 return "NVPTXISD::TexUnified1DArrayU32S32";
551 case NVPTXISD::TexUnified1DArrayU32Float:
552 return "NVPTXISD::TexUnified1DArrayU32Float";
553 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
554 return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
555 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
556 return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
557 case NVPTXISD::TexUnified2DFloatS32:
558 return "NVPTXISD::TexUnified2DFloatS32";
559 case NVPTXISD::TexUnified2DFloatFloat:
560 return "NVPTXISD::TexUnified2DFloatFloat";
561 case NVPTXISD::TexUnified2DFloatFloatLevel:
562 return "NVPTXISD::TexUnified2DFloatFloatLevel";
563 case NVPTXISD::TexUnified2DFloatFloatGrad:
564 return "NVPTXISD::TexUnified2DFloatFloatGrad";
565 case NVPTXISD::TexUnified2DS32S32:
566 return "NVPTXISD::TexUnified2DS32S32";
567 case NVPTXISD::TexUnified2DS32Float:
568 return "NVPTXISD::TexUnified2DS32Float";
569 case NVPTXISD::TexUnified2DS32FloatLevel:
570 return "NVPTXISD::TexUnified2DS32FloatLevel";
571 case NVPTXISD::TexUnified2DS32FloatGrad:
572 return "NVPTXISD::TexUnified2DS32FloatGrad";
573 case NVPTXISD::TexUnified2DU32S32:
574 return "NVPTXISD::TexUnified2DU32S32";
575 case NVPTXISD::TexUnified2DU32Float:
576 return "NVPTXISD::TexUnified2DU32Float";
577 case NVPTXISD::TexUnified2DU32FloatLevel:
578 return "NVPTXISD::TexUnified2DU32FloatLevel";
579 case NVPTXISD::TexUnified2DU32FloatGrad:
580 return "NVPTXISD::TexUnified2DU32FloatGrad";
581 case NVPTXISD::TexUnified2DArrayFloatS32:
582 return "NVPTXISD::TexUnified2DArrayFloatS32";
583 case NVPTXISD::TexUnified2DArrayFloatFloat:
584 return "NVPTXISD::TexUnified2DArrayFloatFloat";
585 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
586 return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
587 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
588 return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
589 case NVPTXISD::TexUnified2DArrayS32S32:
590 return "NVPTXISD::TexUnified2DArrayS32S32";
591 case NVPTXISD::TexUnified2DArrayS32Float:
592 return "NVPTXISD::TexUnified2DArrayS32Float";
593 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
594 return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
595 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
596 return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
597 case NVPTXISD::TexUnified2DArrayU32S32:
598 return "NVPTXISD::TexUnified2DArrayU32S32";
599 case NVPTXISD::TexUnified2DArrayU32Float:
600 return "NVPTXISD::TexUnified2DArrayU32Float";
601 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
602 return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
603 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
604 return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
605 case NVPTXISD::TexUnified3DFloatS32:
606 return "NVPTXISD::TexUnified3DFloatS32";
607 case NVPTXISD::TexUnified3DFloatFloat:
608 return "NVPTXISD::TexUnified3DFloatFloat";
609 case NVPTXISD::TexUnified3DFloatFloatLevel:
610 return "NVPTXISD::TexUnified3DFloatFloatLevel";
611 case NVPTXISD::TexUnified3DFloatFloatGrad:
612 return "NVPTXISD::TexUnified3DFloatFloatGrad";
613 case NVPTXISD::TexUnified3DS32S32:
614 return "NVPTXISD::TexUnified3DS32S32";
615 case NVPTXISD::TexUnified3DS32Float:
616 return "NVPTXISD::TexUnified3DS32Float";
617 case NVPTXISD::TexUnified3DS32FloatLevel:
618 return "NVPTXISD::TexUnified3DS32FloatLevel";
619 case NVPTXISD::TexUnified3DS32FloatGrad:
620 return "NVPTXISD::TexUnified3DS32FloatGrad";
621 case NVPTXISD::TexUnified3DU32S32:
622 return "NVPTXISD::TexUnified3DU32S32";
623 case NVPTXISD::TexUnified3DU32Float:
624 return "NVPTXISD::TexUnified3DU32Float";
625 case NVPTXISD::TexUnified3DU32FloatLevel:
626 return "NVPTXISD::TexUnified3DU32FloatLevel";
627 case NVPTXISD::TexUnified3DU32FloatGrad:
628 return "NVPTXISD::TexUnified3DU32FloatGrad";
629 case NVPTXISD::TexUnifiedCubeFloatFloat:
630 return "NVPTXISD::TexUnifiedCubeFloatFloat";
631 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
632 return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
633 case NVPTXISD::TexUnifiedCubeS32Float:
634 return "NVPTXISD::TexUnifiedCubeS32Float";
635 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
636 return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
637 case NVPTXISD::TexUnifiedCubeU32Float:
638 return "NVPTXISD::TexUnifiedCubeU32Float";
639 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
640 return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
641 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
642 return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
643 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
644 return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
645 case NVPTXISD::TexUnifiedCubeArrayS32Float:
646 return "NVPTXISD::TexUnifiedCubeArrayS32Float";
647 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
648 return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
649 case NVPTXISD::TexUnifiedCubeArrayU32Float:
650 return "NVPTXISD::TexUnifiedCubeArrayU32Float";
651 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
652 return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
653 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
654 return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
655 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
656 return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
657 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
658 return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
659 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
660 return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
661 case NVPTXISD::Tld4UnifiedR2DS64Float:
662 return "NVPTXISD::Tld4UnifiedR2DS64Float";
663 case NVPTXISD::Tld4UnifiedG2DS64Float:
664 return "NVPTXISD::Tld4UnifiedG2DS64Float";
665 case NVPTXISD::Tld4UnifiedB2DS64Float:
666 return "NVPTXISD::Tld4UnifiedB2DS64Float";
667 case NVPTXISD::Tld4UnifiedA2DS64Float:
668 return "NVPTXISD::Tld4UnifiedA2DS64Float";
669 case NVPTXISD::Tld4UnifiedR2DU64Float:
670 return "NVPTXISD::Tld4UnifiedR2DU64Float";
671 case NVPTXISD::Tld4UnifiedG2DU64Float:
672 return "NVPTXISD::Tld4UnifiedG2DU64Float";
673 case NVPTXISD::Tld4UnifiedB2DU64Float:
674 return "NVPTXISD::Tld4UnifiedB2DU64Float";
675 case NVPTXISD::Tld4UnifiedA2DU64Float:
676 return "NVPTXISD::Tld4UnifiedA2DU64Float";
678 case NVPTXISD::Suld1DI8Clamp: return "NVPTXISD::Suld1DI8Clamp";
679 case NVPTXISD::Suld1DI16Clamp: return "NVPTXISD::Suld1DI16Clamp";
680 case NVPTXISD::Suld1DI32Clamp: return "NVPTXISD::Suld1DI32Clamp";
681 case NVPTXISD::Suld1DI64Clamp: return "NVPTXISD::Suld1DI64Clamp";
682 case NVPTXISD::Suld1DV2I8Clamp: return "NVPTXISD::Suld1DV2I8Clamp";
683 case NVPTXISD::Suld1DV2I16Clamp: return "NVPTXISD::Suld1DV2I16Clamp";
684 case NVPTXISD::Suld1DV2I32Clamp: return "NVPTXISD::Suld1DV2I32Clamp";
685 case NVPTXISD::Suld1DV2I64Clamp: return "NVPTXISD::Suld1DV2I64Clamp";
686 case NVPTXISD::Suld1DV4I8Clamp: return "NVPTXISD::Suld1DV4I8Clamp";
687 case NVPTXISD::Suld1DV4I16Clamp: return "NVPTXISD::Suld1DV4I16Clamp";
688 case NVPTXISD::Suld1DV4I32Clamp: return "NVPTXISD::Suld1DV4I32Clamp";
690 case NVPTXISD::Suld1DArrayI8Clamp: return "NVPTXISD::Suld1DArrayI8Clamp";
691 case NVPTXISD::Suld1DArrayI16Clamp: return "NVPTXISD::Suld1DArrayI16Clamp";
692 case NVPTXISD::Suld1DArrayI32Clamp: return "NVPTXISD::Suld1DArrayI32Clamp";
693 case NVPTXISD::Suld1DArrayI64Clamp: return "NVPTXISD::Suld1DArrayI64Clamp";
694 case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
695 case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
696 case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
697 case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
698 case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
699 case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
700 case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
702 case NVPTXISD::Suld2DI8Clamp: return "NVPTXISD::Suld2DI8Clamp";
703 case NVPTXISD::Suld2DI16Clamp: return "NVPTXISD::Suld2DI16Clamp";
704 case NVPTXISD::Suld2DI32Clamp: return "NVPTXISD::Suld2DI32Clamp";
705 case NVPTXISD::Suld2DI64Clamp: return "NVPTXISD::Suld2DI64Clamp";
706 case NVPTXISD::Suld2DV2I8Clamp: return "NVPTXISD::Suld2DV2I8Clamp";
707 case NVPTXISD::Suld2DV2I16Clamp: return "NVPTXISD::Suld2DV2I16Clamp";
708 case NVPTXISD::Suld2DV2I32Clamp: return "NVPTXISD::Suld2DV2I32Clamp";
709 case NVPTXISD::Suld2DV2I64Clamp: return "NVPTXISD::Suld2DV2I64Clamp";
710 case NVPTXISD::Suld2DV4I8Clamp: return "NVPTXISD::Suld2DV4I8Clamp";
711 case NVPTXISD::Suld2DV4I16Clamp: return "NVPTXISD::Suld2DV4I16Clamp";
712 case NVPTXISD::Suld2DV4I32Clamp: return "NVPTXISD::Suld2DV4I32Clamp";
714 case NVPTXISD::Suld2DArrayI8Clamp: return "NVPTXISD::Suld2DArrayI8Clamp";
715 case NVPTXISD::Suld2DArrayI16Clamp: return "NVPTXISD::Suld2DArrayI16Clamp";
716 case NVPTXISD::Suld2DArrayI32Clamp: return "NVPTXISD::Suld2DArrayI32Clamp";
717 case NVPTXISD::Suld2DArrayI64Clamp: return "NVPTXISD::Suld2DArrayI64Clamp";
718 case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
719 case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
720 case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
721 case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
722 case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
723 case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
724 case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
726 case NVPTXISD::Suld3DI8Clamp: return "NVPTXISD::Suld3DI8Clamp";
727 case NVPTXISD::Suld3DI16Clamp: return "NVPTXISD::Suld3DI16Clamp";
728 case NVPTXISD::Suld3DI32Clamp: return "NVPTXISD::Suld3DI32Clamp";
729 case NVPTXISD::Suld3DI64Clamp: return "NVPTXISD::Suld3DI64Clamp";
730 case NVPTXISD::Suld3DV2I8Clamp: return "NVPTXISD::Suld3DV2I8Clamp";
731 case NVPTXISD::Suld3DV2I16Clamp: return "NVPTXISD::Suld3DV2I16Clamp";
732 case NVPTXISD::Suld3DV2I32Clamp: return "NVPTXISD::Suld3DV2I32Clamp";
733 case NVPTXISD::Suld3DV2I64Clamp: return "NVPTXISD::Suld3DV2I64Clamp";
734 case NVPTXISD::Suld3DV4I8Clamp: return "NVPTXISD::Suld3DV4I8Clamp";
735 case NVPTXISD::Suld3DV4I16Clamp: return "NVPTXISD::Suld3DV4I16Clamp";
736 case NVPTXISD::Suld3DV4I32Clamp: return "NVPTXISD::Suld3DV4I32Clamp";
738 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
739 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
740 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
741 case NVPTXISD::Suld1DI64Trap: return "NVPTXISD::Suld1DI64Trap";
742 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
743 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
744 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
745 case NVPTXISD::Suld1DV2I64Trap: return "NVPTXISD::Suld1DV2I64Trap";
746 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
747 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
748 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
750 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
751 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
752 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
753 case NVPTXISD::Suld1DArrayI64Trap: return "NVPTXISD::Suld1DArrayI64Trap";
754 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
755 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
756 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
757 case NVPTXISD::Suld1DArrayV2I64Trap: return "NVPTXISD::Suld1DArrayV2I64Trap";
758 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
759 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
760 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
762 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
763 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
764 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
765 case NVPTXISD::Suld2DI64Trap: return "NVPTXISD::Suld2DI64Trap";
766 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
767 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
768 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
769 case NVPTXISD::Suld2DV2I64Trap: return "NVPTXISD::Suld2DV2I64Trap";
770 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
771 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
772 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
774 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
775 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
776 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
777 case NVPTXISD::Suld2DArrayI64Trap: return "NVPTXISD::Suld2DArrayI64Trap";
778 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
779 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
780 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
781 case NVPTXISD::Suld2DArrayV2I64Trap: return "NVPTXISD::Suld2DArrayV2I64Trap";
782 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
783 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
784 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
786 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
787 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
788 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
789 case NVPTXISD::Suld3DI64Trap: return "NVPTXISD::Suld3DI64Trap";
790 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
791 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
792 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
793 case NVPTXISD::Suld3DV2I64Trap: return "NVPTXISD::Suld3DV2I64Trap";
794 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
795 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
796 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
798 case NVPTXISD::Suld1DI8Zero: return "NVPTXISD::Suld1DI8Zero";
799 case NVPTXISD::Suld1DI16Zero: return "NVPTXISD::Suld1DI16Zero";
800 case NVPTXISD::Suld1DI32Zero: return "NVPTXISD::Suld1DI32Zero";
801 case NVPTXISD::Suld1DI64Zero: return "NVPTXISD::Suld1DI64Zero";
802 case NVPTXISD::Suld1DV2I8Zero: return "NVPTXISD::Suld1DV2I8Zero";
803 case NVPTXISD::Suld1DV2I16Zero: return "NVPTXISD::Suld1DV2I16Zero";
804 case NVPTXISD::Suld1DV2I32Zero: return "NVPTXISD::Suld1DV2I32Zero";
805 case NVPTXISD::Suld1DV2I64Zero: return "NVPTXISD::Suld1DV2I64Zero";
806 case NVPTXISD::Suld1DV4I8Zero: return "NVPTXISD::Suld1DV4I8Zero";
807 case NVPTXISD::Suld1DV4I16Zero: return "NVPTXISD::Suld1DV4I16Zero";
808 case NVPTXISD::Suld1DV4I32Zero: return "NVPTXISD::Suld1DV4I32Zero";
810 case NVPTXISD::Suld1DArrayI8Zero: return "NVPTXISD::Suld1DArrayI8Zero";
811 case NVPTXISD::Suld1DArrayI16Zero: return "NVPTXISD::Suld1DArrayI16Zero";
812 case NVPTXISD::Suld1DArrayI32Zero: return "NVPTXISD::Suld1DArrayI32Zero";
813 case NVPTXISD::Suld1DArrayI64Zero: return "NVPTXISD::Suld1DArrayI64Zero";
814 case NVPTXISD::Suld1DArrayV2I8Zero: return "NVPTXISD::Suld1DArrayV2I8Zero";
815 case NVPTXISD::Suld1DArrayV2I16Zero: return "NVPTXISD::Suld1DArrayV2I16Zero";
816 case NVPTXISD::Suld1DArrayV2I32Zero: return "NVPTXISD::Suld1DArrayV2I32Zero";
817 case NVPTXISD::Suld1DArrayV2I64Zero: return "NVPTXISD::Suld1DArrayV2I64Zero";
818 case NVPTXISD::Suld1DArrayV4I8Zero: return "NVPTXISD::Suld1DArrayV4I8Zero";
819 case NVPTXISD::Suld1DArrayV4I16Zero: return "NVPTXISD::Suld1DArrayV4I16Zero";
820 case NVPTXISD::Suld1DArrayV4I32Zero: return "NVPTXISD::Suld1DArrayV4I32Zero";
822 case NVPTXISD::Suld2DI8Zero: return "NVPTXISD::Suld2DI8Zero";
823 case NVPTXISD::Suld2DI16Zero: return "NVPTXISD::Suld2DI16Zero";
824 case NVPTXISD::Suld2DI32Zero: return "NVPTXISD::Suld2DI32Zero";
825 case NVPTXISD::Suld2DI64Zero: return "NVPTXISD::Suld2DI64Zero";
826 case NVPTXISD::Suld2DV2I8Zero: return "NVPTXISD::Suld2DV2I8Zero";
827 case NVPTXISD::Suld2DV2I16Zero: return "NVPTXISD::Suld2DV2I16Zero";
828 case NVPTXISD::Suld2DV2I32Zero: return "NVPTXISD::Suld2DV2I32Zero";
829 case NVPTXISD::Suld2DV2I64Zero: return "NVPTXISD::Suld2DV2I64Zero";
830 case NVPTXISD::Suld2DV4I8Zero: return "NVPTXISD::Suld2DV4I8Zero";
831 case NVPTXISD::Suld2DV4I16Zero: return "NVPTXISD::Suld2DV4I16Zero";
832 case NVPTXISD::Suld2DV4I32Zero: return "NVPTXISD::Suld2DV4I32Zero";
834 case NVPTXISD::Suld2DArrayI8Zero: return "NVPTXISD::Suld2DArrayI8Zero";
835 case NVPTXISD::Suld2DArrayI16Zero: return "NVPTXISD::Suld2DArrayI16Zero";
836 case NVPTXISD::Suld2DArrayI32Zero: return "NVPTXISD::Suld2DArrayI32Zero";
837 case NVPTXISD::Suld2DArrayI64Zero: return "NVPTXISD::Suld2DArrayI64Zero";
838 case NVPTXISD::Suld2DArrayV2I8Zero: return "NVPTXISD::Suld2DArrayV2I8Zero";
839 case NVPTXISD::Suld2DArrayV2I16Zero: return "NVPTXISD::Suld2DArrayV2I16Zero";
840 case NVPTXISD::Suld2DArrayV2I32Zero: return "NVPTXISD::Suld2DArrayV2I32Zero";
841 case NVPTXISD::Suld2DArrayV2I64Zero: return "NVPTXISD::Suld2DArrayV2I64Zero";
842 case NVPTXISD::Suld2DArrayV4I8Zero: return "NVPTXISD::Suld2DArrayV4I8Zero";
843 case NVPTXISD::Suld2DArrayV4I16Zero: return "NVPTXISD::Suld2DArrayV4I16Zero";
844 case NVPTXISD::Suld2DArrayV4I32Zero: return "NVPTXISD::Suld2DArrayV4I32Zero";
846 case NVPTXISD::Suld3DI8Zero: return "NVPTXISD::Suld3DI8Zero";
847 case NVPTXISD::Suld3DI16Zero: return "NVPTXISD::Suld3DI16Zero";
848 case NVPTXISD::Suld3DI32Zero: return "NVPTXISD::Suld3DI32Zero";
849 case NVPTXISD::Suld3DI64Zero: return "NVPTXISD::Suld3DI64Zero";
850 case NVPTXISD::Suld3DV2I8Zero: return "NVPTXISD::Suld3DV2I8Zero";
851 case NVPTXISD::Suld3DV2I16Zero: return "NVPTXISD::Suld3DV2I16Zero";
852 case NVPTXISD::Suld3DV2I32Zero: return "NVPTXISD::Suld3DV2I32Zero";
853 case NVPTXISD::Suld3DV2I64Zero: return "NVPTXISD::Suld3DV2I64Zero";
854 case NVPTXISD::Suld3DV4I8Zero: return "NVPTXISD::Suld3DV4I8Zero";
855 case NVPTXISD::Suld3DV4I16Zero: return "NVPTXISD::Suld3DV4I16Zero";
856 case NVPTXISD::Suld3DV4I32Zero: return "NVPTXISD::Suld3DV4I32Zero";
860 TargetLoweringBase::LegalizeTypeAction
861 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
862 if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
863 return TypeSplitVector;
865 return TargetLoweringBase::getPreferredVectorAction(VT);
869 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
871 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
872 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
873 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
877 NVPTXTargetLowering::getPrototype(Type *retTy, const ArgListTy &Args,
878 const SmallVectorImpl<ISD::OutputArg> &Outs,
879 unsigned retAlignment,
880 const ImmutableCallSite *CS) const {
882 bool isABI = (STI.getSmVersion() >= 20);
883 assert(isABI && "Non-ABI compilation is not supported");
888 O << "prototype_" << uniqueCallSite << " : .callprototype ";
890 if (retTy->getTypeID() == Type::VoidTyID) {
894 if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
896 if (const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
897 size = ITy->getBitWidth();
901 assert(retTy->isFloatingPointTy() &&
902 "Floating point type expected here");
903 size = retTy->getPrimitiveSizeInBits();
906 O << ".param .b" << size << " _";
907 } else if (isa<PointerType>(retTy)) {
908 O << ".param .b" << getPointerTy().getSizeInBits() << " _";
909 } else if ((retTy->getTypeID() == Type::StructTyID) ||
910 isa<VectorType>(retTy)) {
911 O << ".param .align "
914 << getDataLayout()->getTypeAllocSize(retTy) << "]";
916 llvm_unreachable("Unknown return type");
923 MVT thePointerTy = getPointerTy();
926 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
927 Type *Ty = Args[i].Ty;
933 if (!Outs[OIdx].Flags.isByVal()) {
934 if (Ty->isAggregateType() || Ty->isVectorTy()) {
936 const CallInst *CallI = cast<CallInst>(CS->getInstruction());
937 const DataLayout *TD = getDataLayout();
938 // +1 because index 0 is reserved for return type alignment
939 if (!llvm::getAlign(*CallI, i + 1, align))
940 align = TD->getABITypeAlignment(Ty);
941 unsigned sz = TD->getTypeAllocSize(Ty);
942 O << ".param .align " << align << " .b8 ";
944 O << "[" << sz << "]";
945 // update the index for Outs
946 SmallVector<EVT, 16> vtparts;
947 ComputeValueVTs(*this, Ty, vtparts);
948 if (unsigned len = vtparts.size())
952 // i8 types in IR will be i16 types in SDAG
953 assert((getValueType(Ty) == Outs[OIdx].VT ||
954 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
955 "type mismatch between callee prototype and arguments");
958 if (isa<IntegerType>(Ty)) {
959 sz = cast<IntegerType>(Ty)->getBitWidth();
962 } else if (isa<PointerType>(Ty))
963 sz = thePointerTy.getSizeInBits();
965 sz = Ty->getPrimitiveSizeInBits();
966 O << ".param .b" << sz << " ";
970 const PointerType *PTy = dyn_cast<PointerType>(Ty);
971 assert(PTy && "Param with byval attribute should be a pointer type");
972 Type *ETy = PTy->getElementType();
974 unsigned align = Outs[OIdx].Flags.getByValAlign();
975 unsigned sz = getDataLayout()->getTypeAllocSize(ETy);
976 O << ".param .align " << align << " .b8 ";
978 O << "[" << sz << "]";
985 NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
986 const ImmutableCallSite *CS,
988 unsigned Idx) const {
989 const DataLayout *TD = getDataLayout();
991 const Value *DirectCallee = CS->getCalledFunction();
994 // We don't have a direct function symbol, but that may be because of
995 // constant cast instructions in the call.
996 const Instruction *CalleeI = CS->getInstruction();
997 assert(CalleeI && "Call target is not a function or derived value?");
999 // With bitcast'd call targets, the instruction will be the call
1000 if (isa<CallInst>(CalleeI)) {
1001 // Check if we have call alignment metadata
1002 if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1005 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1006 // Ignore any bitcast instructions
1007 while(isa<ConstantExpr>(CalleeV)) {
1008 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
1011 // Look through the bitcast
1012 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1015 // We have now looked past all of the bitcasts. Do we finally have a
1017 if (isa<Function>(CalleeV))
1018 DirectCallee = CalleeV;
1022 // Check for function alignment information if we found that the
1023 // ultimate target is a Function
1025 if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
1028 // Call is indirect or alignment information is not available, fall back to
1029 // the ABI type alignment
1030 return TD->getABITypeAlignment(Ty);
1033 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1034 SmallVectorImpl<SDValue> &InVals) const {
1035 SelectionDAG &DAG = CLI.DAG;
1037 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1038 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1039 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1040 SDValue Chain = CLI.Chain;
1041 SDValue Callee = CLI.Callee;
1042 bool &isTailCall = CLI.IsTailCall;
1043 ArgListTy &Args = CLI.getArgs();
1044 Type *retTy = CLI.RetTy;
1045 ImmutableCallSite *CS = CLI.CS;
1047 bool isABI = (STI.getSmVersion() >= 20);
1048 assert(isABI && "Non-ABI compilation is not supported");
1051 const DataLayout *TD = getDataLayout();
1052 MachineFunction &MF = DAG.getMachineFunction();
1053 const Function *F = MF.getFunction();
1055 SDValue tempChain = Chain;
1056 Chain = DAG.getCALLSEQ_START(Chain,
1057 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1059 SDValue InFlag = Chain.getValue(1);
1061 unsigned paramCount = 0;
1062 // Args.size() and Outs.size() need not match.
1063 // Outs.size() will be larger
1064 // * if there is an aggregate argument with multiple fields (each field
1065 // showing up separately in Outs)
1066 // * if there is a vector argument with more than typical vector-length
1067 // elements (generally if more than 4) where each vector element is
1068 // individually present in Outs.
1069 // So a different index should be used for indexing into Outs/OutVals.
1070 // See similar issue in LowerFormalArguments.
1072 // Declare the .params or .reg need to pass values
1074 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1075 EVT VT = Outs[OIdx].VT;
1076 Type *Ty = Args[i].Ty;
1078 if (!Outs[OIdx].Flags.isByVal()) {
1079 if (Ty->isAggregateType()) {
1081 SmallVector<EVT, 16> vtparts;
1082 SmallVector<uint64_t, 16> Offsets;
1083 ComputePTXValueVTs(*this, Ty, vtparts, &Offsets, 0);
1085 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1086 // declare .param .align <align> .b8 .param<n>[<size>];
1087 unsigned sz = TD->getTypeAllocSize(Ty);
1088 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1089 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, dl,
1091 DAG.getConstant(paramCount, dl, MVT::i32),
1092 DAG.getConstant(sz, dl, MVT::i32),
1094 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1096 InFlag = Chain.getValue(1);
1097 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1098 EVT elemtype = vtparts[j];
1099 unsigned ArgAlign = GreatestCommonDivisor64(align, Offsets[j]);
1100 if (elemtype.isInteger() && (sz < 8))
1102 SDValue StVal = OutVals[OIdx];
1103 if (elemtype.getSizeInBits() < 16) {
1104 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1106 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1107 SDValue CopyParamOps[] = { Chain,
1108 DAG.getConstant(paramCount, dl, MVT::i32),
1109 DAG.getConstant(Offsets[j], dl, MVT::i32),
1111 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1112 CopyParamVTs, CopyParamOps,
1113 elemtype, MachinePointerInfo(),
1115 InFlag = Chain.getValue(1);
1118 if (vtparts.size() > 0)
1123 if (Ty->isVectorTy()) {
1124 EVT ObjectVT = getValueType(Ty);
1125 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1126 // declare .param .align <align> .b8 .param<n>[<size>];
1127 unsigned sz = TD->getTypeAllocSize(Ty);
1128 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1129 SDValue DeclareParamOps[] = { Chain,
1130 DAG.getConstant(align, dl, MVT::i32),
1131 DAG.getConstant(paramCount, dl, MVT::i32),
1132 DAG.getConstant(sz, dl, MVT::i32),
1134 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1136 InFlag = Chain.getValue(1);
1137 unsigned NumElts = ObjectVT.getVectorNumElements();
1138 EVT EltVT = ObjectVT.getVectorElementType();
1140 bool NeedExtend = false;
1141 if (EltVT.getSizeInBits() < 16) {
1148 SDValue Elt = OutVals[OIdx++];
1150 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
1152 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1153 SDValue CopyParamOps[] = { Chain,
1154 DAG.getConstant(paramCount, dl, MVT::i32),
1155 DAG.getConstant(0, dl, MVT::i32), Elt,
1157 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1158 CopyParamVTs, CopyParamOps,
1159 MemVT, MachinePointerInfo());
1160 InFlag = Chain.getValue(1);
1161 } else if (NumElts == 2) {
1162 SDValue Elt0 = OutVals[OIdx++];
1163 SDValue Elt1 = OutVals[OIdx++];
1165 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
1166 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
1169 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1170 SDValue CopyParamOps[] = { Chain,
1171 DAG.getConstant(paramCount, dl, MVT::i32),
1172 DAG.getConstant(0, dl, MVT::i32), Elt0,
1174 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
1175 CopyParamVTs, CopyParamOps,
1176 MemVT, MachinePointerInfo());
1177 InFlag = Chain.getValue(1);
1179 unsigned curOffset = 0;
1181 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1183 // vector will be expanded to a power of 2 elements, so we know we can
1184 // always round up to the next multiple of 4 when creating the vector
1186 // e.g. 4 elem => 1 st.v4
1187 // 6 elem => 2 st.v4
1188 // 8 elem => 2 st.v4
1189 // 11 elem => 3 st.v4
1190 unsigned VecSize = 4;
1191 if (EltVT.getSizeInBits() == 64)
1194 // This is potentially only part of a vector, so assume all elements
1195 // are packed together.
1196 unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
1198 for (unsigned i = 0; i < NumElts; i += VecSize) {
1201 SmallVector<SDValue, 8> Ops;
1202 Ops.push_back(Chain);
1203 Ops.push_back(DAG.getConstant(paramCount, dl, MVT::i32));
1204 Ops.push_back(DAG.getConstant(curOffset, dl, MVT::i32));
1206 unsigned Opc = NVPTXISD::StoreParamV2;
1208 StoreVal = OutVals[OIdx++];
1210 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1211 Ops.push_back(StoreVal);
1213 if (i + 1 < NumElts) {
1214 StoreVal = OutVals[OIdx++];
1217 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1219 StoreVal = DAG.getUNDEF(EltVT);
1221 Ops.push_back(StoreVal);
1224 Opc = NVPTXISD::StoreParamV4;
1225 if (i + 2 < NumElts) {
1226 StoreVal = OutVals[OIdx++];
1229 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1231 StoreVal = DAG.getUNDEF(EltVT);
1233 Ops.push_back(StoreVal);
1235 if (i + 3 < NumElts) {
1236 StoreVal = OutVals[OIdx++];
1239 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1241 StoreVal = DAG.getUNDEF(EltVT);
1243 Ops.push_back(StoreVal);
1246 Ops.push_back(InFlag);
1248 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1249 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
1250 MemVT, MachinePointerInfo());
1251 InFlag = Chain.getValue(1);
1252 curOffset += PerStoreOffset;
1260 // for ABI, declare .param .b<size> .param<n>;
1261 unsigned sz = VT.getSizeInBits();
1262 bool needExtend = false;
1263 if (VT.isInteger()) {
1269 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1270 SDValue DeclareParamOps[] = { Chain,
1271 DAG.getConstant(paramCount, dl, MVT::i32),
1272 DAG.getConstant(sz, dl, MVT::i32),
1273 DAG.getConstant(0, dl, MVT::i32), InFlag };
1274 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
1276 InFlag = Chain.getValue(1);
1277 SDValue OutV = OutVals[OIdx];
1279 // zext/sext i1 to i16
1280 unsigned opc = ISD::ZERO_EXTEND;
1281 if (Outs[OIdx].Flags.isSExt())
1282 opc = ISD::SIGN_EXTEND;
1283 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
1285 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1286 SDValue CopyParamOps[] = { Chain,
1287 DAG.getConstant(paramCount, dl, MVT::i32),
1288 DAG.getConstant(0, dl, MVT::i32), OutV,
1291 unsigned opcode = NVPTXISD::StoreParam;
1292 if (Outs[OIdx].Flags.isZExt())
1293 opcode = NVPTXISD::StoreParamU32;
1294 else if (Outs[OIdx].Flags.isSExt())
1295 opcode = NVPTXISD::StoreParamS32;
1296 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
1297 VT, MachinePointerInfo());
1299 InFlag = Chain.getValue(1);
1304 SmallVector<EVT, 16> vtparts;
1305 SmallVector<uint64_t, 16> Offsets;
1306 const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
1307 assert(PTy && "Type of a byval parameter should be pointer");
1308 ComputePTXValueVTs(*this, PTy->getElementType(), vtparts, &Offsets, 0);
1310 // declare .param .align <align> .b8 .param<n>[<size>];
1311 unsigned sz = Outs[OIdx].Flags.getByValSize();
1312 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1313 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1314 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1315 // so we don't need to worry about natural alignment or not.
1316 // See TargetLowering::LowerCallTo().
1317 SDValue DeclareParamOps[] = {
1318 Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), dl, MVT::i32),
1319 DAG.getConstant(paramCount, dl, MVT::i32),
1320 DAG.getConstant(sz, dl, MVT::i32), InFlag
1322 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1324 InFlag = Chain.getValue(1);
1325 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1326 EVT elemtype = vtparts[j];
1327 int curOffset = Offsets[j];
1328 unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
1330 DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[OIdx],
1331 DAG.getConstant(curOffset, dl, getPointerTy()));
1332 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
1333 MachinePointerInfo(), false, false, false,
1335 if (elemtype.getSizeInBits() < 16) {
1336 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1338 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1339 SDValue CopyParamOps[] = { Chain,
1340 DAG.getConstant(paramCount, dl, MVT::i32),
1341 DAG.getConstant(curOffset, dl, MVT::i32),
1343 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1344 CopyParamOps, elemtype,
1345 MachinePointerInfo());
1347 InFlag = Chain.getValue(1);
1352 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
1353 unsigned retAlignment = 0;
1356 if (Ins.size() > 0) {
1357 SmallVector<EVT, 16> resvtparts;
1358 ComputeValueVTs(*this, retTy, resvtparts);
1361 // .param .align 16 .b8 retval0[<size-in-bytes>], or
1362 // .param .b<size-in-bits> retval0
1363 unsigned resultsz = TD->getTypeAllocSizeInBits(retTy);
1364 // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
1365 // these three types to match the logic in
1366 // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
1367 // Plus, this behavior is consistent with nvcc's.
1368 if (retTy->isFloatingPointTy() || retTy->isIntegerTy() ||
1369 retTy->isPointerTy()) {
1370 // Scalar needs to be at least 32bit wide
1373 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1374 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1375 DAG.getConstant(resultsz, dl, MVT::i32),
1376 DAG.getConstant(0, dl, MVT::i32), InFlag };
1377 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
1379 InFlag = Chain.getValue(1);
1381 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
1382 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1383 SDValue DeclareRetOps[] = { Chain,
1384 DAG.getConstant(retAlignment, dl, MVT::i32),
1385 DAG.getConstant(resultsz / 8, dl, MVT::i32),
1386 DAG.getConstant(0, dl, MVT::i32), InFlag };
1387 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
1389 InFlag = Chain.getValue(1);
1394 // This is indirect function call case : PTX requires a prototype of the
1396 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1397 // to be emitted, and the label has to used as the last arg of call
1399 // The prototype is embedded in a string and put as the operand for a
1400 // CallPrototype SDNode which will print out to the value of the string.
1401 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1402 std::string Proto = getPrototype(retTy, Args, Outs, retAlignment, CS);
1403 const char *ProtoStr =
1404 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1405 SDValue ProtoOps[] = {
1406 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
1408 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
1409 InFlag = Chain.getValue(1);
1411 // Op to just print "call"
1412 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1413 SDValue PrintCallOps[] = {
1414 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
1416 Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
1417 dl, PrintCallVTs, PrintCallOps);
1418 InFlag = Chain.getValue(1);
1420 // Ops to print out the function name
1421 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1422 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1423 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
1424 InFlag = Chain.getValue(1);
1426 // Ops to print out the param list
1427 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1428 SDValue CallArgBeginOps[] = { Chain, InFlag };
1429 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1431 InFlag = Chain.getValue(1);
1433 for (unsigned i = 0, e = paramCount; i != e; ++i) {
1436 opcode = NVPTXISD::LastCallArg;
1438 opcode = NVPTXISD::CallArg;
1439 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1440 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1441 DAG.getConstant(i, dl, MVT::i32), InFlag };
1442 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
1443 InFlag = Chain.getValue(1);
1445 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1446 SDValue CallArgEndOps[] = { Chain,
1447 DAG.getConstant(Func ? 1 : 0, dl, MVT::i32),
1449 Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
1450 InFlag = Chain.getValue(1);
1453 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1454 SDValue PrototypeOps[] = { Chain,
1455 DAG.getConstant(uniqueCallSite, dl, MVT::i32),
1457 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
1458 InFlag = Chain.getValue(1);
1461 // Generate loads from param memory/moves from registers for result
1462 if (Ins.size() > 0) {
1463 if (retTy && retTy->isVectorTy()) {
1464 EVT ObjectVT = getValueType(retTy);
1465 unsigned NumElts = ObjectVT.getVectorNumElements();
1466 EVT EltVT = ObjectVT.getVectorElementType();
1467 assert(STI.getTargetLowering()->getNumRegisters(F->getContext(),
1468 ObjectVT) == NumElts &&
1469 "Vector was not scalarized");
1470 unsigned sz = EltVT.getSizeInBits();
1471 bool needTruncate = sz < 8;
1474 // Just a simple load
1475 SmallVector<EVT, 4> LoadRetVTs;
1476 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1477 // If loading i1/i8 result, generate
1481 LoadRetVTs.push_back(MVT::i16);
1483 LoadRetVTs.push_back(EltVT);
1484 LoadRetVTs.push_back(MVT::Other);
1485 LoadRetVTs.push_back(MVT::Glue);
1486 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1487 DAG.getConstant(0, dl, MVT::i32), InFlag};
1488 SDValue retval = DAG.getMemIntrinsicNode(
1489 NVPTXISD::LoadParam, dl,
1490 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1491 Chain = retval.getValue(1);
1492 InFlag = retval.getValue(2);
1493 SDValue Ret0 = retval;
1495 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1496 InVals.push_back(Ret0);
1497 } else if (NumElts == 2) {
1499 SmallVector<EVT, 4> LoadRetVTs;
1500 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1501 // If loading i1/i8 result, generate
1505 LoadRetVTs.push_back(MVT::i16);
1506 LoadRetVTs.push_back(MVT::i16);
1508 LoadRetVTs.push_back(EltVT);
1509 LoadRetVTs.push_back(EltVT);
1511 LoadRetVTs.push_back(MVT::Other);
1512 LoadRetVTs.push_back(MVT::Glue);
1513 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1514 DAG.getConstant(0, dl, MVT::i32), InFlag};
1515 SDValue retval = DAG.getMemIntrinsicNode(
1516 NVPTXISD::LoadParamV2, dl,
1517 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1518 Chain = retval.getValue(2);
1519 InFlag = retval.getValue(3);
1520 SDValue Ret0 = retval.getValue(0);
1521 SDValue Ret1 = retval.getValue(1);
1523 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1524 InVals.push_back(Ret0);
1525 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1526 InVals.push_back(Ret1);
1528 InVals.push_back(Ret0);
1529 InVals.push_back(Ret1);
1532 // Split into N LoadV4
1534 unsigned VecSize = 4;
1535 unsigned Opc = NVPTXISD::LoadParamV4;
1536 if (EltVT.getSizeInBits() == 64) {
1538 Opc = NVPTXISD::LoadParamV2;
1540 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1541 for (unsigned i = 0; i < NumElts; i += VecSize) {
1542 SmallVector<EVT, 8> LoadRetVTs;
1543 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1544 // If loading i1/i8 result, generate
1548 for (unsigned j = 0; j < VecSize; ++j)
1549 LoadRetVTs.push_back(MVT::i16);
1551 for (unsigned j = 0; j < VecSize; ++j)
1552 LoadRetVTs.push_back(EltVT);
1554 LoadRetVTs.push_back(MVT::Other);
1555 LoadRetVTs.push_back(MVT::Glue);
1556 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1557 DAG.getConstant(Ofst, dl, MVT::i32), InFlag};
1558 SDValue retval = DAG.getMemIntrinsicNode(
1559 Opc, dl, DAG.getVTList(LoadRetVTs),
1560 LoadRetOps, EltVT, MachinePointerInfo());
1562 Chain = retval.getValue(2);
1563 InFlag = retval.getValue(3);
1565 Chain = retval.getValue(4);
1566 InFlag = retval.getValue(5);
1569 for (unsigned j = 0; j < VecSize; ++j) {
1570 if (i + j >= NumElts)
1572 SDValue Elt = retval.getValue(j);
1574 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1575 InVals.push_back(Elt);
1577 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1581 SmallVector<EVT, 16> VTs;
1582 SmallVector<uint64_t, 16> Offsets;
1583 ComputePTXValueVTs(*this, retTy, VTs, &Offsets, 0);
1584 assert(VTs.size() == Ins.size() && "Bad value decomposition");
1585 unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
1586 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1587 unsigned sz = VTs[i].getSizeInBits();
1588 unsigned AlignI = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1589 bool needTruncate = sz < 8;
1590 if (VTs[i].isInteger() && (sz < 8))
1593 SmallVector<EVT, 4> LoadRetVTs;
1594 EVT TheLoadType = VTs[i];
1595 if (retTy->isIntegerTy() &&
1596 TD->getTypeAllocSizeInBits(retTy) < 32) {
1597 // This is for integer types only, and specifically not for
1599 LoadRetVTs.push_back(MVT::i32);
1600 TheLoadType = MVT::i32;
1601 } else if (sz < 16) {
1602 // If loading i1/i8 result, generate
1604 // trunc i16 to i1/i8
1605 LoadRetVTs.push_back(MVT::i16);
1607 LoadRetVTs.push_back(Ins[i].VT);
1608 LoadRetVTs.push_back(MVT::Other);
1609 LoadRetVTs.push_back(MVT::Glue);
1611 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1612 DAG.getConstant(Offsets[i], dl, MVT::i32),
1614 SDValue retval = DAG.getMemIntrinsicNode(
1615 NVPTXISD::LoadParam, dl,
1616 DAG.getVTList(LoadRetVTs), LoadRetOps,
1617 TheLoadType, MachinePointerInfo(), AlignI);
1618 Chain = retval.getValue(1);
1619 InFlag = retval.getValue(2);
1620 SDValue Ret0 = retval.getValue(0);
1622 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1623 InVals.push_back(Ret0);
1628 Chain = DAG.getCALLSEQ_END(Chain,
1629 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1630 DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
1635 // set isTailCall to false for now, until we figure out how to express
1636 // tail call optimization in PTX
1641 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1642 // (see LegalizeDAG.cpp). This is slow and uses local memory.
1643 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
1645 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1646 SDNode *Node = Op.getNode();
1648 SmallVector<SDValue, 8> Ops;
1649 unsigned NumOperands = Node->getNumOperands();
1650 for (unsigned i = 0; i < NumOperands; ++i) {
1651 SDValue SubOp = Node->getOperand(i);
1652 EVT VVT = SubOp.getNode()->getValueType(0);
1653 EVT EltVT = VVT.getVectorElementType();
1654 unsigned NumSubElem = VVT.getVectorNumElements();
1655 for (unsigned j = 0; j < NumSubElem; ++j) {
1656 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1657 DAG.getIntPtrConstant(j, dl)));
1660 return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
1663 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1664 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1666 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1668 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1669 SelectionDAG &DAG) const {
1670 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1671 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1673 EVT VT = Op.getValueType();
1674 unsigned VTBits = VT.getSizeInBits();
1676 SDValue ShOpLo = Op.getOperand(0);
1677 SDValue ShOpHi = Op.getOperand(1);
1678 SDValue ShAmt = Op.getOperand(2);
1679 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1681 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1683 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1684 // {dHi, dLo} = {aHi, aLo} >> Amt
1686 // dLo = shf.r.clamp aLo, aHi, Amt
1688 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1689 SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1692 SDValue Ops[2] = { Lo, Hi };
1693 return DAG.getMergeValues(Ops, dl);
1697 // {dHi, dLo} = {aHi, aLo} >> Amt
1698 // - if (Amt>=size) then
1699 // dLo = aHi >> (Amt-size)
1700 // dHi = aHi >> Amt (this is either all 0 or all 1)
1702 // dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1705 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1706 DAG.getConstant(VTBits, dl, MVT::i32),
1708 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1709 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1710 DAG.getConstant(VTBits, dl, MVT::i32));
1711 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1712 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1713 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1715 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1716 DAG.getConstant(VTBits, dl, MVT::i32),
1718 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1719 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1721 SDValue Ops[2] = { Lo, Hi };
1722 return DAG.getMergeValues(Ops, dl);
1726 /// LowerShiftLeftParts - Lower SHL_PARTS, which
1727 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1729 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1731 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1732 SelectionDAG &DAG) const {
1733 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1734 assert(Op.getOpcode() == ISD::SHL_PARTS);
1736 EVT VT = Op.getValueType();
1737 unsigned VTBits = VT.getSizeInBits();
1739 SDValue ShOpLo = Op.getOperand(0);
1740 SDValue ShOpHi = Op.getOperand(1);
1741 SDValue ShAmt = Op.getOperand(2);
1743 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1745 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1746 // {dHi, dLo} = {aHi, aLo} << Amt
1747 // dHi = shf.l.clamp aLo, aHi, Amt
1750 SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
1752 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1754 SDValue Ops[2] = { Lo, Hi };
1755 return DAG.getMergeValues(Ops, dl);
1759 // {dHi, dLo} = {aHi, aLo} << Amt
1760 // - if (Amt>=size) then
1761 // dLo = aLo << Amt (all 0)
1762 // dLo = aLo << (Amt-size)
1765 // dHi = (aHi << Amt) | (aLo >> (size-Amt))
1767 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1768 DAG.getConstant(VTBits, dl, MVT::i32),
1770 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1771 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1772 DAG.getConstant(VTBits, dl, MVT::i32));
1773 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1774 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1775 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1777 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1778 DAG.getConstant(VTBits, dl, MVT::i32),
1780 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1781 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1783 SDValue Ops[2] = { Lo, Hi };
1784 return DAG.getMergeValues(Ops, dl);
1789 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1790 switch (Op.getOpcode()) {
1791 case ISD::RETURNADDR:
1793 case ISD::FRAMEADDR:
1795 case ISD::GlobalAddress:
1796 return LowerGlobalAddress(Op, DAG);
1797 case ISD::INTRINSIC_W_CHAIN:
1799 case ISD::BUILD_VECTOR:
1800 case ISD::EXTRACT_SUBVECTOR:
1802 case ISD::CONCAT_VECTORS:
1803 return LowerCONCAT_VECTORS(Op, DAG);
1805 return LowerSTORE(Op, DAG);
1807 return LowerLOAD(Op, DAG);
1808 case ISD::SHL_PARTS:
1809 return LowerShiftLeftParts(Op, DAG);
1810 case ISD::SRA_PARTS:
1811 case ISD::SRL_PARTS:
1812 return LowerShiftRightParts(Op, DAG);
1814 return LowerSelect(Op, DAG);
1816 llvm_unreachable("Custom lowering not defined for operation");
1820 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
1821 SDValue Op0 = Op->getOperand(0);
1822 SDValue Op1 = Op->getOperand(1);
1823 SDValue Op2 = Op->getOperand(2);
1824 SDLoc DL(Op.getNode());
1826 assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
1828 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
1829 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
1830 SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
1831 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
1836 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1837 if (Op.getValueType() == MVT::i1)
1838 return LowerLOADi1(Op, DAG);
1845 // v1 = ld i8* addr (-> i16)
1846 // v = trunc i16 to i1
1847 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
1848 SDNode *Node = Op.getNode();
1849 LoadSDNode *LD = cast<LoadSDNode>(Node);
1851 assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
1852 assert(Node->getValueType(0) == MVT::i1 &&
1853 "Custom lowering for i1 load only");
1855 DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
1856 LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
1857 LD->isInvariant(), LD->getAlignment());
1858 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1859 // The legalizer (the caller) is expecting two values from the legalized
1860 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1861 // in LegalizeDAG.cpp which also uses MergeValues.
1862 SDValue Ops[] = { result, LD->getChain() };
1863 return DAG.getMergeValues(Ops, dl);
1866 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1867 EVT ValVT = Op.getOperand(1).getValueType();
1868 if (ValVT == MVT::i1)
1869 return LowerSTOREi1(Op, DAG);
1870 else if (ValVT.isVector())
1871 return LowerSTOREVector(Op, DAG);
1877 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1878 SDNode *N = Op.getNode();
1879 SDValue Val = N->getOperand(1);
1881 EVT ValVT = Val.getValueType();
1883 if (ValVT.isVector()) {
1884 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1885 // legal. We can (and should) split that into 2 stores of <2 x double> here
1886 // but I'm leaving that as a TODO for now.
1887 if (!ValVT.isSimple())
1889 switch (ValVT.getSimpleVT().SimpleTy) {
1902 // This is a "native" vector type
1906 MemSDNode *MemSD = cast<MemSDNode>(N);
1907 const DataLayout *TD = getDataLayout();
1909 unsigned Align = MemSD->getAlignment();
1910 unsigned PrefAlign =
1911 TD->getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
1912 if (Align < PrefAlign) {
1913 // This store is not sufficiently aligned, so bail out and let this vector
1914 // store be scalarized. Note that we may still be able to emit smaller
1915 // vector stores. For example, if we are storing a <4 x float> with an
1916 // alignment of 8, this check will fail but the legalizer will try again
1917 // with 2 x <2 x float>, which will succeed with an alignment of 8.
1921 unsigned Opcode = 0;
1922 EVT EltVT = ValVT.getVectorElementType();
1923 unsigned NumElts = ValVT.getVectorNumElements();
1925 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
1926 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
1927 // stored type to i16 and propagate the "real" type as the memory type.
1928 bool NeedExt = false;
1929 if (EltVT.getSizeInBits() < 16)
1936 Opcode = NVPTXISD::StoreV2;
1939 Opcode = NVPTXISD::StoreV4;
1944 SmallVector<SDValue, 8> Ops;
1946 // First is the chain
1947 Ops.push_back(N->getOperand(0));
1949 // Then the split values
1950 for (unsigned i = 0; i < NumElts; ++i) {
1951 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
1952 DAG.getIntPtrConstant(i, DL));
1954 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
1955 Ops.push_back(ExtVal);
1958 // Then any remaining arguments
1959 Ops.append(N->op_begin() + 2, N->op_end());
1961 SDValue NewSt = DAG.getMemIntrinsicNode(
1962 Opcode, DL, DAG.getVTList(MVT::Other), Ops,
1963 MemSD->getMemoryVT(), MemSD->getMemOperand());
1965 //return DCI.CombineTo(N, NewSt, true);
1974 // v1 = zxt v to i16
1976 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
1977 SDNode *Node = Op.getNode();
1979 StoreSDNode *ST = cast<StoreSDNode>(Node);
1980 SDValue Tmp1 = ST->getChain();
1981 SDValue Tmp2 = ST->getBasePtr();
1982 SDValue Tmp3 = ST->getValue();
1983 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
1984 unsigned Alignment = ST->getAlignment();
1985 bool isVolatile = ST->isVolatile();
1986 bool isNonTemporal = ST->isNonTemporal();
1987 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
1988 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1989 ST->getPointerInfo(), MVT::i8, isNonTemporal,
1990 isVolatile, Alignment);
1994 SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
1995 int idx, EVT v) const {
1996 std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
1997 std::stringstream suffix;
1999 *name += suffix.str();
2000 return DAG.getTargetExternalSymbol(name->c_str(), v);
2004 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
2005 std::string ParamSym;
2006 raw_string_ostream ParamStr(ParamSym);
2008 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
2011 std::string *SavedStr =
2012 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
2013 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
2016 SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
2017 return getExtSymb(DAG, ".HLPPARAM", idx);
2020 // Check to see if the kernel argument is image*_t or sampler_t
2022 bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
2023 static const char *const specialTypes[] = { "struct._image2d_t",
2024 "struct._image3d_t",
2025 "struct._sampler_t" };
2027 const Type *Ty = arg->getType();
2028 const PointerType *PTy = dyn_cast<PointerType>(Ty);
2036 const StructType *STy = dyn_cast<StructType>(PTy->getElementType());
2037 const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
2039 for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
2040 if (TypeName == specialTypes[i])
2046 SDValue NVPTXTargetLowering::LowerFormalArguments(
2047 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2048 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2049 SmallVectorImpl<SDValue> &InVals) const {
2050 MachineFunction &MF = DAG.getMachineFunction();
2051 const DataLayout *TD = getDataLayout();
2053 const Function *F = MF.getFunction();
2054 const AttributeSet &PAL = F->getAttributes();
2055 const TargetLowering *TLI = STI.getTargetLowering();
2057 SDValue Root = DAG.getRoot();
2058 std::vector<SDValue> OutChains;
2060 bool isKernel = llvm::isKernelFunction(*F);
2061 bool isABI = (STI.getSmVersion() >= 20);
2062 assert(isABI && "Non-ABI compilation is not supported");
2066 std::vector<Type *> argTypes;
2067 std::vector<const Argument *> theArgs;
2068 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
2070 theArgs.push_back(I);
2071 argTypes.push_back(I->getType());
2073 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
2074 // Ins.size() will be larger
2075 // * if there is an aggregate argument with multiple fields (each field
2076 // showing up separately in Ins)
2077 // * if there is a vector argument with more than typical vector-length
2078 // elements (generally if more than 4) where each vector element is
2079 // individually present in Ins.
2080 // So a different index should be used for indexing into Ins.
2081 // See similar issue in LowerCall.
2082 unsigned InsIdx = 0;
2085 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2086 Type *Ty = argTypes[i];
2088 // If the kernel argument is image*_t or sampler_t, convert it to
2089 // a i32 constant holding the parameter position. This can later
2090 // matched in the AsmPrinter to output the correct mangled name.
2091 if (isImageOrSamplerVal(
2093 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
2095 assert(isKernel && "Only kernels can have image/sampler params");
2096 InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32));
2100 if (theArgs[i]->use_empty()) {
2102 if (Ty->isAggregateType()) {
2103 SmallVector<EVT, 16> vtparts;
2105 ComputePTXValueVTs(*this, Ty, vtparts);
2106 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2107 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2109 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2112 if (vtparts.size() > 0)
2116 if (Ty->isVectorTy()) {
2117 EVT ObjectVT = getValueType(Ty);
2118 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
2119 for (unsigned parti = 0; parti < NumRegs; ++parti) {
2120 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2127 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2131 // In the following cases, assign a node order of "idx+1"
2132 // to newly created nodes. The SDNodes for params have to
2133 // appear in the same order as their order of appearance
2134 // in the original function. "idx+1" holds that order.
2135 if (!PAL.hasAttribute(i + 1, Attribute::ByVal)) {
2136 if (Ty->isAggregateType()) {
2137 SmallVector<EVT, 16> vtparts;
2138 SmallVector<uint64_t, 16> offsets;
2140 // NOTE: Here, we lose the ability to issue vector loads for vectors
2141 // that are a part of a struct. This should be investigated in the
2143 ComputePTXValueVTs(*this, Ty, vtparts, &offsets, 0);
2144 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2145 bool aggregateIsPacked = false;
2146 if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
2147 aggregateIsPacked = STy->isPacked();
2149 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
2150 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2152 EVT partVT = vtparts[parti];
2153 Value *srcValue = Constant::getNullValue(
2154 PointerType::get(partVT.getTypeForEVT(F->getContext()),
2155 llvm::ADDRESS_SPACE_PARAM));
2157 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
2158 DAG.getConstant(offsets[parti], dl, getPointerTy()));
2159 unsigned partAlign =
2160 aggregateIsPacked ? 1
2161 : TD->getABITypeAlignment(
2162 partVT.getTypeForEVT(F->getContext()));
2164 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
2165 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2166 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2167 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
2168 MachinePointerInfo(srcValue), partVT, false,
2169 false, false, partAlign);
2171 p = DAG.getLoad(partVT, dl, Root, srcAddr,
2172 MachinePointerInfo(srcValue), false, false, false,
2176 p.getNode()->setIROrder(idx + 1);
2177 InVals.push_back(p);
2180 if (vtparts.size() > 0)
2184 if (Ty->isVectorTy()) {
2185 EVT ObjectVT = getValueType(Ty);
2186 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
2187 unsigned NumElts = ObjectVT.getVectorNumElements();
2188 assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
2189 "Vector was not scalarized");
2190 EVT EltVT = ObjectVT.getVectorElementType();
2195 // We only have one element, so just directly load it
2196 Value *SrcValue = Constant::getNullValue(PointerType::get(
2197 EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2198 SDValue P = DAG.getLoad(
2199 EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false,
2201 TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
2203 P.getNode()->setIROrder(idx + 1);
2205 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2206 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
2207 InVals.push_back(P);
2209 } else if (NumElts == 2) {
2211 // f32,f32 = load ...
2212 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
2213 Value *SrcValue = Constant::getNullValue(PointerType::get(
2214 VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2215 SDValue P = DAG.getLoad(
2216 VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false,
2218 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2220 P.getNode()->setIROrder(idx + 1);
2222 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2223 DAG.getIntPtrConstant(0, dl));
2224 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2225 DAG.getIntPtrConstant(1, dl));
2227 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
2228 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
2229 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
2232 InVals.push_back(Elt0);
2233 InVals.push_back(Elt1);
2237 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
2239 // vector will be expanded to a power of 2 elements, so we know we can
2240 // always round up to the next multiple of 4 when creating the vector
2242 // e.g. 4 elem => 1 ld.v4
2243 // 6 elem => 2 ld.v4
2244 // 8 elem => 2 ld.v4
2245 // 11 elem => 3 ld.v4
2246 unsigned VecSize = 4;
2247 if (EltVT.getSizeInBits() == 64) {
2250 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2252 for (unsigned i = 0; i < NumElts; i += VecSize) {
2253 Value *SrcValue = Constant::getNullValue(
2254 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
2255 llvm::ADDRESS_SPACE_PARAM));
2257 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
2258 DAG.getConstant(Ofst, dl, getPointerTy()));
2259 SDValue P = DAG.getLoad(
2260 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
2262 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2264 P.getNode()->setIROrder(idx + 1);
2266 for (unsigned j = 0; j < VecSize; ++j) {
2267 if (i + j >= NumElts)
2269 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2270 DAG.getIntPtrConstant(j, dl));
2271 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2272 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
2273 InVals.push_back(Elt);
2275 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2285 EVT ObjectVT = getValueType(Ty);
2286 // If ABI, load from the param symbol
2287 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
2288 Value *srcValue = Constant::getNullValue(PointerType::get(
2289 ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2291 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
2292 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2293 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2294 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
2295 MachinePointerInfo(srcValue), ObjectVT, false, false,
2297 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2299 p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
2300 MachinePointerInfo(srcValue), false, false, false,
2301 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2304 p.getNode()->setIROrder(idx + 1);
2305 InVals.push_back(p);
2309 // Param has ByVal attribute
2310 // Return MoveParam(param symbol).
2311 // Ideally, the param symbol can be returned directly,
2312 // but when SDNode builder decides to use it in a CopyToReg(),
2313 // machine instruction fails because TargetExternalSymbol
2314 // (not lowered) is target dependent, and CopyToReg assumes
2315 // the source is lowered.
2316 EVT ObjectVT = getValueType(Ty);
2317 assert(ObjectVT == Ins[InsIdx].VT &&
2318 "Ins type did not match function type");
2319 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
2320 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
2322 p.getNode()->setIROrder(idx + 1);
2324 InVals.push_back(p);
2326 SDValue p2 = DAG.getNode(
2327 ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
2328 DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, dl, MVT::i32), p);
2329 InVals.push_back(p2);
2333 // Clang will check explicit VarArg and issue error if any. However, Clang
2334 // will let code with
2335 // implicit var arg like f() pass. See bug 617733.
2336 // We treat this case as if the arg list is empty.
2337 // if (F.isVarArg()) {
2338 // assert(0 && "VarArg not supported yet!");
2341 if (!OutChains.empty())
2342 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
2349 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2351 const SmallVectorImpl<ISD::OutputArg> &Outs,
2352 const SmallVectorImpl<SDValue> &OutVals,
2353 SDLoc dl, SelectionDAG &DAG) const {
2354 MachineFunction &MF = DAG.getMachineFunction();
2355 const Function *F = MF.getFunction();
2356 Type *RetTy = F->getReturnType();
2357 const DataLayout *TD = getDataLayout();
2359 bool isABI = (STI.getSmVersion() >= 20);
2360 assert(isABI && "Non-ABI compilation is not supported");
2364 if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
2365 // If we have a vector type, the OutVals array will be the scalarized
2366 // components and we have combine them into 1 or more vector stores.
2367 unsigned NumElts = VTy->getNumElements();
2368 assert(NumElts == Outs.size() && "Bad scalarization of return value");
2370 // const_cast can be removed in later LLVM versions
2371 EVT EltVT = getValueType(RetTy).getVectorElementType();
2372 bool NeedExtend = false;
2373 if (EltVT.getSizeInBits() < 16)
2378 SDValue StoreVal = OutVals[0];
2379 // We only have one element, so just directly store it
2381 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
2382 SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal };
2383 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2384 DAG.getVTList(MVT::Other), Ops,
2385 EltVT, MachinePointerInfo());
2387 } else if (NumElts == 2) {
2389 SDValue StoreVal0 = OutVals[0];
2390 SDValue StoreVal1 = OutVals[1];
2393 StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
2394 StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
2397 SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal0,
2399 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
2400 DAG.getVTList(MVT::Other), Ops,
2401 EltVT, MachinePointerInfo());
2404 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
2405 // vector will be expanded to a power of 2 elements, so we know we can
2406 // always round up to the next multiple of 4 when creating the vector
2408 // e.g. 4 elem => 1 st.v4
2409 // 6 elem => 2 st.v4
2410 // 8 elem => 2 st.v4
2411 // 11 elem => 3 st.v4
2413 unsigned VecSize = 4;
2414 if (OutVals[0].getValueType().getSizeInBits() == 64)
2417 unsigned Offset = 0;
2420 EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2421 unsigned PerStoreOffset =
2422 TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2424 for (unsigned i = 0; i < NumElts; i += VecSize) {
2427 SmallVector<SDValue, 8> Ops;
2428 Ops.push_back(Chain);
2429 Ops.push_back(DAG.getConstant(Offset, dl, MVT::i32));
2430 unsigned Opc = NVPTXISD::StoreRetvalV2;
2431 EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
2433 StoreVal = OutVals[i];
2435 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2436 Ops.push_back(StoreVal);
2438 if (i + 1 < NumElts) {
2439 StoreVal = OutVals[i + 1];
2441 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2443 StoreVal = DAG.getUNDEF(ExtendedVT);
2445 Ops.push_back(StoreVal);
2448 Opc = NVPTXISD::StoreRetvalV4;
2449 if (i + 2 < NumElts) {
2450 StoreVal = OutVals[i + 2];
2453 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2455 StoreVal = DAG.getUNDEF(ExtendedVT);
2457 Ops.push_back(StoreVal);
2459 if (i + 3 < NumElts) {
2460 StoreVal = OutVals[i + 3];
2463 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2465 StoreVal = DAG.getUNDEF(ExtendedVT);
2467 Ops.push_back(StoreVal);
2470 // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
2472 DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
2473 EltVT, MachinePointerInfo());
2474 Offset += PerStoreOffset;
2478 SmallVector<EVT, 16> ValVTs;
2479 SmallVector<uint64_t, 16> Offsets;
2480 ComputePTXValueVTs(*this, RetTy, ValVTs, &Offsets, 0);
2481 assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
2483 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2484 SDValue theVal = OutVals[i];
2485 EVT TheValType = theVal.getValueType();
2486 unsigned numElems = 1;
2487 if (TheValType.isVector())
2488 numElems = TheValType.getVectorNumElements();
2489 for (unsigned j = 0, je = numElems; j != je; ++j) {
2490 SDValue TmpVal = theVal;
2491 if (TheValType.isVector())
2492 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2493 TheValType.getVectorElementType(), TmpVal,
2494 DAG.getIntPtrConstant(j, dl));
2495 EVT TheStoreType = ValVTs[i];
2496 if (RetTy->isIntegerTy() &&
2497 TD->getTypeAllocSizeInBits(RetTy) < 32) {
2498 // The following zero-extension is for integer types only, and
2499 // specifically not for aggregates.
2500 TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
2501 TheStoreType = MVT::i32;
2503 else if (TmpVal.getValueType().getSizeInBits() < 16)
2504 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
2508 DAG.getConstant(Offsets[i], dl, MVT::i32),
2510 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2511 DAG.getVTList(MVT::Other), Ops,
2513 MachinePointerInfo());
2518 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2522 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2523 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2524 SelectionDAG &DAG) const {
2525 if (Constraint.length() > 1)
2528 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2531 // NVPTX suuport vector of legal types of any length in Intrinsics because the
2532 // NVPTX specific type legalizer
2533 // will legalize them to the PTX supported length.
2534 bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
2535 if (isTypeLegal(VT))
2537 if (VT.isVector()) {
2538 MVT eVT = VT.getVectorElementType();
2539 if (isTypeLegal(eVT))
2545 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2546 switch (Intrinsic) {
2550 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2551 return NVPTXISD::Tex1DFloatS32;
2552 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2553 return NVPTXISD::Tex1DFloatFloat;
2554 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2555 return NVPTXISD::Tex1DFloatFloatLevel;
2556 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2557 return NVPTXISD::Tex1DFloatFloatGrad;
2558 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2559 return NVPTXISD::Tex1DS32S32;
2560 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2561 return NVPTXISD::Tex1DS32Float;
2562 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2563 return NVPTXISD::Tex1DS32FloatLevel;
2564 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2565 return NVPTXISD::Tex1DS32FloatGrad;
2566 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2567 return NVPTXISD::Tex1DU32S32;
2568 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2569 return NVPTXISD::Tex1DU32Float;
2570 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2571 return NVPTXISD::Tex1DU32FloatLevel;
2572 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2573 return NVPTXISD::Tex1DU32FloatGrad;
2575 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2576 return NVPTXISD::Tex1DArrayFloatS32;
2577 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2578 return NVPTXISD::Tex1DArrayFloatFloat;
2579 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2580 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2581 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2582 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2583 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2584 return NVPTXISD::Tex1DArrayS32S32;
2585 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2586 return NVPTXISD::Tex1DArrayS32Float;
2587 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2588 return NVPTXISD::Tex1DArrayS32FloatLevel;
2589 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2590 return NVPTXISD::Tex1DArrayS32FloatGrad;
2591 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2592 return NVPTXISD::Tex1DArrayU32S32;
2593 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2594 return NVPTXISD::Tex1DArrayU32Float;
2595 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2596 return NVPTXISD::Tex1DArrayU32FloatLevel;
2597 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2598 return NVPTXISD::Tex1DArrayU32FloatGrad;
2600 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2601 return NVPTXISD::Tex2DFloatS32;
2602 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2603 return NVPTXISD::Tex2DFloatFloat;
2604 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2605 return NVPTXISD::Tex2DFloatFloatLevel;
2606 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2607 return NVPTXISD::Tex2DFloatFloatGrad;
2608 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2609 return NVPTXISD::Tex2DS32S32;
2610 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2611 return NVPTXISD::Tex2DS32Float;
2612 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2613 return NVPTXISD::Tex2DS32FloatLevel;
2614 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2615 return NVPTXISD::Tex2DS32FloatGrad;
2616 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2617 return NVPTXISD::Tex2DU32S32;
2618 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2619 return NVPTXISD::Tex2DU32Float;
2620 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2621 return NVPTXISD::Tex2DU32FloatLevel;
2622 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2623 return NVPTXISD::Tex2DU32FloatGrad;
2625 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2626 return NVPTXISD::Tex2DArrayFloatS32;
2627 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2628 return NVPTXISD::Tex2DArrayFloatFloat;
2629 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2630 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2631 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2632 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2633 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2634 return NVPTXISD::Tex2DArrayS32S32;
2635 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2636 return NVPTXISD::Tex2DArrayS32Float;
2637 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2638 return NVPTXISD::Tex2DArrayS32FloatLevel;
2639 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2640 return NVPTXISD::Tex2DArrayS32FloatGrad;
2641 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2642 return NVPTXISD::Tex2DArrayU32S32;
2643 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2644 return NVPTXISD::Tex2DArrayU32Float;
2645 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2646 return NVPTXISD::Tex2DArrayU32FloatLevel;
2647 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2648 return NVPTXISD::Tex2DArrayU32FloatGrad;
2650 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2651 return NVPTXISD::Tex3DFloatS32;
2652 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2653 return NVPTXISD::Tex3DFloatFloat;
2654 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2655 return NVPTXISD::Tex3DFloatFloatLevel;
2656 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2657 return NVPTXISD::Tex3DFloatFloatGrad;
2658 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2659 return NVPTXISD::Tex3DS32S32;
2660 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2661 return NVPTXISD::Tex3DS32Float;
2662 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2663 return NVPTXISD::Tex3DS32FloatLevel;
2664 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2665 return NVPTXISD::Tex3DS32FloatGrad;
2666 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2667 return NVPTXISD::Tex3DU32S32;
2668 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2669 return NVPTXISD::Tex3DU32Float;
2670 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2671 return NVPTXISD::Tex3DU32FloatLevel;
2672 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2673 return NVPTXISD::Tex3DU32FloatGrad;
2675 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2676 return NVPTXISD::TexCubeFloatFloat;
2677 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2678 return NVPTXISD::TexCubeFloatFloatLevel;
2679 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2680 return NVPTXISD::TexCubeS32Float;
2681 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2682 return NVPTXISD::TexCubeS32FloatLevel;
2683 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2684 return NVPTXISD::TexCubeU32Float;
2685 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2686 return NVPTXISD::TexCubeU32FloatLevel;
2688 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2689 return NVPTXISD::TexCubeArrayFloatFloat;
2690 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2691 return NVPTXISD::TexCubeArrayFloatFloatLevel;
2692 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2693 return NVPTXISD::TexCubeArrayS32Float;
2694 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2695 return NVPTXISD::TexCubeArrayS32FloatLevel;
2696 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2697 return NVPTXISD::TexCubeArrayU32Float;
2698 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2699 return NVPTXISD::TexCubeArrayU32FloatLevel;
2701 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2702 return NVPTXISD::Tld4R2DFloatFloat;
2703 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2704 return NVPTXISD::Tld4G2DFloatFloat;
2705 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2706 return NVPTXISD::Tld4B2DFloatFloat;
2707 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2708 return NVPTXISD::Tld4A2DFloatFloat;
2709 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2710 return NVPTXISD::Tld4R2DS64Float;
2711 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2712 return NVPTXISD::Tld4G2DS64Float;
2713 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2714 return NVPTXISD::Tld4B2DS64Float;
2715 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2716 return NVPTXISD::Tld4A2DS64Float;
2717 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2718 return NVPTXISD::Tld4R2DU64Float;
2719 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2720 return NVPTXISD::Tld4G2DU64Float;
2721 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2722 return NVPTXISD::Tld4B2DU64Float;
2723 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2724 return NVPTXISD::Tld4A2DU64Float;
2726 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2727 return NVPTXISD::TexUnified1DFloatS32;
2728 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2729 return NVPTXISD::TexUnified1DFloatFloat;
2730 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2731 return NVPTXISD::TexUnified1DFloatFloatLevel;
2732 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2733 return NVPTXISD::TexUnified1DFloatFloatGrad;
2734 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2735 return NVPTXISD::TexUnified1DS32S32;
2736 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2737 return NVPTXISD::TexUnified1DS32Float;
2738 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2739 return NVPTXISD::TexUnified1DS32FloatLevel;
2740 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2741 return NVPTXISD::TexUnified1DS32FloatGrad;
2742 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2743 return NVPTXISD::TexUnified1DU32S32;
2744 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2745 return NVPTXISD::TexUnified1DU32Float;
2746 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2747 return NVPTXISD::TexUnified1DU32FloatLevel;
2748 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2749 return NVPTXISD::TexUnified1DU32FloatGrad;
2751 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2752 return NVPTXISD::TexUnified1DArrayFloatS32;
2753 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2754 return NVPTXISD::TexUnified1DArrayFloatFloat;
2755 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2756 return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
2757 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2758 return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
2759 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2760 return NVPTXISD::TexUnified1DArrayS32S32;
2761 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2762 return NVPTXISD::TexUnified1DArrayS32Float;
2763 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2764 return NVPTXISD::TexUnified1DArrayS32FloatLevel;
2765 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2766 return NVPTXISD::TexUnified1DArrayS32FloatGrad;
2767 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2768 return NVPTXISD::TexUnified1DArrayU32S32;
2769 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2770 return NVPTXISD::TexUnified1DArrayU32Float;
2771 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2772 return NVPTXISD::TexUnified1DArrayU32FloatLevel;
2773 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2774 return NVPTXISD::TexUnified1DArrayU32FloatGrad;
2776 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2777 return NVPTXISD::TexUnified2DFloatS32;
2778 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2779 return NVPTXISD::TexUnified2DFloatFloat;
2780 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2781 return NVPTXISD::TexUnified2DFloatFloatLevel;
2782 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2783 return NVPTXISD::TexUnified2DFloatFloatGrad;
2784 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2785 return NVPTXISD::TexUnified2DS32S32;
2786 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2787 return NVPTXISD::TexUnified2DS32Float;
2788 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2789 return NVPTXISD::TexUnified2DS32FloatLevel;
2790 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2791 return NVPTXISD::TexUnified2DS32FloatGrad;
2792 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2793 return NVPTXISD::TexUnified2DU32S32;
2794 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2795 return NVPTXISD::TexUnified2DU32Float;
2796 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2797 return NVPTXISD::TexUnified2DU32FloatLevel;
2798 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2799 return NVPTXISD::TexUnified2DU32FloatGrad;
2801 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2802 return NVPTXISD::TexUnified2DArrayFloatS32;
2803 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2804 return NVPTXISD::TexUnified2DArrayFloatFloat;
2805 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2806 return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
2807 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2808 return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
2809 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2810 return NVPTXISD::TexUnified2DArrayS32S32;
2811 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2812 return NVPTXISD::TexUnified2DArrayS32Float;
2813 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2814 return NVPTXISD::TexUnified2DArrayS32FloatLevel;
2815 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2816 return NVPTXISD::TexUnified2DArrayS32FloatGrad;
2817 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2818 return NVPTXISD::TexUnified2DArrayU32S32;
2819 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2820 return NVPTXISD::TexUnified2DArrayU32Float;
2821 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2822 return NVPTXISD::TexUnified2DArrayU32FloatLevel;
2823 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2824 return NVPTXISD::TexUnified2DArrayU32FloatGrad;
2826 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2827 return NVPTXISD::TexUnified3DFloatS32;
2828 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2829 return NVPTXISD::TexUnified3DFloatFloat;
2830 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2831 return NVPTXISD::TexUnified3DFloatFloatLevel;
2832 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2833 return NVPTXISD::TexUnified3DFloatFloatGrad;
2834 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2835 return NVPTXISD::TexUnified3DS32S32;
2836 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2837 return NVPTXISD::TexUnified3DS32Float;
2838 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2839 return NVPTXISD::TexUnified3DS32FloatLevel;
2840 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2841 return NVPTXISD::TexUnified3DS32FloatGrad;
2842 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2843 return NVPTXISD::TexUnified3DU32S32;
2844 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2845 return NVPTXISD::TexUnified3DU32Float;
2846 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2847 return NVPTXISD::TexUnified3DU32FloatLevel;
2848 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2849 return NVPTXISD::TexUnified3DU32FloatGrad;
2851 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2852 return NVPTXISD::TexUnifiedCubeFloatFloat;
2853 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2854 return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
2855 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2856 return NVPTXISD::TexUnifiedCubeS32Float;
2857 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2858 return NVPTXISD::TexUnifiedCubeS32FloatLevel;
2859 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2860 return NVPTXISD::TexUnifiedCubeU32Float;
2861 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2862 return NVPTXISD::TexUnifiedCubeU32FloatLevel;
2864 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2865 return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
2866 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2867 return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
2868 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2869 return NVPTXISD::TexUnifiedCubeArrayS32Float;
2870 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2871 return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
2872 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2873 return NVPTXISD::TexUnifiedCubeArrayU32Float;
2874 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2875 return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
2877 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2878 return NVPTXISD::Tld4UnifiedR2DFloatFloat;
2879 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2880 return NVPTXISD::Tld4UnifiedG2DFloatFloat;
2881 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2882 return NVPTXISD::Tld4UnifiedB2DFloatFloat;
2883 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2884 return NVPTXISD::Tld4UnifiedA2DFloatFloat;
2885 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2886 return NVPTXISD::Tld4UnifiedR2DS64Float;
2887 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2888 return NVPTXISD::Tld4UnifiedG2DS64Float;
2889 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2890 return NVPTXISD::Tld4UnifiedB2DS64Float;
2891 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2892 return NVPTXISD::Tld4UnifiedA2DS64Float;
2893 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2894 return NVPTXISD::Tld4UnifiedR2DU64Float;
2895 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2896 return NVPTXISD::Tld4UnifiedG2DU64Float;
2897 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2898 return NVPTXISD::Tld4UnifiedB2DU64Float;
2899 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2900 return NVPTXISD::Tld4UnifiedA2DU64Float;
2904 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2905 switch (Intrinsic) {
2908 case Intrinsic::nvvm_suld_1d_i8_clamp:
2909 return NVPTXISD::Suld1DI8Clamp;
2910 case Intrinsic::nvvm_suld_1d_i16_clamp:
2911 return NVPTXISD::Suld1DI16Clamp;
2912 case Intrinsic::nvvm_suld_1d_i32_clamp:
2913 return NVPTXISD::Suld1DI32Clamp;
2914 case Intrinsic::nvvm_suld_1d_i64_clamp:
2915 return NVPTXISD::Suld1DI64Clamp;
2916 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2917 return NVPTXISD::Suld1DV2I8Clamp;
2918 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2919 return NVPTXISD::Suld1DV2I16Clamp;
2920 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2921 return NVPTXISD::Suld1DV2I32Clamp;
2922 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2923 return NVPTXISD::Suld1DV2I64Clamp;
2924 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2925 return NVPTXISD::Suld1DV4I8Clamp;
2926 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2927 return NVPTXISD::Suld1DV4I16Clamp;
2928 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2929 return NVPTXISD::Suld1DV4I32Clamp;
2930 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2931 return NVPTXISD::Suld1DArrayI8Clamp;
2932 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2933 return NVPTXISD::Suld1DArrayI16Clamp;
2934 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2935 return NVPTXISD::Suld1DArrayI32Clamp;
2936 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
2937 return NVPTXISD::Suld1DArrayI64Clamp;
2938 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
2939 return NVPTXISD::Suld1DArrayV2I8Clamp;
2940 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
2941 return NVPTXISD::Suld1DArrayV2I16Clamp;
2942 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
2943 return NVPTXISD::Suld1DArrayV2I32Clamp;
2944 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
2945 return NVPTXISD::Suld1DArrayV2I64Clamp;
2946 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
2947 return NVPTXISD::Suld1DArrayV4I8Clamp;
2948 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
2949 return NVPTXISD::Suld1DArrayV4I16Clamp;
2950 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
2951 return NVPTXISD::Suld1DArrayV4I32Clamp;
2952 case Intrinsic::nvvm_suld_2d_i8_clamp:
2953 return NVPTXISD::Suld2DI8Clamp;
2954 case Intrinsic::nvvm_suld_2d_i16_clamp:
2955 return NVPTXISD::Suld2DI16Clamp;
2956 case Intrinsic::nvvm_suld_2d_i32_clamp:
2957 return NVPTXISD::Suld2DI32Clamp;
2958 case Intrinsic::nvvm_suld_2d_i64_clamp:
2959 return NVPTXISD::Suld2DI64Clamp;
2960 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
2961 return NVPTXISD::Suld2DV2I8Clamp;
2962 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
2963 return NVPTXISD::Suld2DV2I16Clamp;
2964 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
2965 return NVPTXISD::Suld2DV2I32Clamp;
2966 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
2967 return NVPTXISD::Suld2DV2I64Clamp;
2968 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
2969 return NVPTXISD::Suld2DV4I8Clamp;
2970 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
2971 return NVPTXISD::Suld2DV4I16Clamp;
2972 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
2973 return NVPTXISD::Suld2DV4I32Clamp;
2974 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
2975 return NVPTXISD::Suld2DArrayI8Clamp;
2976 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
2977 return NVPTXISD::Suld2DArrayI16Clamp;
2978 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
2979 return NVPTXISD::Suld2DArrayI32Clamp;
2980 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
2981 return NVPTXISD::Suld2DArrayI64Clamp;
2982 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
2983 return NVPTXISD::Suld2DArrayV2I8Clamp;
2984 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
2985 return NVPTXISD::Suld2DArrayV2I16Clamp;
2986 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
2987 return NVPTXISD::Suld2DArrayV2I32Clamp;
2988 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
2989 return NVPTXISD::Suld2DArrayV2I64Clamp;
2990 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
2991 return NVPTXISD::Suld2DArrayV4I8Clamp;
2992 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
2993 return NVPTXISD::Suld2DArrayV4I16Clamp;
2994 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
2995 return NVPTXISD::Suld2DArrayV4I32Clamp;
2996 case Intrinsic::nvvm_suld_3d_i8_clamp:
2997 return NVPTXISD::Suld3DI8Clamp;
2998 case Intrinsic::nvvm_suld_3d_i16_clamp:
2999 return NVPTXISD::Suld3DI16Clamp;
3000 case Intrinsic::nvvm_suld_3d_i32_clamp:
3001 return NVPTXISD::Suld3DI32Clamp;
3002 case Intrinsic::nvvm_suld_3d_i64_clamp:
3003 return NVPTXISD::Suld3DI64Clamp;
3004 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3005 return NVPTXISD::Suld3DV2I8Clamp;
3006 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3007 return NVPTXISD::Suld3DV2I16Clamp;
3008 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3009 return NVPTXISD::Suld3DV2I32Clamp;
3010 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3011 return NVPTXISD::Suld3DV2I64Clamp;
3012 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3013 return NVPTXISD::Suld3DV4I8Clamp;
3014 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3015 return NVPTXISD::Suld3DV4I16Clamp;
3016 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3017 return NVPTXISD::Suld3DV4I32Clamp;
3018 case Intrinsic::nvvm_suld_1d_i8_trap:
3019 return NVPTXISD::Suld1DI8Trap;
3020 case Intrinsic::nvvm_suld_1d_i16_trap:
3021 return NVPTXISD::Suld1DI16Trap;
3022 case Intrinsic::nvvm_suld_1d_i32_trap:
3023 return NVPTXISD::Suld1DI32Trap;
3024 case Intrinsic::nvvm_suld_1d_i64_trap:
3025 return NVPTXISD::Suld1DI64Trap;
3026 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3027 return NVPTXISD::Suld1DV2I8Trap;
3028 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3029 return NVPTXISD::Suld1DV2I16Trap;
3030 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3031 return NVPTXISD::Suld1DV2I32Trap;
3032 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3033 return NVPTXISD::Suld1DV2I64Trap;
3034 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3035 return NVPTXISD::Suld1DV4I8Trap;
3036 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3037 return NVPTXISD::Suld1DV4I16Trap;
3038 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3039 return NVPTXISD::Suld1DV4I32Trap;
3040 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3041 return NVPTXISD::Suld1DArrayI8Trap;
3042 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3043 return NVPTXISD::Suld1DArrayI16Trap;
3044 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3045 return NVPTXISD::Suld1DArrayI32Trap;
3046 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3047 return NVPTXISD::Suld1DArrayI64Trap;
3048 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3049 return NVPTXISD::Suld1DArrayV2I8Trap;
3050 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3051 return NVPTXISD::Suld1DArrayV2I16Trap;
3052 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3053 return NVPTXISD::Suld1DArrayV2I32Trap;
3054 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3055 return NVPTXISD::Suld1DArrayV2I64Trap;
3056 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3057 return NVPTXISD::Suld1DArrayV4I8Trap;
3058 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3059 return NVPTXISD::Suld1DArrayV4I16Trap;
3060 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3061 return NVPTXISD::Suld1DArrayV4I32Trap;
3062 case Intrinsic::nvvm_suld_2d_i8_trap:
3063 return NVPTXISD::Suld2DI8Trap;
3064 case Intrinsic::nvvm_suld_2d_i16_trap:
3065 return NVPTXISD::Suld2DI16Trap;
3066 case Intrinsic::nvvm_suld_2d_i32_trap:
3067 return NVPTXISD::Suld2DI32Trap;
3068 case Intrinsic::nvvm_suld_2d_i64_trap:
3069 return NVPTXISD::Suld2DI64Trap;
3070 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3071 return NVPTXISD::Suld2DV2I8Trap;
3072 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3073 return NVPTXISD::Suld2DV2I16Trap;
3074 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3075 return NVPTXISD::Suld2DV2I32Trap;
3076 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3077 return NVPTXISD::Suld2DV2I64Trap;
3078 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3079 return NVPTXISD::Suld2DV4I8Trap;
3080 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3081 return NVPTXISD::Suld2DV4I16Trap;
3082 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3083 return NVPTXISD::Suld2DV4I32Trap;
3084 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3085 return NVPTXISD::Suld2DArrayI8Trap;
3086 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3087 return NVPTXISD::Suld2DArrayI16Trap;
3088 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3089 return NVPTXISD::Suld2DArrayI32Trap;
3090 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3091 return NVPTXISD::Suld2DArrayI64Trap;
3092 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3093 return NVPTXISD::Suld2DArrayV2I8Trap;
3094 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3095 return NVPTXISD::Suld2DArrayV2I16Trap;
3096 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3097 return NVPTXISD::Suld2DArrayV2I32Trap;
3098 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3099 return NVPTXISD::Suld2DArrayV2I64Trap;
3100 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3101 return NVPTXISD::Suld2DArrayV4I8Trap;
3102 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3103 return NVPTXISD::Suld2DArrayV4I16Trap;
3104 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3105 return NVPTXISD::Suld2DArrayV4I32Trap;
3106 case Intrinsic::nvvm_suld_3d_i8_trap:
3107 return NVPTXISD::Suld3DI8Trap;
3108 case Intrinsic::nvvm_suld_3d_i16_trap:
3109 return NVPTXISD::Suld3DI16Trap;
3110 case Intrinsic::nvvm_suld_3d_i32_trap:
3111 return NVPTXISD::Suld3DI32Trap;
3112 case Intrinsic::nvvm_suld_3d_i64_trap:
3113 return NVPTXISD::Suld3DI64Trap;
3114 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3115 return NVPTXISD::Suld3DV2I8Trap;
3116 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3117 return NVPTXISD::Suld3DV2I16Trap;
3118 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3119 return NVPTXISD::Suld3DV2I32Trap;
3120 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3121 return NVPTXISD::Suld3DV2I64Trap;
3122 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3123 return NVPTXISD::Suld3DV4I8Trap;
3124 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3125 return NVPTXISD::Suld3DV4I16Trap;
3126 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3127 return NVPTXISD::Suld3DV4I32Trap;
3128 case Intrinsic::nvvm_suld_1d_i8_zero:
3129 return NVPTXISD::Suld1DI8Zero;
3130 case Intrinsic::nvvm_suld_1d_i16_zero:
3131 return NVPTXISD::Suld1DI16Zero;
3132 case Intrinsic::nvvm_suld_1d_i32_zero:
3133 return NVPTXISD::Suld1DI32Zero;
3134 case Intrinsic::nvvm_suld_1d_i64_zero:
3135 return NVPTXISD::Suld1DI64Zero;
3136 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3137 return NVPTXISD::Suld1DV2I8Zero;
3138 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3139 return NVPTXISD::Suld1DV2I16Zero;
3140 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3141 return NVPTXISD::Suld1DV2I32Zero;
3142 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3143 return NVPTXISD::Suld1DV2I64Zero;
3144 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3145 return NVPTXISD::Suld1DV4I8Zero;
3146 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3147 return NVPTXISD::Suld1DV4I16Zero;
3148 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3149 return NVPTXISD::Suld1DV4I32Zero;
3150 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3151 return NVPTXISD::Suld1DArrayI8Zero;
3152 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3153 return NVPTXISD::Suld1DArrayI16Zero;
3154 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3155 return NVPTXISD::Suld1DArrayI32Zero;
3156 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3157 return NVPTXISD::Suld1DArrayI64Zero;
3158 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3159 return NVPTXISD::Suld1DArrayV2I8Zero;
3160 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3161 return NVPTXISD::Suld1DArrayV2I16Zero;
3162 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3163 return NVPTXISD::Suld1DArrayV2I32Zero;
3164 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3165 return NVPTXISD::Suld1DArrayV2I64Zero;
3166 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3167 return NVPTXISD::Suld1DArrayV4I8Zero;
3168 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3169 return NVPTXISD::Suld1DArrayV4I16Zero;
3170 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3171 return NVPTXISD::Suld1DArrayV4I32Zero;
3172 case Intrinsic::nvvm_suld_2d_i8_zero:
3173 return NVPTXISD::Suld2DI8Zero;
3174 case Intrinsic::nvvm_suld_2d_i16_zero:
3175 return NVPTXISD::Suld2DI16Zero;
3176 case Intrinsic::nvvm_suld_2d_i32_zero:
3177 return NVPTXISD::Suld2DI32Zero;
3178 case Intrinsic::nvvm_suld_2d_i64_zero:
3179 return NVPTXISD::Suld2DI64Zero;
3180 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3181 return NVPTXISD::Suld2DV2I8Zero;
3182 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3183 return NVPTXISD::Suld2DV2I16Zero;
3184 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3185 return NVPTXISD::Suld2DV2I32Zero;
3186 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3187 return NVPTXISD::Suld2DV2I64Zero;
3188 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3189 return NVPTXISD::Suld2DV4I8Zero;
3190 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3191 return NVPTXISD::Suld2DV4I16Zero;
3192 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3193 return NVPTXISD::Suld2DV4I32Zero;
3194 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3195 return NVPTXISD::Suld2DArrayI8Zero;
3196 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3197 return NVPTXISD::Suld2DArrayI16Zero;
3198 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3199 return NVPTXISD::Suld2DArrayI32Zero;
3200 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3201 return NVPTXISD::Suld2DArrayI64Zero;
3202 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3203 return NVPTXISD::Suld2DArrayV2I8Zero;
3204 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3205 return NVPTXISD::Suld2DArrayV2I16Zero;
3206 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3207 return NVPTXISD::Suld2DArrayV2I32Zero;
3208 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3209 return NVPTXISD::Suld2DArrayV2I64Zero;
3210 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3211 return NVPTXISD::Suld2DArrayV4I8Zero;
3212 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3213 return NVPTXISD::Suld2DArrayV4I16Zero;
3214 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3215 return NVPTXISD::Suld2DArrayV4I32Zero;
3216 case Intrinsic::nvvm_suld_3d_i8_zero:
3217 return NVPTXISD::Suld3DI8Zero;
3218 case Intrinsic::nvvm_suld_3d_i16_zero:
3219 return NVPTXISD::Suld3DI16Zero;
3220 case Intrinsic::nvvm_suld_3d_i32_zero:
3221 return NVPTXISD::Suld3DI32Zero;
3222 case Intrinsic::nvvm_suld_3d_i64_zero:
3223 return NVPTXISD::Suld3DI64Zero;
3224 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3225 return NVPTXISD::Suld3DV2I8Zero;
3226 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3227 return NVPTXISD::Suld3DV2I16Zero;
3228 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3229 return NVPTXISD::Suld3DV2I32Zero;
3230 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3231 return NVPTXISD::Suld3DV2I64Zero;
3232 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3233 return NVPTXISD::Suld3DV4I8Zero;
3234 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3235 return NVPTXISD::Suld3DV4I16Zero;
3236 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3237 return NVPTXISD::Suld3DV4I32Zero;
3241 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
3243 // because we need the information that is only available in the "Value" type
3245 // pointer. In particular, the address space information.
3246 bool NVPTXTargetLowering::getTgtMemIntrinsic(
3247 IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
3248 switch (Intrinsic) {
3252 case Intrinsic::nvvm_atomic_load_add_f32:
3253 Info.opc = ISD::INTRINSIC_W_CHAIN;
3254 Info.memVT = MVT::f32;
3255 Info.ptrVal = I.getArgOperand(0);
3258 Info.readMem = true;
3259 Info.writeMem = true;
3263 case Intrinsic::nvvm_atomic_load_inc_32:
3264 case Intrinsic::nvvm_atomic_load_dec_32:
3265 Info.opc = ISD::INTRINSIC_W_CHAIN;
3266 Info.memVT = MVT::i32;
3267 Info.ptrVal = I.getArgOperand(0);
3270 Info.readMem = true;
3271 Info.writeMem = true;
3275 case Intrinsic::nvvm_ldu_global_i:
3276 case Intrinsic::nvvm_ldu_global_f:
3277 case Intrinsic::nvvm_ldu_global_p: {
3279 Info.opc = ISD::INTRINSIC_W_CHAIN;
3280 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3281 Info.memVT = getValueType(I.getType());
3282 else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3283 Info.memVT = getPointerTy();
3285 Info.memVT = getValueType(I.getType());
3286 Info.ptrVal = I.getArgOperand(0);
3289 Info.readMem = true;
3290 Info.writeMem = false;
3291 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3295 case Intrinsic::nvvm_ldg_global_i:
3296 case Intrinsic::nvvm_ldg_global_f:
3297 case Intrinsic::nvvm_ldg_global_p: {
3299 Info.opc = ISD::INTRINSIC_W_CHAIN;
3300 if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3301 Info.memVT = getValueType(I.getType());
3302 else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3303 Info.memVT = getPointerTy();
3305 Info.memVT = getValueType(I.getType());
3306 Info.ptrVal = I.getArgOperand(0);
3309 Info.readMem = true;
3310 Info.writeMem = false;
3311 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3316 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3317 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3318 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3319 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3320 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3321 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3322 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3323 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3324 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3325 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3326 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3327 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3328 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3329 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3330 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3331 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3332 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3333 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3334 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3335 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3336 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3337 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3338 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3339 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3340 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3341 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3342 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3343 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3344 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3345 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3346 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3347 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3348 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3349 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3350 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3351 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3352 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3353 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3354 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3355 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3356 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3357 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3358 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3359 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3360 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3361 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3362 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3363 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3364 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3365 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3366 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3367 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3368 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3369 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3370 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3371 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
3372 Info.opc = getOpcForTextureInstr(Intrinsic);
3373 Info.memVT = MVT::v4f32;
3374 Info.ptrVal = nullptr;
3377 Info.readMem = true;
3378 Info.writeMem = false;
3382 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3383 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3384 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3385 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3386 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3387 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3388 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3389 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3390 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3391 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3392 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3393 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3394 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3395 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3396 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3397 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3398 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3399 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3400 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3401 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3402 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3403 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3404 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3405 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3406 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3407 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3408 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3409 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3410 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3411 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3412 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3413 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3414 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3415 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3416 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3417 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3418 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3419 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3420 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3421 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3422 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3423 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3424 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3425 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3426 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3427 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3428 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3429 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3430 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3431 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3432 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3433 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3434 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3435 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3436 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3437 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3438 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3439 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3440 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3441 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3442 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3443 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3444 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3445 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3446 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3447 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3448 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3449 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3450 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3451 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3452 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3453 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3454 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3455 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3456 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3457 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3458 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3459 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3460 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3461 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3462 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3463 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3464 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3465 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3466 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3467 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3468 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3469 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3470 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3471 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3472 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3473 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3474 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3475 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3476 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3477 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3478 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3479 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3480 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3481 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3482 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3483 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3484 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3485 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3486 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3487 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3488 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3489 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3490 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3491 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3492 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3493 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
3494 Info.opc = getOpcForTextureInstr(Intrinsic);
3495 Info.memVT = MVT::v4i32;
3496 Info.ptrVal = nullptr;
3499 Info.readMem = true;
3500 Info.writeMem = false;
3504 case Intrinsic::nvvm_suld_1d_i8_clamp:
3505 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3506 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3507 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3508 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3509 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3510 case Intrinsic::nvvm_suld_2d_i8_clamp:
3511 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3512 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3513 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3514 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3515 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3516 case Intrinsic::nvvm_suld_3d_i8_clamp:
3517 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3518 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3519 case Intrinsic::nvvm_suld_1d_i8_trap:
3520 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3521 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3522 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3523 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3524 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3525 case Intrinsic::nvvm_suld_2d_i8_trap:
3526 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3527 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3528 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3529 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3530 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3531 case Intrinsic::nvvm_suld_3d_i8_trap:
3532 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3533 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3534 case Intrinsic::nvvm_suld_1d_i8_zero:
3535 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3536 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3537 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3538 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3539 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3540 case Intrinsic::nvvm_suld_2d_i8_zero:
3541 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3542 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3543 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3544 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3545 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3546 case Intrinsic::nvvm_suld_3d_i8_zero:
3547 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3548 case Intrinsic::nvvm_suld_3d_v4i8_zero: {
3549 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3550 Info.memVT = MVT::i8;
3551 Info.ptrVal = nullptr;
3554 Info.readMem = true;
3555 Info.writeMem = false;
3559 case Intrinsic::nvvm_suld_1d_i16_clamp:
3560 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3561 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3562 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3563 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3564 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3565 case Intrinsic::nvvm_suld_2d_i16_clamp:
3566 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3567 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3568 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3569 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3570 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3571 case Intrinsic::nvvm_suld_3d_i16_clamp:
3572 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3573 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3574 case Intrinsic::nvvm_suld_1d_i16_trap:
3575 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3576 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3577 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3578 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3579 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3580 case Intrinsic::nvvm_suld_2d_i16_trap:
3581 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3582 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3583 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3584 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3585 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3586 case Intrinsic::nvvm_suld_3d_i16_trap:
3587 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3588 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3589 case Intrinsic::nvvm_suld_1d_i16_zero:
3590 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3591 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3592 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3593 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3594 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3595 case Intrinsic::nvvm_suld_2d_i16_zero:
3596 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3597 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3598 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3599 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3600 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3601 case Intrinsic::nvvm_suld_3d_i16_zero:
3602 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3603 case Intrinsic::nvvm_suld_3d_v4i16_zero: {
3604 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3605 Info.memVT = MVT::i16;
3606 Info.ptrVal = nullptr;
3609 Info.readMem = true;
3610 Info.writeMem = false;
3614 case Intrinsic::nvvm_suld_1d_i32_clamp:
3615 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3616 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3617 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3618 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3619 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3620 case Intrinsic::nvvm_suld_2d_i32_clamp:
3621 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3622 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3623 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3624 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3625 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3626 case Intrinsic::nvvm_suld_3d_i32_clamp:
3627 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3628 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3629 case Intrinsic::nvvm_suld_1d_i32_trap:
3630 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3631 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3632 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3633 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3634 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3635 case Intrinsic::nvvm_suld_2d_i32_trap:
3636 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3637 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3638 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3639 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3640 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3641 case Intrinsic::nvvm_suld_3d_i32_trap:
3642 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3643 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3644 case Intrinsic::nvvm_suld_1d_i32_zero:
3645 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3646 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3647 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3648 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3649 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3650 case Intrinsic::nvvm_suld_2d_i32_zero:
3651 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3652 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3653 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3654 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3655 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3656 case Intrinsic::nvvm_suld_3d_i32_zero:
3657 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3658 case Intrinsic::nvvm_suld_3d_v4i32_zero: {
3659 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3660 Info.memVT = MVT::i32;
3661 Info.ptrVal = nullptr;
3664 Info.readMem = true;
3665 Info.writeMem = false;
3669 case Intrinsic::nvvm_suld_1d_i64_clamp:
3670 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3671 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3672 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3673 case Intrinsic::nvvm_suld_2d_i64_clamp:
3674 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3675 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3676 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3677 case Intrinsic::nvvm_suld_3d_i64_clamp:
3678 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3679 case Intrinsic::nvvm_suld_1d_i64_trap:
3680 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3681 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3682 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3683 case Intrinsic::nvvm_suld_2d_i64_trap:
3684 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3685 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3686 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3687 case Intrinsic::nvvm_suld_3d_i64_trap:
3688 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3689 case Intrinsic::nvvm_suld_1d_i64_zero:
3690 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3691 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3692 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3693 case Intrinsic::nvvm_suld_2d_i64_zero:
3694 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3695 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3696 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3697 case Intrinsic::nvvm_suld_3d_i64_zero:
3698 case Intrinsic::nvvm_suld_3d_v2i64_zero: {
3699 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3700 Info.memVT = MVT::i64;
3701 Info.ptrVal = nullptr;
3704 Info.readMem = true;
3705 Info.writeMem = false;
3713 /// isLegalAddressingMode - Return true if the addressing mode represented
3714 /// by AM is legal for this target, for a load/store of the specified type.
3715 /// Used to guide target specific optimizations, like loop strength reduction
3716 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
3717 /// (CodeGenPrepare.cpp)
3718 bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3721 // AddrMode - This represents an addressing mode of:
3722 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
3724 // The legal address modes are
3731 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
3737 case 0: // "r", "r+i" or "i" is allowed
3740 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
3742 // Otherwise we have r+i.
3745 // No scale > 1 is allowed
3751 //===----------------------------------------------------------------------===//
3752 // NVPTX Inline Assembly Support
3753 //===----------------------------------------------------------------------===//
3755 /// getConstraintType - Given a constraint letter, return the type of
3756 /// constraint it is for this target.
3757 NVPTXTargetLowering::ConstraintType
3758 NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
3759 if (Constraint.size() == 1) {
3760 switch (Constraint[0]) {
3772 return C_RegisterClass;
3775 return TargetLowering::getConstraintType(Constraint);
3778 std::pair<unsigned, const TargetRegisterClass *>
3779 NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3780 const std::string &Constraint,
3782 if (Constraint.size() == 1) {
3783 switch (Constraint[0]) {
3785 return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3787 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3789 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3791 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3794 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3796 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3798 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3801 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3804 /// getFunctionAlignment - Return the Log2 alignment of this function.
3805 unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
3809 //===----------------------------------------------------------------------===//
3810 // NVPTX DAG Combining
3811 //===----------------------------------------------------------------------===//
3813 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
3814 CodeGenOpt::Level OptLevel) const {
3815 const Function *F = MF.getFunction();
3816 const TargetOptions &TO = MF.getTarget().Options;
3818 // Always honor command-line argument
3819 if (FMAContractLevelOpt.getNumOccurrences() > 0) {
3820 return FMAContractLevelOpt > 0;
3821 } else if (OptLevel == 0) {
3822 // Do not contract if we're not optimizing the code
3824 } else if (TO.AllowFPOpFusion == FPOpFusion::Fast || TO.UnsafeFPMath) {
3825 // Honor TargetOptions flags that explicitly say fusion is okay
3827 } else if (F->hasFnAttribute("unsafe-fp-math")) {
3828 // Check for unsafe-fp-math=true coming from Clang
3829 Attribute Attr = F->getFnAttribute("unsafe-fp-math");
3830 StringRef Val = Attr.getValueAsString();
3835 // We did not have a clear indication that fusion is allowed, so assume not
3839 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
3840 /// operands N0 and N1. This is a helper for PerformADDCombine that is
3841 /// called with the default operands, and if that fails, with commuted
3843 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
3844 TargetLowering::DAGCombinerInfo &DCI,
3845 const NVPTXSubtarget &Subtarget,
3846 CodeGenOpt::Level OptLevel) {
3847 SelectionDAG &DAG = DCI.DAG;
3848 // Skip non-integer, non-scalar case
3849 EVT VT=N0.getValueType();
3853 // fold (add (mul a, b), c) -> (mad a, b, c)
3855 if (N0.getOpcode() == ISD::MUL) {
3856 assert (VT.isInteger());
3858 // Since integer multiply-add costs the same as integer multiply
3859 // but is more costly than integer add, do the fusion only when
3860 // the mul is only used in the add.
3861 if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
3862 !N0.getNode()->hasOneUse())
3866 return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
3867 N0.getOperand(0), N0.getOperand(1), N1);
3869 else if (N0.getOpcode() == ISD::FMUL) {
3870 if (VT == MVT::f32 || VT == MVT::f64) {
3871 const auto *TLI = static_cast<const NVPTXTargetLowering *>(
3872 &DAG.getTargetLoweringInfo());
3873 if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
3876 // For floating point:
3877 // Do the fusion only when the mul has less than 5 uses and all
3879 // The heuristic is that if a use is not an add, then that use
3880 // cannot be fused into fma, therefore mul is still needed anyway.
3881 // If there are more than 4 uses, even if they are all add, fusing
3882 // them will increase register pressue.
3885 int nonAddCount = 0;
3886 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3887 UE = N0.getNode()->use_end();
3891 if (User->getOpcode() != ISD::FADD)
3897 int orderNo = N->getIROrder();
3898 int orderNo2 = N0.getNode()->getIROrder();
3899 // simple heuristics here for considering potential register
3900 // pressure, the logics here is that the differnce are used
3901 // to measure the distance between def and use, the longer distance
3902 // more likely cause register pressure.
3903 if (orderNo - orderNo2 < 500)
3906 // Now, check if at least one of the FMUL's operands is live beyond the node N,
3907 // which guarantees that the FMA will not increase register pressure at node N.
3908 bool opIsLive = false;
3909 const SDNode *left = N0.getOperand(0).getNode();
3910 const SDNode *right = N0.getOperand(1).getNode();
3912 if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
3916 for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
3918 int orderNo3 = User->getIROrder();
3919 if (orderNo3 > orderNo) {
3926 for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
3928 int orderNo3 = User->getIROrder();
3929 if (orderNo3 > orderNo) {
3939 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
3940 N0.getOperand(0), N0.getOperand(1), N1);
3947 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3949 static SDValue PerformADDCombine(SDNode *N,
3950 TargetLowering::DAGCombinerInfo &DCI,
3951 const NVPTXSubtarget &Subtarget,
3952 CodeGenOpt::Level OptLevel) {
3953 SDValue N0 = N->getOperand(0);
3954 SDValue N1 = N->getOperand(1);
3956 // First try with the default operand order.
3957 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
3959 if (Result.getNode())
3962 // If that didn't work, try again with the operands commuted.
3963 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
3966 static SDValue PerformANDCombine(SDNode *N,
3967 TargetLowering::DAGCombinerInfo &DCI) {
3968 // The type legalizer turns a vector load of i8 values into a zextload to i16
3969 // registers, optionally ANY_EXTENDs it (if target type is integer),
3970 // and ANDs off the high 8 bits. Since we turn this load into a
3971 // target-specific DAG node, the DAG combiner fails to eliminate these AND
3972 // nodes. Do that here.
3973 SDValue Val = N->getOperand(0);
3974 SDValue Mask = N->getOperand(1);
3976 if (isa<ConstantSDNode>(Val)) {
3977 std::swap(Val, Mask);
3981 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
3982 if (Val.getOpcode() == ISD::ANY_EXTEND) {
3984 Val = Val->getOperand(0);
3987 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
3988 Val = Val->getOperand(0);
3991 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
3992 Val->getOpcode() == NVPTXISD::LoadV4) {
3993 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
3995 // Not an AND with a constant
3999 uint64_t MaskVal = MaskCnst->getZExtValue();
4000 if (MaskVal != 0xff) {
4001 // Not an AND that chops off top 8 bits
4005 MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
4007 // Not a MemSDNode?!?
4011 EVT MemVT = Mem->getMemoryVT();
4012 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4013 // We only handle the i8 case
4018 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4020 if (ExtType == ISD::SEXTLOAD) {
4021 // If for some reason the load is a sextload, the and is needed to zero
4022 // out the high 8 bits
4027 if (AExt.getNode() != 0) {
4028 // Re-insert the ext as a zext.
4029 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4030 AExt.getValueType(), Val);
4034 // If we get here, the AND is unnecessary. Just replace it with the load
4035 DCI.CombineTo(N, Val, AddTo);
4041 enum OperandSignedness {
4047 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
4048 /// that can be demoted to \p OptSize bits without loss of information. The
4049 /// signedness of the operand, if determinable, is placed in \p S.
4050 static bool IsMulWideOperandDemotable(SDValue Op,
4052 OperandSignedness &S) {
4055 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4056 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4057 EVT OrigVT = Op.getOperand(0).getValueType();
4058 if (OrigVT.getSizeInBits() <= OptSize) {
4062 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4063 EVT OrigVT = Op.getOperand(0).getValueType();
4064 if (OrigVT.getSizeInBits() <= OptSize) {
4073 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
4074 /// be demoted to \p OptSize bits without loss of information. If the operands
4075 /// contain a constant, it should appear as the RHS operand. The signedness of
4076 /// the operands is placed in \p IsSigned.
4077 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
4081 OperandSignedness LHSSign;
4083 // The LHS operand must be a demotable op
4084 if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
4087 // We should have been able to determine the signedness from the LHS
4088 if (LHSSign == Unknown)
4091 IsSigned = (LHSSign == Signed);
4093 // The RHS can be a demotable op or a constant
4094 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
4095 APInt Val = CI->getAPIntValue();
4096 if (LHSSign == Unsigned) {
4097 if (Val.isIntN(OptSize)) {
4102 if (Val.isSignedIntN(OptSize)) {
4108 OperandSignedness RHSSign;
4109 if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
4112 if (LHSSign != RHSSign)
4119 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
4120 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
4121 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
4123 static SDValue TryMULWIDECombine(SDNode *N,
4124 TargetLowering::DAGCombinerInfo &DCI) {
4125 EVT MulType = N->getValueType(0);
4126 if (MulType != MVT::i32 && MulType != MVT::i64) {
4131 unsigned OptSize = MulType.getSizeInBits() >> 1;
4132 SDValue LHS = N->getOperand(0);
4133 SDValue RHS = N->getOperand(1);
4135 // Canonicalize the multiply so the constant (if any) is on the right
4136 if (N->getOpcode() == ISD::MUL) {
4137 if (isa<ConstantSDNode>(LHS)) {
4138 std::swap(LHS, RHS);
4142 // If we have a SHL, determine the actual multiply amount
4143 if (N->getOpcode() == ISD::SHL) {
4144 ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
4149 APInt ShiftAmt = ShlRHS->getAPIntValue();
4150 unsigned BitWidth = MulType.getSizeInBits();
4151 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4152 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
4153 RHS = DCI.DAG.getConstant(MulVal, DL, MulType);
4160 // Verify that our operands are demotable
4161 if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
4166 if (MulType == MVT::i32) {
4167 DemotedVT = MVT::i16;
4169 DemotedVT = MVT::i32;
4172 // Truncate the operands to the correct size. Note that these are just for
4173 // type consistency and will (likely) be eliminated in later phases.
4175 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS);
4177 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS);
4181 Opc = NVPTXISD::MUL_WIDE_SIGNED;
4183 Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
4186 return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4189 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
4190 static SDValue PerformMULCombine(SDNode *N,
4191 TargetLowering::DAGCombinerInfo &DCI,
4192 CodeGenOpt::Level OptLevel) {
4194 // Try mul.wide combining at OptLevel > 0
4195 SDValue Ret = TryMULWIDECombine(N, DCI);
4203 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
4204 static SDValue PerformSHLCombine(SDNode *N,
4205 TargetLowering::DAGCombinerInfo &DCI,
4206 CodeGenOpt::Level OptLevel) {
4208 // Try mul.wide combining at OptLevel > 0
4209 SDValue Ret = TryMULWIDECombine(N, DCI);
4217 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
4218 DAGCombinerInfo &DCI) const {
4219 CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
4220 switch (N->getOpcode()) {
4224 return PerformADDCombine(N, DCI, STI, OptLevel);
4226 return PerformMULCombine(N, DCI, OptLevel);
4228 return PerformSHLCombine(N, DCI, OptLevel);
4230 return PerformANDCombine(N, DCI);
4235 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
4236 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
4237 const DataLayout *TD,
4238 SmallVectorImpl<SDValue> &Results) {
4239 EVT ResVT = N->getValueType(0);
4242 assert(ResVT.isVector() && "Vector load must have vector type");
4244 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
4245 // legal. We can (and should) split that into 2 loads of <2 x double> here
4246 // but I'm leaving that as a TODO for now.
4247 assert(ResVT.isSimple() && "Can only handle simple types");
4248 switch (ResVT.getSimpleVT().SimpleTy) {
4261 // This is a "native" vector type
4265 LoadSDNode *LD = cast<LoadSDNode>(N);
4267 unsigned Align = LD->getAlignment();
4268 unsigned PrefAlign =
4269 TD->getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
4270 if (Align < PrefAlign) {
4271 // This load is not sufficiently aligned, so bail out and let this vector
4272 // load be scalarized. Note that we may still be able to emit smaller
4273 // vector loads. For example, if we are loading a <4 x float> with an
4274 // alignment of 8, this check will fail but the legalizer will try again
4275 // with 2 x <2 x float>, which will succeed with an alignment of 8.
4279 EVT EltVT = ResVT.getVectorElementType();
4280 unsigned NumElts = ResVT.getVectorNumElements();
4282 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
4283 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4284 // loaded type to i16 and propagate the "real" type as the memory type.
4285 bool NeedTrunc = false;
4286 if (EltVT.getSizeInBits() < 16) {
4291 unsigned Opcode = 0;
4298 Opcode = NVPTXISD::LoadV2;
4299 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4302 Opcode = NVPTXISD::LoadV4;
4303 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4304 LdResVTs = DAG.getVTList(ListVTs);
4309 // Copy regular operands
4310 SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
4312 // The select routine does not have access to the LoadSDNode instance, so
4313 // pass along the extension information
4314 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));
4316 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4318 LD->getMemOperand());
4320 SmallVector<SDValue, 4> ScalarRes;
4322 for (unsigned i = 0; i < NumElts; ++i) {
4323 SDValue Res = NewLD.getValue(i);
4325 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4326 ScalarRes.push_back(Res);
4329 SDValue LoadChain = NewLD.getValue(NumElts);
4331 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4333 Results.push_back(BuildVec);
4334 Results.push_back(LoadChain);
4337 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
4338 SmallVectorImpl<SDValue> &Results) {
4339 SDValue Chain = N->getOperand(0);
4340 SDValue Intrin = N->getOperand(1);
4343 // Get the intrinsic ID
4344 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
4348 case Intrinsic::nvvm_ldg_global_i:
4349 case Intrinsic::nvvm_ldg_global_f:
4350 case Intrinsic::nvvm_ldg_global_p:
4351 case Intrinsic::nvvm_ldu_global_i:
4352 case Intrinsic::nvvm_ldu_global_f:
4353 case Intrinsic::nvvm_ldu_global_p: {
4354 EVT ResVT = N->getValueType(0);
4356 if (ResVT.isVector()) {
4359 unsigned NumElts = ResVT.getVectorNumElements();
4360 EVT EltVT = ResVT.getVectorElementType();
4362 // Since LDU/LDG are target nodes, we cannot rely on DAG type
4364 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4365 // loaded type to i16 and propagate the "real" type as the memory type.
4366 bool NeedTrunc = false;
4367 if (EltVT.getSizeInBits() < 16) {
4372 unsigned Opcode = 0;
4382 case Intrinsic::nvvm_ldg_global_i:
4383 case Intrinsic::nvvm_ldg_global_f:
4384 case Intrinsic::nvvm_ldg_global_p:
4385 Opcode = NVPTXISD::LDGV2;
4387 case Intrinsic::nvvm_ldu_global_i:
4388 case Intrinsic::nvvm_ldu_global_f:
4389 case Intrinsic::nvvm_ldu_global_p:
4390 Opcode = NVPTXISD::LDUV2;
4393 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4399 case Intrinsic::nvvm_ldg_global_i:
4400 case Intrinsic::nvvm_ldg_global_f:
4401 case Intrinsic::nvvm_ldg_global_p:
4402 Opcode = NVPTXISD::LDGV4;
4404 case Intrinsic::nvvm_ldu_global_i:
4405 case Intrinsic::nvvm_ldu_global_f:
4406 case Intrinsic::nvvm_ldu_global_p:
4407 Opcode = NVPTXISD::LDUV4;
4410 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4411 LdResVTs = DAG.getVTList(ListVTs);
4416 SmallVector<SDValue, 8> OtherOps;
4418 // Copy regular operands
4420 OtherOps.push_back(Chain); // Chain
4421 // Skip operand 1 (intrinsic ID)
4423 OtherOps.append(N->op_begin() + 2, N->op_end());
4425 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4427 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4428 MemSD->getMemoryVT(),
4429 MemSD->getMemOperand());
4431 SmallVector<SDValue, 4> ScalarRes;
4433 for (unsigned i = 0; i < NumElts; ++i) {
4434 SDValue Res = NewLD.getValue(i);
4437 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4438 ScalarRes.push_back(Res);
4441 SDValue LoadChain = NewLD.getValue(NumElts);
4444 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4446 Results.push_back(BuildVec);
4447 Results.push_back(LoadChain);
4450 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
4451 "Custom handling of non-i8 ldu/ldg?");
4453 // Just copy all operands as-is
4454 SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
4456 // Force output to i16
4457 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
4459 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4461 // We make sure the memory type is i8, which will be used during isel
4462 // to select the proper instruction.
4464 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
4465 MVT::i8, MemSD->getMemOperand());
4467 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
4468 NewLD.getValue(0)));
4469 Results.push_back(NewLD.getValue(1));
4475 void NVPTXTargetLowering::ReplaceNodeResults(
4476 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
4477 switch (N->getOpcode()) {
4479 report_fatal_error("Unhandled custom legalization");
4481 ReplaceLoadVector(N, DAG, getDataLayout(), Results);
4483 case ISD::INTRINSIC_W_CHAIN:
4484 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
4489 // Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
4490 void NVPTXSection::anchor() {}
4492 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
4496 delete ReadOnlySection;
4498 delete StaticCtorSection;
4499 delete StaticDtorSection;
4501 delete EHFrameSection;
4502 delete DwarfAbbrevSection;
4503 delete DwarfInfoSection;
4504 delete DwarfLineSection;
4505 delete DwarfFrameSection;
4506 delete DwarfPubTypesSection;
4507 delete DwarfDebugInlineSection;
4508 delete DwarfStrSection;
4509 delete DwarfLocSection;
4510 delete DwarfARangesSection;
4511 delete DwarfRangesSection;
4515 NVPTXTargetObjectFile::SelectSectionForGlobal(const GlobalValue *GV,
4516 SectionKind Kind, Mangler &Mang,
4517 const TargetMachine &TM) const {
4518 return getDataSection();