1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
16 #include "Mips16FrameLowering.h"
17 #include "Mips16HardFloat.h"
18 #include "Mips16ISelDAGToDAG.h"
19 #include "Mips16ISelLowering.h"
20 #include "Mips16InstrInfo.h"
21 #include "MipsFrameLowering.h"
22 #include "MipsInstrInfo.h"
23 #include "MipsModuleISelDAGToDAG.h"
25 #include "MipsSEFrameLowering.h"
26 #include "MipsSEISelDAGToDAG.h"
27 #include "MipsSEISelLowering.h"
28 #include "MipsSEInstrInfo.h"
29 #include "llvm/Analysis/TargetTransformInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/PassManager.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Transforms/Scalar.h"
38 #define DEBUG_TYPE "mips"
40 extern "C" void LLVMInitializeMipsTarget() {
41 // Register the target.
42 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
43 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
44 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
45 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
48 // On function prologue, the stack is created by decrementing
49 // its pointer. Once decremented, all references are done with positive
50 // offset from the stack/frame pointer, using StackGrowsUp enables
51 // an easier handling.
52 // Using CodeModel::Large enables different CALL behavior.
53 MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
54 StringRef CPU, StringRef FS,
55 const TargetOptions &Options,
56 Reloc::Model RM, CodeModel::Model CM,
57 CodeGenOpt::Level OL, bool isLittle)
58 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59 Subtarget(TT, CPU, FS, isLittle, RM, this) {
63 void MipsebTargetMachine::anchor() { }
66 MipsebTargetMachine(const Target &T, StringRef TT,
67 StringRef CPU, StringRef FS, const TargetOptions &Options,
68 Reloc::Model RM, CodeModel::Model CM,
70 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
72 void MipselTargetMachine::anchor() { }
75 MipselTargetMachine(const Target &T, StringRef TT,
76 StringRef CPU, StringRef FS, const TargetOptions &Options,
77 Reloc::Model RM, CodeModel::Model CM,
79 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
82 /// Mips Code Generator Pass Configuration Options.
83 class MipsPassConfig : public TargetPassConfig {
85 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
86 : TargetPassConfig(TM, PM) {
87 // The current implementation of long branch pass requires a scratch
88 // register ($at) to be available before branch instructions. Tail merging
89 // can break this requirement, so disable it when long branch pass is
91 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
94 MipsTargetMachine &getMipsTargetMachine() const {
95 return getTM<MipsTargetMachine>();
98 const MipsSubtarget &getMipsSubtarget() const {
99 return *getMipsTargetMachine().getSubtargetImpl();
102 void addIRPasses() override;
103 bool addInstSelector() override;
104 void addMachineSSAOptimization() override;
105 bool addPreEmitPass() override;
107 bool addPreRegAlloc() override;
112 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
113 return new MipsPassConfig(this, PM);
116 void MipsPassConfig::addIRPasses() {
117 TargetPassConfig::addIRPasses();
118 if (getMipsSubtarget().os16())
119 addPass(createMipsOs16(getMipsTargetMachine()));
120 if (getMipsSubtarget().inMips16HardFloat())
121 addPass(createMips16HardFloat(getMipsTargetMachine()));
122 addPass(createPartiallyInlineLibCallsPass());
124 // Install an instruction selector pass using
125 // the ISelDag to gen Mips code.
126 bool MipsPassConfig::addInstSelector() {
127 if (getMipsSubtarget().allowMixed16_32()) {
128 addPass(createMipsModuleISelDag(getMipsTargetMachine()));
129 addPass(createMips16ISelDag(getMipsTargetMachine()));
130 addPass(createMipsSEISelDag(getMipsTargetMachine()));
132 addPass(createMipsISelDag(getMipsTargetMachine()));
137 void MipsPassConfig::addMachineSSAOptimization() {
138 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
139 TargetPassConfig::addMachineSSAOptimization();
142 bool MipsPassConfig::addPreRegAlloc() {
143 if (getOptLevel() == CodeGenOpt::None) {
144 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
151 void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
152 if (Subtarget.allowMixed16_32()) {
153 DEBUG(errs() << "No ");
154 //FIXME: The Basic Target Transform Info
155 // pass needs to become a function pass instead of
156 // being an immutable pass and then this method as it exists now
157 // would be unnecessary.
158 PM.add(createNoTargetTransformInfoPass());
160 LLVMTargetMachine::addAnalysisPasses(PM);
161 DEBUG(errs() << "Target Transform Info Pass Added\n");
164 // Implemented by targets that want to run passes immediately before
165 // machine code is emitted. return true if -print-machineinstrs should
166 // print out the code after the passes.
167 bool MipsPassConfig::addPreEmitPass() {
168 MipsTargetMachine &TM = getMipsTargetMachine();
169 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
170 addPass(createMipsDelaySlotFillerPass(TM));
172 if (Subtarget.enableLongBranchPass())
173 addPass(createMipsLongBranchPass(TM));
174 if (Subtarget.inMips16Mode() ||
175 Subtarget.allowMixed16_32())
176 addPass(createMipsConstantIslandPass(TM));
181 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
182 JITCodeEmitter &JCE) {
183 // Machine code emitter pass for Mips.
184 PM.add(createMipsJITCodeEmitterPass(*this, JCE));