1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 def MipsERet : SDNode<"MipsISD::ERet", SDTNone,
81 [SDNPHasChain, SDNPOptInGlue, SDNPSideEffect]>;
83 // These are target-independent nodes, but have target-specific formats.
84 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
85 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
86 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
87 [SDNPHasChain, SDNPSideEffect,
88 SDNPOptInGlue, SDNPOutGlue]>;
90 // Nodes used to extract LO/HI registers.
91 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
92 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
94 // Node used to insert 32-bit integers to LOHI register pair.
95 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
98 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
99 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
102 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
103 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
104 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
105 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
108 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
109 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
110 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
112 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
115 // Target constant nodes that are not part of any isel patterns and remain
116 // unchanged can cause instructions with illegal operands to be emitted.
117 // Wrapper node patterns give the instruction selector a chance to replace
118 // target constant nodes that would otherwise remain unchanged with ADDiu
119 // nodes. Without these wrapper node patterns, the following conditional move
120 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
122 // movn %got(d)($gp), %got(c)($gp), $4
123 // This instruction is illegal since movn can take only register operands.
125 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
127 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
129 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
130 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
132 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
135 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
136 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
139 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
140 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
143 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
144 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
147 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
149 //===----------------------------------------------------------------------===//
150 // Mips Instruction Predicate Definitions.
151 //===----------------------------------------------------------------------===//
152 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
153 AssemblerPredicate<"FeatureMips2">;
154 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
155 AssemblerPredicate<"FeatureMips3_32">;
156 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
157 AssemblerPredicate<"FeatureMips3_32r2">;
158 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
159 AssemblerPredicate<"FeatureMips3">;
160 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
161 AssemblerPredicate<"FeatureMips4_32">;
162 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
163 AssemblerPredicate<"!FeatureMips4_32">;
164 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
165 AssemblerPredicate<"FeatureMips4_32r2">;
166 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
167 AssemblerPredicate<"FeatureMips5_32r2">;
168 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
169 AssemblerPredicate<"FeatureMips32">;
170 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
171 AssemblerPredicate<"FeatureMips32r2">;
172 def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">,
173 AssemblerPredicate<"FeatureMips32r5">;
174 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
175 AssemblerPredicate<"FeatureMips32r6">;
176 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
177 AssemblerPredicate<"!FeatureMips32r6">;
178 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
179 AssemblerPredicate<"FeatureGP64Bit">;
180 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
181 AssemblerPredicate<"!FeatureGP64Bit">;
182 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
183 AssemblerPredicate<"FeatureMips64">;
184 def NotMips64 : Predicate<"!Subtarget->hasMips64()">,
185 AssemblerPredicate<"!FeatureMips64">;
186 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
187 AssemblerPredicate<"FeatureMips64r2">;
188 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
189 AssemblerPredicate<"FeatureMips64r6">;
190 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
191 AssemblerPredicate<"!FeatureMips64r6">;
192 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
193 AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
194 def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
195 AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
196 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
197 AssemblerPredicate<"FeatureMips16">;
198 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
199 AssemblerPredicate<"FeatureCnMips">;
200 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
201 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
202 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
203 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
204 AssemblerPredicate<"!FeatureMips16">;
205 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
206 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
207 AssemblerPredicate<"FeatureMicroMips">;
208 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
209 AssemblerPredicate<"!FeatureMicroMips">;
210 def IsLE : Predicate<"Subtarget->isLittle()">;
211 def IsBE : Predicate<"!Subtarget->isLittle()">;
212 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
213 def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
214 def HasEVA : Predicate<"Subtarget->hasEVA()">,
215 AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
216 def HasMSA : Predicate<"Subtarget->hasMSA()">,
217 AssemblerPredicate<"FeatureMSA">;
220 //===----------------------------------------------------------------------===//
221 // Mips GPR size adjectives.
222 // They are mutually exclusive.
223 //===----------------------------------------------------------------------===//
225 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
226 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
228 //===----------------------------------------------------------------------===//
229 // Mips ISA/ASE membership and instruction group membership adjectives.
230 // They are mutually exclusive.
231 //===----------------------------------------------------------------------===//
233 // FIXME: I'd prefer to use additive predicates to build the instruction sets
234 // but we are short on assembler feature bits at the moment. Using a
235 // subtractive predicate will hopefully keep us under the 32 predicate
236 // limit long enough to develop an alternative way to handle P1||P2
238 class ISA_MIPS1_NOT_4_32 {
239 list<Predicate> InsnPredicates = [NotMips4_32];
241 class ISA_MIPS1_NOT_32R6_64R6 {
242 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
244 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
245 class ISA_MIPS2_NOT_32R6_64R6 {
246 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
248 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
249 class ISA_MIPS3_NOT_32R6_64R6 {
250 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
252 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
253 class ISA_MIPS32_NOT_32R6_64R6 {
254 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
256 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
257 class ISA_MIPS32R2_NOT_32R6_64R6 {
258 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
260 class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
261 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
262 class ISA_MIPS64_NOT_64R6 {
263 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
265 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
266 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
267 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
268 class ISA_MICROMIPS { list<Predicate> InsnPredicates = [InMicroMips]; }
269 class ISA_MICROMIPS32R6 {
270 list<Predicate> InsnPredicates = [HasMicroMips32r6];
272 class ISA_MICROMIPS64R6 {
273 list<Predicate> InsnPredicates = [HasMicroMips64r6];
275 class ISA_MICROMIPS32_NOT_MIPS32R6 {
276 list<Predicate> InsnPredicates = [InMicroMips, NotMips32r6];
279 class INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; }
280 class INSN_EVA_NOT_32R6_64R6 {
281 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
284 // The portions of MIPS-III that were also added to MIPS32
285 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
287 // The portions of MIPS-III that were also added to MIPS32 but were removed in
288 // MIPS32r6 and MIPS64r6.
289 class INSN_MIPS3_32_NOT_32R6_64R6 {
290 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
293 // The portions of MIPS-III that were also added to MIPS32
294 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
296 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
297 // MIPS32r6 and MIPS64r6.
298 class INSN_MIPS4_32_NOT_32R6_64R6 {
299 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
302 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
303 // MIPS32r6 and MIPS64r6.
304 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
305 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
308 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
309 // MIPS32r6 and MIPS64r6.
310 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
311 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
315 list<Predicate> InsnPredicates = [HasCnMips];
319 list<Predicate> InsnPredicates = [HasMSA];
322 class ASE_MSA_NOT_MSA64 {
323 list<Predicate> InsnPredicates = [HasMSA, NotMips64];
327 list<Predicate> InsnPredicates = [HasMSA, HasMips64];
330 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
331 // It can be used only on instructions that doesn't inherit PredicateControl.
332 class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
333 let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
336 //===----------------------------------------------------------------------===//
338 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
339 let EncodingPredicates = [HasStdEnc];
342 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
343 InstAlias<Asm, Result, Emit>, PredicateControl;
346 bit isCommutable = 1;
363 bit isTerminator = 1;
366 bit hasExtraSrcRegAllocReq = 1;
367 bit isCodeGenOnly = 1;
370 class IsAsCheapAsAMove {
371 bit isAsCheapAsAMove = 1;
374 class NeverHasSideEffects {
375 bit hasSideEffects = 0;
378 //===----------------------------------------------------------------------===//
379 // Instruction format superclass
380 //===----------------------------------------------------------------------===//
382 include "MipsInstrFormats.td"
384 //===----------------------------------------------------------------------===//
385 // Mips Operand, Complex Patterns and Transformations Definitions.
386 //===----------------------------------------------------------------------===//
388 class ConstantSImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
390 let Name = "ConstantSImm" # Bits;
391 let RenderMethod = "addImmOperands";
392 let PredicateMethod = "isConstantSImm<" # Bits # ">";
393 let SuperClasses = Supers;
394 let DiagnosticType = "SImm" # Bits;
397 class ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],
398 int Offset = 0> : AsmOperandClass {
399 let Name = "ConstantUImm" # Bits # "_" # Offset;
400 let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">";
401 let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">";
402 let SuperClasses = Supers;
403 let DiagnosticType = "UImm" # Bits # "_" # Offset;
406 def ConstantUImm10AsmOperandClass
407 : ConstantUImmAsmOperandClass<10, []>;
408 def ConstantUImm8AsmOperandClass
409 : ConstantUImmAsmOperandClass<8, [ConstantUImm10AsmOperandClass]>;
410 def ConstantUImm7AsmOperandClass
411 : ConstantUImmAsmOperandClass<7, [ConstantUImm8AsmOperandClass]>;
412 def ConstantUImm6AsmOperandClass
413 : ConstantUImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>;
414 def ConstantSImm6AsmOperandClass
415 : ConstantSImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>;
416 def ConstantUImm5Plus32AsmOperandClass
417 : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32>;
418 def ConstantUImm5Plus32NormalizeAsmOperandClass
419 : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32> {
420 let Name = "ConstantUImm5_32_Norm";
421 // We must also subtract 32 when we render the operand.
422 let RenderMethod = "addConstantUImmOperands<5, 32, -32>";
424 def ConstantUImm5Lsl2AsmOperandClass : AsmOperandClass {
425 let Name = "UImm5Lsl2";
426 let RenderMethod = "addImmOperands";
427 let PredicateMethod = "isScaledUImm<5, 2>";
428 let SuperClasses = [ConstantUImm6AsmOperandClass];
429 let DiagnosticType = "UImm5_Lsl2";
431 def ConstantUImm5ReportUImm6AsmOperandClass
432 : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass]> {
433 let Name = "ConstantUImm5_0_Report_UImm6";
434 let DiagnosticType = "UImm5_0_Report_UImm6";
436 def ConstantUImm5AsmOperandClass
437 : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass]>;
438 def ConstantUImm4AsmOperandClass
439 : ConstantUImmAsmOperandClass<
440 4, [ConstantUImm5AsmOperandClass,
441 ConstantUImm5Plus32AsmOperandClass,
442 ConstantUImm5Plus32NormalizeAsmOperandClass]>;
443 def ConstantUImm3AsmOperandClass
444 : ConstantUImmAsmOperandClass<3, [ConstantUImm4AsmOperandClass]>;
445 def ConstantUImm2Plus1AsmOperandClass
446 : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass], 1>;
447 def ConstantUImm2AsmOperandClass
448 : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass]>;
449 def ConstantUImm1AsmOperandClass
450 : ConstantUImmAsmOperandClass<1, [ConstantUImm2AsmOperandClass]>;
451 def ConstantImmzAsmOperandClass : AsmOperandClass {
452 let Name = "ConstantImmz";
453 let RenderMethod = "addConstantUImmOperands<1>";
454 let PredicateMethod = "isConstantImmz";
455 let SuperClasses = [ConstantUImm1AsmOperandClass];
456 let DiagnosticType = "Immz";
459 def MipsJumpTargetAsmOperand : AsmOperandClass {
460 let Name = "JumpTarget";
461 let ParserMethod = "parseJumpTarget";
462 let PredicateMethod = "isImm";
463 let RenderMethod = "addImmOperands";
466 // Instruction operand types
467 def jmptarget : Operand<OtherVT> {
468 let EncoderMethod = "getJumpTargetOpValue";
469 let ParserMatchClass = MipsJumpTargetAsmOperand;
471 def brtarget : Operand<OtherVT> {
472 let EncoderMethod = "getBranchTargetOpValue";
473 let OperandType = "OPERAND_PCREL";
474 let DecoderMethod = "DecodeBranchTarget";
475 let ParserMatchClass = MipsJumpTargetAsmOperand;
477 def calltarget : Operand<iPTR> {
478 let EncoderMethod = "getJumpTargetOpValue";
479 let ParserMatchClass = MipsJumpTargetAsmOperand;
482 def imm64: Operand<i64>;
484 def simm6 : Operand<i32> {
485 let ParserMatchClass = ConstantSImm6AsmOperandClass;
486 let OperandType = "OPERAND_IMMEDIATE";
488 def simm9 : Operand<i32>;
489 def simm10 : Operand<i32>;
490 def simm11 : Operand<i32>;
492 def simm16 : Operand<i32> {
493 let DecoderMethod= "DecodeSimm16";
496 def simm19_lsl2 : Operand<i32> {
497 let EncoderMethod = "getSimm19Lsl2Encoding";
498 let DecoderMethod = "DecodeSimm19Lsl2";
499 let ParserMatchClass = MipsJumpTargetAsmOperand;
502 def simm18_lsl3 : Operand<i32> {
503 let EncoderMethod = "getSimm18Lsl3Encoding";
504 let DecoderMethod = "DecodeSimm18Lsl3";
505 let ParserMatchClass = MipsJumpTargetAsmOperand;
508 def simm20 : Operand<i32>;
509 def simm32 : Operand<i32>;
511 def uimm20 : Operand<i32> {
514 def simm16_64 : Operand<i64> {
515 let DecoderMethod = "DecodeSimm16";
519 def uimmz : Operand<i32> {
520 let PrintMethod = "printUnsignedImm";
521 let ParserMatchClass = ConstantImmzAsmOperandClass;
525 foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10} in
526 def uimm # I : Operand<i32> {
527 let PrintMethod = "printUnsignedImm";
528 let ParserMatchClass =
529 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
532 def uimm2_plus1 : Operand<i32> {
533 let PrintMethod = "printUnsignedImm";
534 let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>";
535 let DecoderMethod = "DecodeUImmWithOffset<2, 1>";
536 let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass;
539 def uimm5_plus32 : Operand<i32> {
540 let PrintMethod = "printUnsignedImm";
541 let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass;
544 def uimm5_plus32_normalize : Operand<i32> {
545 let PrintMethod = "printUnsignedImm";
546 let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;
549 def uimm5_lsl2 : Operand<OtherVT> {
550 let EncoderMethod = "getUImm5Lsl2Encoding";
551 let DecoderMethod = "DecodeUImm5lsl2";
552 let ParserMatchClass = ConstantUImm5Lsl2AsmOperandClass;
555 def uimm5_plus32_normalize_64 : Operand<i64> {
556 let PrintMethod = "printUnsignedImm";
557 let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;
561 def uimm # I # _64 : Operand<i64> {
562 let PrintMethod = "printUnsignedImm";
563 let ParserMatchClass =
564 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
567 // Like uimm5_64 but reports a less confusing error for 32-63 when
568 // an instruction alias permits that.
569 def uimm5_64_report_uimm6 : Operand<i64> {
570 let PrintMethod = "printUnsignedImm";
571 let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;
574 def uimm16 : Operand<i32> {
575 let PrintMethod = "printUnsignedImm";
578 def pcrel16 : Operand<i32> {
581 def MipsMemAsmOperand : AsmOperandClass {
583 let ParserMethod = "parseMemOperand";
586 def MipsMemSimm9AsmOperand : AsmOperandClass {
587 let Name = "MemOffsetSimm9";
588 let SuperClasses = [MipsMemAsmOperand];
589 let RenderMethod = "addMemOperands";
590 let ParserMethod = "parseMemOperand";
591 let PredicateMethod = "isMemWithSimmOffset<9>";
594 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
595 let Name = "MemOffsetSimm9GPR";
596 let SuperClasses = [MipsMemAsmOperand];
597 let RenderMethod = "addMemOperands";
598 let ParserMethod = "parseMemOperand";
599 let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
602 def MipsMemSimm11AsmOperand : AsmOperandClass {
603 let Name = "MemOffsetSimm11";
604 let SuperClasses = [MipsMemAsmOperand];
605 let RenderMethod = "addMemOperands";
606 let ParserMethod = "parseMemOperand";
607 let PredicateMethod = "isMemWithSimmOffset<11>";
610 def MipsMemSimm16AsmOperand : AsmOperandClass {
611 let Name = "MemOffsetSimm16";
612 let SuperClasses = [MipsMemAsmOperand];
613 let RenderMethod = "addMemOperands";
614 let ParserMethod = "parseMemOperand";
615 let PredicateMethod = "isMemWithSimmOffset<16>";
618 def MipsInvertedImmoperand : AsmOperandClass {
620 let RenderMethod = "addImmOperands";
621 let ParserMethod = "parseInvNum";
624 def InvertedImOperand : Operand<i32> {
625 let ParserMatchClass = MipsInvertedImmoperand;
628 def InvertedImOperand64 : Operand<i64> {
629 let ParserMatchClass = MipsInvertedImmoperand;
632 class mem_generic : Operand<iPTR> {
633 let PrintMethod = "printMemOperand";
634 let MIOperandInfo = (ops ptr_rc, simm16);
635 let EncoderMethod = "getMemEncoding";
636 let ParserMatchClass = MipsMemAsmOperand;
637 let OperandType = "OPERAND_MEMORY";
641 def mem : mem_generic;
643 // MSA specific address operand
644 def mem_msa : mem_generic {
645 let MIOperandInfo = (ops ptr_rc, simm10);
646 let EncoderMethod = "getMSAMemEncoding";
649 def mem_simm9 : mem_generic {
650 let MIOperandInfo = (ops ptr_rc, simm9);
651 let EncoderMethod = "getMemEncoding";
652 let ParserMatchClass = MipsMemSimm9AsmOperand;
655 def mem_simm9gpr : mem_generic {
656 let MIOperandInfo = (ops ptr_rc, simm9);
657 let EncoderMethod = "getMemEncoding";
658 let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
661 def mem_simm11 : mem_generic {
662 let MIOperandInfo = (ops ptr_rc, simm11);
663 let EncoderMethod = "getMemEncoding";
664 let ParserMatchClass = MipsMemSimm11AsmOperand;
667 def mem_simm16 : mem_generic {
668 let MIOperandInfo = (ops ptr_rc, simm16);
669 let EncoderMethod = "getMemEncoding";
670 let ParserMatchClass = MipsMemSimm16AsmOperand;
673 def mem_ea : Operand<iPTR> {
674 let PrintMethod = "printMemOperandEA";
675 let MIOperandInfo = (ops ptr_rc, simm16);
676 let EncoderMethod = "getMemEncoding";
677 let OperandType = "OPERAND_MEMORY";
680 def PtrRC : Operand<iPTR> {
681 let MIOperandInfo = (ops ptr_rc);
682 let DecoderMethod = "DecodePtrRegisterClass";
683 let ParserMatchClass = GPR32AsmOperand;
686 // size operand of ext instruction
687 def size_ext : Operand<i32> {
688 let EncoderMethod = "getSizeExtEncoding";
689 let DecoderMethod = "DecodeExtSize";
692 // size operand of ins instruction
693 def size_ins : Operand<i32> {
694 let EncoderMethod = "getSizeInsEncoding";
695 let DecoderMethod = "DecodeInsSize";
698 // Transformation Function - get the lower 16 bits.
699 def LO16 : SDNodeXForm<imm, [{
700 return getImm(N, N->getZExtValue() & 0xFFFF);
703 // Transformation Function - get the higher 16 bits.
704 def HI16 : SDNodeXForm<imm, [{
705 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
709 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
711 // Node immediate is zero (e.g. insve.d)
712 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
714 // Node immediate fits as 16-bit sign extended on target immediate.
716 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
718 // Node immediate fits as 16-bit sign extended on target immediate.
720 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
722 // Node immediate fits as 15-bit sign extended on target immediate.
724 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
726 // Node immediate fits as 16-bit zero extended on target immediate.
727 // The LO16 param means that only the lower 16 bits of the node
728 // immediate are caught.
730 def immZExt16 : PatLeaf<(imm), [{
731 if (N->getValueType(0) == MVT::i32)
732 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
734 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
737 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
738 def immLow16Zero : PatLeaf<(imm), [{
739 int64_t Val = N->getSExtValue();
740 return isInt<32>(Val) && !(Val & 0xffff);
743 // shamt field must fit in 5 bits.
744 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
746 // True if (N + 1) fits in 16-bit field.
747 def immSExt16Plus1 : PatLeaf<(imm), [{
748 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
751 // Mips Address Mode! SDNode frameindex could possibily be a match
752 // since load and store instructions from stack used it.
754 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
757 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
760 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
763 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
765 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
767 //===----------------------------------------------------------------------===//
768 // Instructions specific format
769 //===----------------------------------------------------------------------===//
771 // Arithmetic and logical instructions with 3 register operands.
772 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
773 InstrItinClass Itin = NoItinerary,
774 SDPatternOperator OpNode = null_frag>:
775 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
776 !strconcat(opstr, "\t$rd, $rs, $rt"),
777 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
778 let isCommutable = isComm;
779 let isReMaterializable = 1;
780 let TwoOperandAliasConstraint = "$rd = $rs";
783 // Arithmetic and logical instructions with 2 register operands.
784 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
785 InstrItinClass Itin = NoItinerary,
786 SDPatternOperator imm_type = null_frag,
787 SDPatternOperator OpNode = null_frag> :
788 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
789 !strconcat(opstr, "\t$rt, $rs, $imm16"),
790 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
792 let isReMaterializable = 1;
793 let TwoOperandAliasConstraint = "$rs = $rt";
796 // Arithmetic Multiply ADD/SUB
797 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
798 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
799 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
800 let Defs = [HI0, LO0];
801 let Uses = [HI0, LO0];
802 let isCommutable = isComm;
806 class LogicNOR<string opstr, RegisterOperand RO>:
807 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
808 !strconcat(opstr, "\t$rd, $rs, $rt"),
809 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
810 let isCommutable = 1;
814 class shift_rotate_imm<string opstr, Operand ImmOpnd,
815 RegisterOperand RO, InstrItinClass itin,
816 SDPatternOperator OpNode = null_frag,
817 SDPatternOperator PF = null_frag> :
818 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
819 !strconcat(opstr, "\t$rd, $rt, $shamt"),
820 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
821 let TwoOperandAliasConstraint = "$rt = $rd";
824 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
825 SDPatternOperator OpNode = null_frag>:
826 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
827 !strconcat(opstr, "\t$rd, $rt, $rs"),
828 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
831 // Load Upper Immediate
832 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
833 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
834 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
835 let hasSideEffects = 0;
836 let isReMaterializable = 1;
840 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
841 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
842 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
843 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
844 let DecoderMethod = "DecodeMem";
845 let canFoldAsLoad = 1;
849 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
850 SDPatternOperator OpNode = null_frag,
851 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
852 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
853 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
854 let DecoderMethod = "DecodeMem";
858 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
859 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
860 StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
862 // Load/Store Left/Right
863 let canFoldAsLoad = 1 in
864 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
865 InstrItinClass Itin> :
866 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
867 !strconcat(opstr, "\t$rt, $addr"),
868 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
869 let DecoderMethod = "DecodeMem";
870 string Constraints = "$src = $rt";
873 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
874 InstrItinClass Itin> :
875 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
876 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
877 let DecoderMethod = "DecodeMem";
881 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
882 SDPatternOperator OpNode= null_frag> :
883 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
884 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
885 let DecoderMethod = "DecodeFMem2";
889 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
890 SDPatternOperator OpNode= null_frag> :
891 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
892 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
893 let DecoderMethod = "DecodeFMem2";
898 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
899 SDPatternOperator OpNode= null_frag> :
900 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
901 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
902 let DecoderMethod = "DecodeFMem3";
906 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
907 SDPatternOperator OpNode= null_frag> :
908 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
909 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
910 let DecoderMethod = "DecodeFMem3";
914 // Conditional Branch
915 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
916 RegisterOperand RO, bit DelaySlot = 1> :
917 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
918 !strconcat(opstr, "\t$rs, $rt, $offset"),
919 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
922 let isTerminator = 1;
923 let hasDelaySlot = DelaySlot;
927 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
928 RegisterOperand RO, bit DelaySlot = 1> :
929 InstSE<(outs), (ins RO:$rs, opnd:$offset),
930 !strconcat(opstr, "\t$rs, $offset"),
931 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
934 let isTerminator = 1;
935 let hasDelaySlot = DelaySlot;
940 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
941 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
942 !strconcat(opstr, "\t$rd, $rs, $rt"),
943 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
944 II_SLT_SLTU, FrmR, opstr>;
946 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
948 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
949 !strconcat(opstr, "\t$rt, $rs, $imm16"),
950 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
951 II_SLTI_SLTIU, FrmI, opstr>;
954 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
955 SDPatternOperator targetoperator, string bopstr> :
956 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
957 [(operator targetoperator:$target)], II_J, FrmJ, bopstr> {
960 let hasDelaySlot = 1;
961 let DecoderMethod = "DecodeJumpTarget";
965 // Unconditional branch
966 class UncondBranch<Instruction BEQInst> :
967 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
968 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
970 let isTerminator = 1;
972 let hasDelaySlot = 1;
973 let AdditionalPredicates = [RelocPIC];
977 // Base class for indirect branch and return instruction classes.
978 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
979 class JumpFR<string opstr, RegisterOperand RO,
980 SDPatternOperator operator = null_frag>:
981 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
985 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
987 let isIndirectBranch = 1;
990 // Jump and Link (Call)
991 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
992 class JumpLink<string opstr, DAGOperand opnd> :
993 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
994 [(MipsJmpLink imm:$target)], II_JAL, FrmJ, opstr> {
995 let DecoderMethod = "DecodeJumpTarget";
998 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
999 Register RetReg, RegisterOperand ResRO = RO>:
1000 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
1001 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
1003 class JumpLinkReg<string opstr, RegisterOperand RO>:
1004 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1005 [], II_JALR, FrmR, opstr>;
1007 class BGEZAL_FT<string opstr, DAGOperand opnd,
1008 RegisterOperand RO, bit DelaySlot = 1> :
1009 InstSE<(outs), (ins RO:$rs, opnd:$offset),
1010 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> {
1011 let hasDelaySlot = DelaySlot;
1016 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
1017 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
1018 class TailCall<Instruction JumpInst> :
1019 PseudoSE<(outs), (ins calltarget:$target), [], II_J>,
1020 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
1022 class TailCallReg<RegisterOperand RO, Instruction JRInst,
1023 RegisterOperand ResRO = RO> :
1024 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1025 PseudoInstExpansion<(JRInst ResRO:$rs)>;
1028 class BAL_BR_Pseudo<Instruction RealInst> :
1029 PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
1030 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
1032 let isTerminator = 1;
1034 let hasDelaySlot = 1;
1039 class SYS_FT<string opstr> :
1040 InstSE<(outs), (ins uimm20:$code_),
1041 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
1043 class BRK_FT<string opstr> :
1044 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
1045 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
1049 class ER_FT<string opstr> :
1050 InstSE<(outs), (ins),
1051 opstr, [], NoItinerary, FrmOther, opstr>;
1054 class DEI_FT<string opstr, RegisterOperand RO> :
1055 InstSE<(outs RO:$rt), (ins),
1056 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
1059 class WAIT_FT<string opstr> :
1060 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
1063 let hasSideEffects = 1 in
1064 class SYNC_FT<string opstr> :
1065 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
1066 NoItinerary, FrmOther, opstr>;
1068 class SYNCI_FT<string opstr> :
1069 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
1070 NoItinerary, FrmOther, opstr> {
1071 let hasSideEffects = 1;
1072 let DecoderMethod = "DecodeSyncI";
1075 let hasSideEffects = 1 in
1076 class TEQ_FT<string opstr, RegisterOperand RO> :
1077 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
1078 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
1081 class TEQI_FT<string opstr, RegisterOperand RO> :
1082 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
1083 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
1085 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
1086 list<Register> DefRegs> :
1087 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
1088 itin, FrmR, opstr> {
1089 let isCommutable = 1;
1091 let hasSideEffects = 0;
1094 // Pseudo multiply/divide instruction with explicit accumulator register
1096 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
1097 SDPatternOperator OpNode, InstrItinClass Itin,
1098 bit IsComm = 1, bit HasSideEffects = 0,
1099 bit UsesCustomInserter = 0> :
1100 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
1101 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
1102 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
1103 let isCommutable = IsComm;
1104 let hasSideEffects = HasSideEffects;
1105 let usesCustomInserter = UsesCustomInserter;
1108 // Pseudo multiply add/sub instruction with explicit accumulator register
1110 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
1111 InstrItinClass itin>
1112 : PseudoSE<(outs ACC64:$ac),
1113 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
1115 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
1117 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
1118 string Constraints = "$acin = $ac";
1121 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
1122 list<Register> DefRegs> :
1123 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
1124 [], itin, FrmR, opstr> {
1129 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
1130 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
1131 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
1133 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1134 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
1136 let Uses = [UseReg];
1137 let hasSideEffects = 0;
1140 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
1141 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
1142 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
1145 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1146 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
1149 let hasSideEffects = 0;
1152 class EffectiveAddress<string opstr, RegisterOperand RO> :
1153 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
1154 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
1155 !strconcat(opstr, "_lea")> {
1156 let isCodeGenOnly = 1;
1157 let DecoderMethod = "DecodeMem";
1160 // Count Leading Ones/Zeros in Word
1161 class CountLeading0<string opstr, RegisterOperand RO>:
1162 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1163 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
1165 class CountLeading1<string opstr, RegisterOperand RO>:
1166 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1167 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
1169 // Sign Extend in Register.
1170 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
1171 InstrItinClass itin> :
1172 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
1173 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1176 class SubwordSwap<string opstr, RegisterOperand RO,
1177 InstrItinClass itin = NoItinerary>:
1178 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
1180 let hasSideEffects = 0;
1184 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
1185 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
1186 II_RDHWR, FrmR, "rdhwr">;
1189 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1190 SDPatternOperator Op = null_frag>:
1191 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
1192 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1193 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
1194 FrmR, opstr>, ISA_MIPS32R2;
1196 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1197 SDPatternOperator Op = null_frag>:
1198 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1199 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1200 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1201 II_INS, FrmR, opstr>, ISA_MIPS32R2 {
1202 let Constraints = "$src = $rt";
1205 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1206 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1207 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1208 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1210 // Atomic Compare & Swap.
1211 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1212 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1213 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1215 class LLBase<string opstr, RegisterOperand RO> :
1216 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1217 [], NoItinerary, FrmI> {
1218 let DecoderMethod = "DecodeMem";
1222 class SCBase<string opstr, RegisterOperand RO> :
1223 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1224 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1225 let DecoderMethod = "DecodeMem";
1227 let Constraints = "$rt = $dst";
1230 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1231 InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
1232 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1234 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1235 InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
1236 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1238 class TrapBase<Instruction RealInst>
1239 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1240 PseudoInstExpansion<(RealInst 0, 0)> {
1242 let isTerminator = 1;
1243 let isCodeGenOnly = 1;
1246 //===----------------------------------------------------------------------===//
1247 // Pseudo instructions
1248 //===----------------------------------------------------------------------===//
1251 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1252 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1254 let isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, hasSideEffects=1 in
1255 def ERet : PseudoSE<(outs), (ins), [(MipsERet)]>;
1257 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1258 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1259 [(callseq_start timm:$amt)]>;
1260 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1261 [(callseq_end timm:$amt1, timm:$amt2)]>;
1264 let usesCustomInserter = 1 in {
1265 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1266 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1267 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1268 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1269 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1270 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1271 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1272 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1273 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1274 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1275 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1276 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1277 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1278 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1279 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1280 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1281 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1282 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1284 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1285 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1286 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1288 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1289 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1290 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1293 /// Pseudo instructions for loading and storing accumulator registers.
1294 let isPseudo = 1, isCodeGenOnly = 1 in {
1295 def LOAD_ACC64 : Load<"", ACC64>;
1296 def STORE_ACC64 : Store<"", ACC64>;
1299 // We need these two pseudo instructions to avoid offset calculation for long
1300 // branches. See the comment in file MipsLongBranch.cpp for detailed
1303 // Expands to: lui $dst, %hi($tgt - $baltgt)
1304 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1305 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1307 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1308 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1309 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1311 //===----------------------------------------------------------------------===//
1312 // Instruction definition
1313 //===----------------------------------------------------------------------===//
1314 //===----------------------------------------------------------------------===//
1315 // MipsI Instructions
1316 //===----------------------------------------------------------------------===//
1318 /// Arithmetic Instructions (ALU Immediate)
1319 let AdditionalPredicates = [NotInMicroMips] in {
1320 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
1321 II_ADDIU, immSExt16, add>,
1322 ADDI_FM<0x9>, IsAsCheapAsAMove;
1324 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1325 ISA_MIPS1_NOT_32R6_64R6;
1326 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1328 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1330 let AdditionalPredicates = [NotInMicroMips] in {
1331 def ANDi : MMRel, StdMMR6Rel,
1332 ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
1335 def ORi : MMRel, StdMMR6Rel,
1336 ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
1338 def XORi : MMRel, StdMMR6Rel,
1339 ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
1341 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1342 let AdditionalPredicates = [NotInMicroMips] in {
1343 /// Arithmetic Instructions (3-Operand, R-Type)
1344 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1346 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1349 let Defs = [HI0, LO0] in
1350 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1351 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1352 def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1353 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1354 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1355 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1356 let AdditionalPredicates = [NotInMicroMips] in {
1357 def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1359 def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1361 def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1364 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1366 /// Shift Instructions
1367 let AdditionalPredicates = [NotInMicroMips] in {
1368 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1369 immZExt5>, SRA_FM<0, 0>;
1370 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1371 immZExt5>, SRA_FM<2, 0>;
1373 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1374 immZExt5>, SRA_FM<3, 0>;
1375 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1377 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1379 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1382 // Rotate Instructions
1383 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1385 SRA_FM<2, 1>, ISA_MIPS32R2;
1386 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1387 SRLV_FM<6, 1>, ISA_MIPS32R2;
1389 /// Load and Store Instructions
1391 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1392 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1394 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1396 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1397 let AdditionalPredicates = [NotInMicroMips] in {
1398 def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1401 def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
1403 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1404 let AdditionalPredicates = [NotInMicroMips] in {
1405 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1408 /// load/store left/right
1409 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1410 AdditionalPredicates = [NotInMicroMips] in {
1411 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1412 ISA_MIPS1_NOT_32R6_64R6;
1413 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1414 ISA_MIPS1_NOT_32R6_64R6;
1415 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1416 ISA_MIPS1_NOT_32R6_64R6;
1417 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1418 ISA_MIPS1_NOT_32R6_64R6;
1421 let AdditionalPredicates = [NotInMicroMips] in {
1422 // COP2 Memory Instructions
1423 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1424 ISA_MIPS1_NOT_32R6_64R6;
1425 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1426 ISA_MIPS1_NOT_32R6_64R6;
1427 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1428 ISA_MIPS2_NOT_32R6_64R6;
1429 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1430 ISA_MIPS2_NOT_32R6_64R6;
1432 // COP3 Memory Instructions
1433 let DecoderNamespace = "COP3_" in {
1434 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1435 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1436 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1438 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1443 def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1444 def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1446 let AdditionalPredicates = [NotInMicroMips] in {
1447 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1448 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1449 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1450 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1451 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1452 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1455 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1456 ISA_MIPS2_NOT_32R6_64R6;
1457 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1458 ISA_MIPS2_NOT_32R6_64R6;
1459 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1460 ISA_MIPS2_NOT_32R6_64R6;
1461 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1462 ISA_MIPS2_NOT_32R6_64R6;
1463 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1464 ISA_MIPS2_NOT_32R6_64R6;
1465 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1466 ISA_MIPS2_NOT_32R6_64R6;
1468 let AdditionalPredicates = [NotInMicroMips] in {
1469 def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
1471 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1472 def TRAP : TrapBase<BREAK>;
1473 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1475 let AdditionalPredicates = [NotInMicroMips] in {
1476 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
1477 def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
1479 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
1481 let AdditionalPredicates = [NotInMicroMips] in {
1482 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1484 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1486 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1487 AdditionalPredicates = [NotInMicroMips] in {
1488 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1490 /// Load-linked, Store-conditional
1491 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1492 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1495 /// Jump and Branch Instructions
1496 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1497 AdditionalRequires<[RelocStatic]>, IsBranch;
1498 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1499 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1500 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1501 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1502 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1503 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1504 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1505 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1507 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1508 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1509 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1511 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1512 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1513 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1515 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1516 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1517 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1519 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1520 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1521 def B : UncondBranch<BEQ>;
1523 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1524 let AdditionalPredicates = [NotInMicroMips] in {
1525 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1526 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1529 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
1530 ISA_MIPS32_NOT_32R6_64R6;
1531 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1532 ISA_MIPS1_NOT_32R6_64R6;
1533 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1534 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1535 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1536 ISA_MIPS1_NOT_32R6_64R6;
1537 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1538 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1539 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1540 def TAILCALL : TailCall<J>;
1541 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1543 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1544 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1545 class PseudoIndirectBranchBase<RegisterOperand RO> :
1546 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1547 II_IndirectBranchPseudo> {
1550 let hasDelaySlot = 1;
1552 let isIndirectBranch = 1;
1555 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1557 // Return instructions are matched as a RetRA instruction, then are expanded
1558 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1559 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1561 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1562 [], II_ReturnPseudo> {
1563 let isTerminator = 1;
1565 let hasDelaySlot = 1;
1567 let isCodeGenOnly = 1;
1569 let hasExtraSrcRegAllocReq = 1;
1572 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1574 // Exception handling related node and instructions.
1575 // The conversion sequence is:
1576 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1577 // MIPSeh_return -> (stack change + indirect branch)
1579 // MIPSeh_return takes the place of regular return instruction
1580 // but takes two arguments (V1, V0) which are used for storing
1581 // the offset and return address respectively.
1582 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1584 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1585 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1587 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1588 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1589 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1590 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1592 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1595 /// Multiply and Divide Instructions.
1596 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1597 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1598 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1599 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1600 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1601 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1602 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1603 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1605 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1606 ISA_MIPS1_NOT_32R6_64R6;
1607 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1608 ISA_MIPS1_NOT_32R6_64R6;
1609 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1610 AdditionalPredicates = [NotInMicroMips] in {
1611 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1612 ISA_MIPS1_NOT_32R6_64R6;
1613 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1614 ISA_MIPS1_NOT_32R6_64R6;
1617 /// Sign Ext In Register Instructions.
1618 def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1619 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1620 def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1621 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1624 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1625 ISA_MIPS32_NOT_32R6_64R6;
1626 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1627 ISA_MIPS32_NOT_32R6_64R6;
1629 let AdditionalPredicates = [NotInMicroMips] in {
1630 /// Word Swap Bytes Within Halfwords
1631 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
1636 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1638 // FrameIndexes are legalized when they are operands from load/store
1639 // instructions. The same not happens for stack address copies, so an
1640 // add op with mem ComplexPattern is used and the stack address copy
1641 // can be matched. It's similar to Sparc LEA_ADDRi
1642 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1645 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1646 ISA_MIPS32_NOT_32R6_64R6;
1647 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1648 ISA_MIPS32_NOT_32R6_64R6;
1649 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1650 ISA_MIPS32_NOT_32R6_64R6;
1651 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1652 ISA_MIPS32_NOT_32R6_64R6;
1654 let AdditionalPredicates = [NotDSP] in {
1655 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1656 ISA_MIPS1_NOT_32R6_64R6;
1657 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1658 ISA_MIPS1_NOT_32R6_64R6;
1659 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1660 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1661 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1662 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1663 ISA_MIPS32_NOT_32R6_64R6;
1664 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1665 ISA_MIPS32_NOT_32R6_64R6;
1666 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1667 ISA_MIPS32_NOT_32R6_64R6;
1668 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1669 ISA_MIPS32_NOT_32R6_64R6;
1672 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1673 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1674 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1675 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1676 let AdditionalPredicates = [NotInMicroMips] in {
1677 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1679 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1680 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1682 /// Move Control Registers From/To CPU Registers
1683 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1684 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1685 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
1686 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1688 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1690 def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop">, BARRIER_FM<1>;
1691 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
1692 def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1694 // JR_HB and JALR_HB are defined here using the new style naming
1695 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1696 // and because of that it doesn't follow the naming convention of the
1697 // rest of the file. To avoid a mixture of old vs new style, the new
1698 // style was chosen.
1699 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1700 dag OutOperandList = (outs);
1701 dag InOperandList = (ins GPROpnd:$rs);
1702 string AsmString = !strconcat(instr_asm, "\t$rs");
1703 list<dag> Pattern = [];
1706 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1707 dag OutOperandList = (outs GPROpnd:$rd);
1708 dag InOperandList = (ins GPROpnd:$rs);
1709 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1710 list<dag> Pattern = [];
1713 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1714 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1716 let isIndirectBranch=1;
1722 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1723 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1724 let isIndirectBranch=1;
1728 class JR_HB_ENC : JR_HB_FM<8>;
1729 class JALR_HB_ENC : JALR_HB_FM<9>;
1731 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1732 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1734 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1736 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1737 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1738 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1739 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1741 class CacheOp<string instr_asm, Operand MemOpnd> :
1742 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1743 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
1745 let DecoderMethod = "DecodeCacheOp";
1748 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1749 INSN_MIPS3_32_NOT_32R6_64R6;
1750 def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1751 INSN_MIPS3_32_NOT_32R6_64R6;
1753 def ROL : MipsAsmPseudoInst<(outs),
1754 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
1755 "rol\t$rs, $rt, $rd">;
1756 def ROLImm : MipsAsmPseudoInst<(outs),
1757 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
1758 "rol\t$rs, $rt, $imm">;
1759 def : MipsInstAlias<"rol $rd, $rs",
1760 (ROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1761 def : MipsInstAlias<"rol $rd, $imm",
1762 (ROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;
1764 def ROR : MipsAsmPseudoInst<(outs),
1765 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
1766 "ror\t$rs, $rt, $rd">;
1767 def RORImm : MipsAsmPseudoInst<(outs),
1768 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
1769 "ror\t$rs, $rt, $imm">;
1770 def : MipsInstAlias<"ror $rd, $rs",
1771 (ROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1772 def : MipsInstAlias<"ror $rd, $imm",
1773 (RORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;
1775 def DROL : MipsAsmPseudoInst<(outs),
1776 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
1777 "drol\t$rs, $rt, $rd">, ISA_MIPS64;
1778 def DROLImm : MipsAsmPseudoInst<(outs),
1779 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
1780 "drol\t$rs, $rt, $imm">, ISA_MIPS64;
1781 def : MipsInstAlias<"drol $rd, $rs",
1782 (DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
1783 def : MipsInstAlias<"drol $rd, $imm",
1784 (DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
1786 def DROR : MipsAsmPseudoInst<(outs),
1787 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
1788 "dror\t$rs, $rt, $rd">, ISA_MIPS64;
1789 def DRORImm : MipsAsmPseudoInst<(outs),
1790 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
1791 "dror\t$rs, $rt, $imm">, ISA_MIPS64;
1792 def : MipsInstAlias<"dror $rd, $rs",
1793 (DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
1794 def : MipsInstAlias<"dror $rd, $imm",
1795 (DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
1797 //===----------------------------------------------------------------------===//
1798 // Instruction aliases
1799 //===----------------------------------------------------------------------===//
1800 def : MipsInstAlias<"move $dst, $src",
1801 (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
1803 let AdditionalPredicates = [NotInMicroMips];
1805 def : MipsInstAlias<"move $dst, $src",
1806 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
1808 let AdditionalPredicates = [NotInMicroMips];
1810 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1811 ISA_MIPS1_NOT_32R6_64R6;
1812 def : MipsInstAlias<"addu $rs, $rt, $imm",
1813 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1814 def : MipsInstAlias<"addu $rs, $imm",
1815 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1816 def : MipsInstAlias<"add $rs, $rt, $imm",
1817 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1818 ISA_MIPS1_NOT_32R6_64R6;
1819 def : MipsInstAlias<"add $rs, $imm",
1820 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1821 ISA_MIPS1_NOT_32R6_64R6;
1822 def : MipsInstAlias<"and $rs, $rt, $imm",
1823 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1824 def : MipsInstAlias<"and $rs, $imm",
1825 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1826 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1827 let Predicates = [NotInMicroMips] in {
1828 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1830 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1831 def : MipsInstAlias<"not $rt, $rs",
1832 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1833 def : MipsInstAlias<"neg $rt, $rs",
1834 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1835 def : MipsInstAlias<"negu $rt",
1836 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1837 def : MipsInstAlias<"negu $rt, $rs",
1838 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1839 def : MipsInstAlias<"slt $rs, $rt, $imm",
1840 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1841 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1842 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1843 def : MipsInstAlias<"xor $rs, $rt, $imm",
1844 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1845 def : MipsInstAlias<"xor $rs, $imm",
1846 (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1847 def : MipsInstAlias<"or $rs, $rt, $imm",
1848 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1849 def : MipsInstAlias<"or $rs, $imm",
1850 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1851 let AdditionalPredicates = [NotInMicroMips] in {
1852 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1854 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
1855 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1856 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
1857 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1858 let AdditionalPredicates = [NotInMicroMips] in {
1859 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1861 def : MipsInstAlias<"bnez $rs,$offset",
1862 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1863 def : MipsInstAlias<"bnezl $rs,$offset",
1864 (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1865 def : MipsInstAlias<"beqz $rs,$offset",
1866 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1867 def : MipsInstAlias<"beqzl $rs,$offset",
1868 (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1869 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1871 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1872 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1873 let AdditionalPredicates = [NotInMicroMips] in {
1874 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1876 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1877 let AdditionalPredicates = [NotInMicroMips] in {
1878 def : MipsInstAlias<"teq $rs, $rt",
1879 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1880 def : MipsInstAlias<"tge $rs, $rt",
1881 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1882 def : MipsInstAlias<"tgeu $rs, $rt",
1883 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1884 def : MipsInstAlias<"tlt $rs, $rt",
1885 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1886 def : MipsInstAlias<"tltu $rs, $rt",
1887 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1888 def : MipsInstAlias<"tne $rs, $rt",
1889 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1891 def : MipsInstAlias<"sll $rd, $rt, $rs",
1892 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1893 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1894 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1895 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1896 def : MipsInstAlias<"sub $rs, $imm",
1897 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1898 0>, ISA_MIPS1_NOT_32R6_64R6;
1899 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1900 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1901 InvertedImOperand:$imm), 0>;
1902 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1903 InvertedImOperand:$imm), 0>;
1904 def : MipsInstAlias<"sra $rd, $rt, $rs",
1905 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1906 def : MipsInstAlias<"srl $rd, $rt, $rs",
1907 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1908 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1909 def : MipsInstAlias<"sync",
1910 (SYNC 0), 1>, ISA_MIPS2;
1911 //===----------------------------------------------------------------------===//
1912 // Assembler Pseudo Instructions
1913 //===----------------------------------------------------------------------===//
1915 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
1916 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1917 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1918 def LoadImm32 : LoadImmediate32<"li", simm32, GPR32Opnd>;
1920 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
1921 RegisterOperand RO> :
1922 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1923 !strconcat(instr_asm, "\t$rt, $addr")> ;
1924 def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
1926 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
1927 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1928 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1929 def LoadAddrImm32 : LoadAddressFromImm32<"la", simm32, GPR32Opnd>;
1931 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
1933 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
1936 def NORImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
1937 "nor\t$rs, $rt, $imm"> ;
1939 let hasDelaySlot = 1 in {
1940 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1941 (ins imm64:$imm64, brtarget:$offset),
1942 "bne\t$rt, $imm64, $offset">;
1943 def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1944 (ins imm64:$imm64, brtarget:$offset),
1945 "beq\t$rt, $imm64, $offset">;
1947 class CondBranchPseudo<string instr_asm> :
1948 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt,
1950 !strconcat(instr_asm, "\t$rs, $rt, $offset")>;
1953 def BLT : CondBranchPseudo<"blt">;
1954 def BLE : CondBranchPseudo<"ble">;
1955 def BGE : CondBranchPseudo<"bge">;
1956 def BGT : CondBranchPseudo<"bgt">;
1957 def BLTU : CondBranchPseudo<"bltu">;
1958 def BLEU : CondBranchPseudo<"bleu">;
1959 def BGEU : CondBranchPseudo<"bgeu">;
1960 def BGTU : CondBranchPseudo<"bgtu">;
1961 def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
1962 def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
1963 def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
1964 def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
1965 def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
1966 def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
1967 def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
1968 def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
1970 class CondBranchImmPseudo<string instr_asm> :
1971 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset),
1972 !strconcat(instr_asm, "\t$rs, $imm, $offset")>;
1974 def BLTImmMacro : CondBranchImmPseudo<"blt">;
1975 def BLEImmMacro : CondBranchImmPseudo<"ble">;
1976 def BGEImmMacro : CondBranchImmPseudo<"bge">;
1977 def BGTImmMacro : CondBranchImmPseudo<"bgt">;
1978 def BLTUImmMacro : CondBranchImmPseudo<"bltu">;
1979 def BLEUImmMacro : CondBranchImmPseudo<"bleu">;
1980 def BGEUImmMacro : CondBranchImmPseudo<"bgeu">;
1981 def BGTUImmMacro : CondBranchImmPseudo<"bgtu">;
1982 def BLTLImmMacro : CondBranchImmPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
1983 def BLELImmMacro : CondBranchImmPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
1984 def BGELImmMacro : CondBranchImmPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
1985 def BGTLImmMacro : CondBranchImmPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
1986 def BLTULImmMacro : CondBranchImmPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
1987 def BLEULImmMacro : CondBranchImmPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
1988 def BGEULImmMacro : CondBranchImmPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
1989 def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
1991 // FIXME: Predicates are removed because instructions are matched regardless of
1992 // predicates, because PredicateControl was not in the hierarchy. This was
1993 // done to emit more precise error message from expansion function.
1994 // Once the tablegen-erated errors are made better, this needs to be fixed and
1995 // predicates needs to be restored.
1997 def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1998 "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
2000 def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
2001 "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
2003 def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
2004 "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
2006 def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
2007 "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
2009 def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
2010 "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
2012 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
2013 "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
2015 def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
2016 "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
2018 //===----------------------------------------------------------------------===//
2019 // Arbitrary patterns that map to one or more instructions
2020 //===----------------------------------------------------------------------===//
2022 // Load/store pattern templates.
2023 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
2024 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
2026 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
2027 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
2030 let AdditionalPredicates = [NotInMicroMips] in {
2031 def : MipsPat<(i32 immSExt16:$in),
2032 (ADDiu ZERO, imm:$in)>;
2033 def : MipsPat<(i32 immZExt16:$in),
2034 (ORi ZERO, imm:$in)>;
2036 def : MipsPat<(i32 immLow16Zero:$in),
2037 (LUi (HI16 imm:$in))>;
2039 // Arbitrary immediates
2040 def : MipsPat<(i32 imm:$imm),
2041 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
2043 // Carry MipsPatterns
2044 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
2045 (SUBu GPR32:$lhs, GPR32:$rhs)>;
2046 let AdditionalPredicates = [NotDSP] in {
2047 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
2048 (ADDu GPR32:$lhs, GPR32:$rhs)>;
2049 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
2050 (ADDiu GPR32:$src, imm:$imm)>;
2053 // Support multiplication for pre-Mips32 targets that don't have
2054 // the MUL instruction.
2055 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
2056 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
2057 ISA_MIPS1_NOT_32R6_64R6;
2060 def : MipsPat<(MipsSync (i32 immz)),
2061 (SYNC 0)>, ISA_MIPS2;
2064 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
2065 (JAL tglobaladdr:$dst)>;
2066 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
2067 (JAL texternalsym:$dst)>;
2068 //def : MipsPat<(MipsJmpLink GPR32:$dst),
2069 // (JALR GPR32:$dst)>;
2072 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
2073 (TAILCALL tglobaladdr:$dst)>;
2074 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
2075 (TAILCALL texternalsym:$dst)>;
2077 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
2078 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
2079 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
2080 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
2081 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
2082 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
2084 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
2085 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
2086 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
2087 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
2088 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
2089 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
2091 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
2092 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
2093 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
2094 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
2095 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
2096 (ADDiu GPR32:$hi, tjumptable:$lo)>;
2097 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
2098 (ADDiu GPR32:$hi, tconstpool:$lo)>;
2099 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
2100 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
2103 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
2104 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
2105 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
2106 (ADDiu GPR32:$gp, tconstpool:$in)>;
2109 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
2110 MipsPat<(MipsWrapper RC:$gp, node:$in),
2111 (ADDiuOp RC:$gp, node:$in)>;
2113 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
2114 def : WrapperPat<tconstpool, ADDiu, GPR32>;
2115 def : WrapperPat<texternalsym, ADDiu, GPR32>;
2116 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
2117 def : WrapperPat<tjumptable, ADDiu, GPR32>;
2118 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
2120 let AdditionalPredicates = [NotInMicroMips] in {
2121 // Mips does not have "not", so we expand our way
2122 def : MipsPat<(not GPR32:$in),
2123 (NOR GPR32Opnd:$in, ZERO)>;
2127 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
2128 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
2129 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
2132 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
2135 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
2136 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
2137 Instruction SLTiuOp, Register ZEROReg> {
2138 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
2139 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
2140 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
2141 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
2143 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
2144 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
2145 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
2146 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
2147 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
2148 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
2149 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
2150 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
2151 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
2152 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
2153 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
2154 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
2156 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
2157 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
2158 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
2159 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
2161 def : MipsPat<(brcond RC:$cond, bb:$dst),
2162 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
2165 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
2167 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
2168 (BLEZ i32:$lhs, bb:$dst)>;
2169 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
2170 (BGEZ i32:$lhs, bb:$dst)>;
2173 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
2174 Instruction SLTuOp, Register ZEROReg> {
2175 def : MipsPat<(seteq RC:$lhs, 0),
2176 (SLTiuOp RC:$lhs, 1)>;
2177 def : MipsPat<(setne RC:$lhs, 0),
2178 (SLTuOp ZEROReg, RC:$lhs)>;
2179 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
2180 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
2181 def : MipsPat<(setne RC:$lhs, RC:$rhs),
2182 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
2185 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2186 def : MipsPat<(setle RC:$lhs, RC:$rhs),
2187 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
2188 def : MipsPat<(setule RC:$lhs, RC:$rhs),
2189 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
2192 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2193 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
2194 (SLTOp RC:$rhs, RC:$lhs)>;
2195 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
2196 (SLTuOp RC:$rhs, RC:$lhs)>;
2199 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2200 def : MipsPat<(setge RC:$lhs, RC:$rhs),
2201 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
2202 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
2203 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
2206 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
2207 Instruction SLTiuOp> {
2208 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
2209 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
2210 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
2211 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
2214 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
2215 defm : SetlePats<GPR32, SLT, SLTu>;
2216 defm : SetgtPats<GPR32, SLT, SLTu>;
2217 defm : SetgePats<GPR32, SLT, SLTu>;
2218 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
2221 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
2223 // Load halfword/word patterns.
2224 let AddedComplexity = 40 in {
2225 def : LoadRegImmPat<LBu, i32, zextloadi8>;
2226 def : LoadRegImmPat<LH, i32, sextloadi16>;
2227 let AdditionalPredicates = [NotInMicroMips] in {
2228 def : LoadRegImmPat<LW, i32, load>;
2232 // Atomic load patterns.
2233 def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>;
2234 def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>;
2235 def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>;
2237 // Atomic store patterns.
2238 def : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>;
2239 def : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>;
2240 def : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>;
2242 //===----------------------------------------------------------------------===//
2243 // Floating Point Support
2244 //===----------------------------------------------------------------------===//
2246 include "MipsInstrFPU.td"
2247 include "Mips64InstrInfo.td"
2248 include "MipsCondMov.td"
2250 include "Mips32r6InstrInfo.td"
2251 include "Mips64r6InstrInfo.td"
2256 include "Mips16InstrFormats.td"
2257 include "Mips16InstrInfo.td"
2260 include "MipsDSPInstrFormats.td"
2261 include "MipsDSPInstrInfo.td"
2264 include "MipsMSAInstrFormats.td"
2265 include "MipsMSAInstrInfo.td"
2268 include "MipsEVAInstrFormats.td"
2269 include "MipsEVAInstrInfo.td"
2272 include "MicroMipsInstrFormats.td"
2273 include "MicroMipsInstrInfo.td"
2274 include "MicroMipsInstrFPU.td"
2277 include "MicroMips32r6InstrFormats.td"
2278 include "MicroMips32r6InstrInfo.td"
2281 include "MicroMips64r6InstrFormats.td"
2282 include "MicroMips64r6InstrInfo.td"
2285 include "MicroMipsDSPInstrFormats.td"
2286 include "MicroMipsDSPInstrInfo.td"