1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
74 // Node used to insert integers to accumulator.
105 // EXTR.W instrinsic nodes.
115 // DPA.W intrinsic nodes.
151 // DSP setcc and select_cc nodes.
155 // Vector comparisons.
156 // These take a vector and return a boolean.
162 // These take a vector and return a vector bitmask.
169 // Element-wise vector max/min.
175 // Vector Shuffle with mask as an operand
176 VSHF, // Generic shuffle
177 SHF, // 4-element set shuffle.
178 ILVEV, // Interleave even elements
179 ILVOD, // Interleave odd elements
180 ILVL, // Interleave left elements
181 ILVR, // Interleave right elements
183 // Combined (XOR (OR $a, $b), -1)
186 // Extended vector element extraction
190 // Load/Store Left/Right nodes.
191 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
202 //===--------------------------------------------------------------------===//
203 // TargetLowering Implementation
204 //===--------------------------------------------------------------------===//
205 class MipsFunctionInfo;
207 class MipsTargetLowering : public TargetLowering {
209 explicit MipsTargetLowering(MipsTargetMachine &TM);
211 static const MipsTargetLowering *create(MipsTargetMachine &TM);
213 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
215 virtual void LowerOperationWrapper(SDNode *N,
216 SmallVectorImpl<SDValue> &Results,
217 SelectionDAG &DAG) const;
219 /// LowerOperation - Provide custom lowering hooks for some operations.
220 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
222 /// ReplaceNodeResults - Replace the results of node with an illegal result
223 /// type with new values built out of custom code.
225 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
226 SelectionDAG &DAG) const;
228 /// getTargetNodeName - This method returns the name of a target specific
230 virtual const char *getTargetNodeName(unsigned Opcode) const;
232 /// getSetCCResultType - get the ISD::SETCC result ValueType
233 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
235 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
237 virtual MachineBasicBlock *
238 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
241 bool operator()(const char *S1, const char *S2) const {
242 return strcmp(S1, S2) < 0;
247 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
249 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
251 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
253 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
254 unsigned HiFlag, unsigned LoFlag) const;
256 /// This function fills Ops, which is the list of operands that will later
257 /// be used when a function call node is created. It also generates
258 /// copyToReg nodes to set up argument registers.
260 getOpndList(SmallVectorImpl<SDValue> &Ops,
261 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
262 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
263 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
265 /// ByValArgInfo - Byval argument information.
266 struct ByValArgInfo {
267 unsigned FirstIdx; // Index of the first register used.
268 unsigned NumRegs; // Number of registers used for this argument.
269 unsigned Address; // Offset of the stack area used to pass this argument.
271 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
274 /// MipsCC - This class provides methods used to analyze formal and call
275 /// arguments and inquire about calling convention information.
278 enum SpecialCallingConvType {
279 Mips16RetHelperConv, NoSpecialCallingConv
282 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
283 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
286 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
287 bool IsVarArg, bool IsSoftFloat,
288 const SDNode *CallNode,
289 std::vector<ArgListEntry> &FuncArgs);
290 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
292 Function::const_arg_iterator FuncArg);
294 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
295 bool IsSoftFloat, const SDNode *CallNode,
296 const Type *RetTy) const;
298 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
299 bool IsSoftFloat, const Type *RetTy) const;
301 const CCState &getCCInfo() const { return CCInfo; }
303 /// hasByValArg - Returns true if function has byval arguments.
304 bool hasByValArg() const { return !ByValArgs.empty(); }
306 /// regSize - Size (in number of bits) of integer registers.
307 unsigned regSize() const { return IsO32 ? 4 : 8; }
309 /// numIntArgRegs - Number of integer registers available for calls.
310 unsigned numIntArgRegs() const;
312 /// reservedArgArea - The size of the area the caller reserves for
313 /// register arguments. This is 16-byte if ABI is O32.
314 unsigned reservedArgArea() const;
316 /// Return pointer to array of integer argument registers.
317 const uint16_t *intArgRegs() const;
319 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
320 byval_iterator byval_begin() const { return ByValArgs.begin(); }
321 byval_iterator byval_end() const { return ByValArgs.end(); }
324 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
325 CCValAssign::LocInfo LocInfo,
326 ISD::ArgFlagsTy ArgFlags);
328 /// useRegsForByval - Returns true if the calling convention allows the
329 /// use of registers to pass byval arguments.
330 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
332 /// Return the function that analyzes fixed argument list functions.
333 llvm::CCAssignFn *fixedArgFn() const;
335 /// Return the function that analyzes variable argument list functions.
336 llvm::CCAssignFn *varArgFn() const;
338 const uint16_t *shadowRegs() const;
340 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
343 /// Return the type of the register which is used to pass an argument or
344 /// return a value. This function returns f64 if the argument is an i64
345 /// value which has been generated as a result of softening an f128 value.
346 /// Otherwise, it just returns VT.
347 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
348 bool IsSoftFloat) const;
350 template<typename Ty>
351 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
352 const SDNode *CallNode, const Type *RetTy) const;
355 CallingConv::ID CallConv;
357 SpecialCallingConvType SpecialCallingConv;
358 SmallVector<ByValArgInfo, 2> ByValArgs;
361 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
362 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
365 const MipsSubtarget *Subtarget;
367 bool HasMips64, IsN64, IsO32;
371 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
372 // Lower Operand helpers
373 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
374 CallingConv::ID CallConv, bool isVarArg,
375 const SmallVectorImpl<ISD::InputArg> &Ins,
376 SDLoc dl, SelectionDAG &DAG,
377 SmallVectorImpl<SDValue> &InVals,
378 const SDNode *CallNode, const Type *RetTy) const;
380 // Lower Operand specifics
381 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
382 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
383 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
384 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
385 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
386 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
387 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
388 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
389 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
390 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
391 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
392 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
393 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
394 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
395 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
396 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
397 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
398 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
399 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
401 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
402 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
404 /// isEligibleForTailCallOptimization - Check whether the call is eligible
405 /// for tail call optimization.
407 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
408 unsigned NextStackOffset,
409 const MipsFunctionInfo& FI) const = 0;
411 /// copyByValArg - Copy argument registers which were used to pass a byval
412 /// argument to the stack. Create a stack frame object for the byval
414 void copyByValRegs(SDValue Chain, SDLoc DL,
415 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
416 const ISD::ArgFlagsTy &Flags,
417 SmallVectorImpl<SDValue> &InVals,
418 const Argument *FuncArg,
419 const MipsCC &CC, const ByValArgInfo &ByVal) const;
421 /// passByValArg - Pass a byval argument in registers or on stack.
422 void passByValArg(SDValue Chain, SDLoc DL,
423 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
424 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
425 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
426 const MipsCC &CC, const ByValArgInfo &ByVal,
427 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
429 /// writeVarArgRegs - Write variable function arguments passed in registers
430 /// to the stack. Also create a stack frame object for the first variable
432 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
433 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
436 LowerFormalArguments(SDValue Chain,
437 CallingConv::ID CallConv, bool isVarArg,
438 const SmallVectorImpl<ISD::InputArg> &Ins,
439 SDLoc dl, SelectionDAG &DAG,
440 SmallVectorImpl<SDValue> &InVals) const;
442 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
443 SDValue Arg, SDLoc DL, bool IsTailCall,
444 SelectionDAG &DAG) const;
447 LowerCall(TargetLowering::CallLoweringInfo &CLI,
448 SmallVectorImpl<SDValue> &InVals) const;
451 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
453 const SmallVectorImpl<ISD::OutputArg> &Outs,
454 LLVMContext &Context) const;
457 LowerReturn(SDValue Chain,
458 CallingConv::ID CallConv, bool isVarArg,
459 const SmallVectorImpl<ISD::OutputArg> &Outs,
460 const SmallVectorImpl<SDValue> &OutVals,
461 SDLoc dl, SelectionDAG &DAG) const;
463 // Inline asm support
464 ConstraintType getConstraintType(const std::string &Constraint) const;
466 /// Examine constraint string and operand type and determine a weight value.
467 /// The operand object must already have been set up with the operand type.
468 ConstraintWeight getSingleConstraintMatchWeight(
469 AsmOperandInfo &info, const char *constraint) const;
471 /// This function parses registers that appear in inline-asm constraints.
472 /// It returns pair (0, 0) on failure.
473 std::pair<unsigned, const TargetRegisterClass *>
474 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
476 std::pair<unsigned, const TargetRegisterClass*>
477 getRegForInlineAsmConstraint(const std::string &Constraint,
480 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
481 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
482 /// true it means one of the asm constraint of the inline asm instruction
483 /// being processed is 'm'.
484 virtual void LowerAsmOperandForConstraint(SDValue Op,
485 std::string &Constraint,
486 std::vector<SDValue> &Ops,
487 SelectionDAG &DAG) const;
489 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
491 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
493 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
495 bool IsMemset, bool ZeroMemset,
497 MachineFunction &MF) const;
499 /// isFPImmLegal - Returns true if the target can instruction select the
500 /// specified FP immediate natively. If false, the legalizer will
501 /// materialize the FP immediate as a load from a constant pool.
502 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
504 virtual unsigned getJumpTableEncoding() const;
506 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
507 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
508 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
509 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
510 bool Nand = false) const;
511 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
512 MachineBasicBlock *BB, unsigned Size) const;
513 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
514 MachineBasicBlock *BB, unsigned Size) const;
517 /// Create MipsTargetLowering objects.
518 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
519 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
522 #endif // MipsISELLOWERING_H