1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/SSARegMap.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/Support/Debug.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 default : return NULL;
51 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
53 // Mips does not have i1 type, so use i32 for
54 // setcc operations results (slt, sgt, ...).
55 setSetCCResultType(MVT::i32);
56 setSetCCResultContents(ZeroOrOneSetCCResult);
58 // JumpTable targets must use GOT when using PIC_
59 setUsesGlobalOffsetTable(true);
61 // Set up the register classes
62 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
65 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
66 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
67 setOperationAction(ISD::RET, MVT::Other, Custom);
68 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
70 // Load extented operations for i1 types must be promoted
71 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
72 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
73 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
75 // Store operations for i1 types must be promoted
76 setStoreXAction(MVT::i1, Promote);
78 // Mips does not have these NodeTypes below.
79 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
80 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
81 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
82 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
83 setOperationAction(ISD::SELECT, MVT::i32, Expand);
84 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
86 // Mips not supported intrinsics.
87 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
88 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
89 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
91 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
92 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
93 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
94 setOperationAction(ISD::ROTL , MVT::i32, Expand);
95 setOperationAction(ISD::ROTR , MVT::i32, Expand);
96 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
98 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
99 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
100 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
102 // We don't have line number support yet.
103 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
104 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
105 setOperationAction(ISD::LABEL, MVT::Other, Expand);
107 // Use the default for now
108 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
109 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
111 setStackPointerRegisterToSaveRestore(Mips::SP);
112 computeRegisterProperties();
116 SDOperand MipsTargetLowering::
117 LowerOperation(SDOperand Op, SelectionDAG &DAG)
119 switch (Op.getOpcode())
121 case ISD::CALL: return LowerCALL(Op, DAG);
122 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
123 case ISD::RET: return LowerRET(Op, DAG);
124 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
125 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
126 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
131 //===----------------------------------------------------------------------===//
132 // Lower helper functions
133 //===----------------------------------------------------------------------===//
135 // AddLiveIn - This helper function adds the specified physical register to the
136 // MachineFunction as a live in value. It also creates a corresponding
137 // virtual register for it.
139 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
141 assert(RC->contains(PReg) && "Not the correct regclass!");
142 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
143 MF.addLiveIn(PReg, VReg);
147 //===----------------------------------------------------------------------===//
148 // Misc Lower Operation implementation
149 //===----------------------------------------------------------------------===//
150 SDOperand MipsTargetLowering::
151 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
154 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
155 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
156 bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_);
160 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
161 SDOperand Ops[] = { GA };
162 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
163 } else // Emit Load from Global Pointer
164 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
166 // On functions and global targets not internal linked only
167 // a load from got/GP is necessary for PIC to work.
168 if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV))))
171 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
172 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
177 SDOperand MipsTargetLowering::
178 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
180 assert(0 && "TLS not implemented for MIPS.");
183 SDOperand MipsTargetLowering::
184 LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
189 MVT::ValueType PtrVT = Op.getValueType();
190 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
191 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
193 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
194 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
195 SDOperand Ops[] = { JTI };
196 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
197 } else // Emit Load from Global Pointer
198 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
200 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
201 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
206 //===----------------------------------------------------------------------===//
207 // Calling Convention Implementation
209 // The lower operations present on calling convention works on this order:
210 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
211 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
212 // LowerRET (virt regs --> phys regs)
213 // LowerCALL (phys regs --> virt regs)
215 //===----------------------------------------------------------------------===//
217 #include "MipsGenCallingConv.inc"
219 //===----------------------------------------------------------------------===//
220 // CALL Calling Convention Implementation
221 //===----------------------------------------------------------------------===//
223 /// Mips custom CALL implementation
224 SDOperand MipsTargetLowering::
225 LowerCALL(SDOperand Op, SelectionDAG &DAG)
227 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
229 // By now, only CallingConv::C implemented
233 assert(0 && "Unsupported calling convention");
234 case CallingConv::Fast:
236 return LowerCCCCallTo(Op, DAG, CallingConv);
240 /// LowerCCCCallTo - functions arguments are copied from virtual
241 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
242 /// CALLSEQ_END are emitted.
243 /// TODO: isVarArg, isTailCall, sret.
244 SDOperand MipsTargetLowering::
245 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
247 MachineFunction &MF = DAG.getMachineFunction();
248 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
250 SDOperand Chain = Op.getOperand(0);
251 SDOperand Callee = Op.getOperand(4);
252 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
254 MachineFrameInfo *MFI = MF.getFrameInfo();
256 // Analyze operands of the call, assigning locations to each operand.
257 SmallVector<CCValAssign, 16> ArgLocs;
258 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
260 // To meet ABI, Mips must always allocate 16 bytes on
261 // the stack (even if less than 4 are used as arguments)
262 int VTsize = MVT::getSizeInBits(MVT::i32)/8;
263 MFI->CreateFixedObject(VTsize, (VTsize*3));
265 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
267 // Get a count of how many bytes are to be pushed on the stack.
268 unsigned NumBytes = CCInfo.getNextStackOffset();
269 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
272 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
273 SmallVector<SDOperand, 8> MemOpChains;
278 // Walk the register/memloc assignments, inserting copies/loads.
279 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
280 CCValAssign &VA = ArgLocs[i];
282 // Arguments start after the 5 first operands of ISD::CALL
283 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
285 // Promote the value if needed.
286 switch (VA.getLocInfo()) {
287 default: assert(0 && "Unknown loc info!");
288 case CCValAssign::Full: break;
289 case CCValAssign::SExt:
290 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
292 case CCValAssign::ZExt:
293 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
295 case CCValAssign::AExt:
296 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
300 // Arguments that can be passed on register must be kept at
303 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
306 assert(VA.isMemLoc());
308 if (StackPtr.Val == 0)
309 StackPtr = DAG.getRegister(StackReg, getPointerTy());
311 // Create the frame index object for this incoming parameter
312 // This guarantees that when allocating Local Area the firsts
313 // 16 bytes which are alwayes reserved won't be overwritten.
314 LastStackLoc = (16 + VA.getLocMemOffset());
315 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
318 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
320 // emit ISD::STORE whichs stores the
321 // parameter value to a stack Location
322 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
326 // Transform all store nodes into one single node because
327 // all store nodes are independent of each other.
328 if (!MemOpChains.empty())
329 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
330 &MemOpChains[0], MemOpChains.size());
332 // Build a sequence of copy-to-reg nodes chained together with token
333 // chain and flag operands which copy the outgoing args into registers.
334 // The InFlag in necessary since all emited instructions must be
337 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
338 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
339 RegsToPass[i].second, InFlag);
340 InFlag = Chain.getValue(1);
343 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
344 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
345 // node so that legalize doesn't hack it.
346 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
347 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
348 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
349 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
352 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
353 // = Chain, Callee, Reg#1, Reg#2, ...
355 // Returns a chain & a flag for retval copy to use.
356 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
357 SmallVector<SDOperand, 8> Ops;
358 Ops.push_back(Chain);
359 Ops.push_back(Callee);
361 // Add argument registers to the end of the list so that they are
362 // known live into the call.
363 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
364 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
365 RegsToPass[i].second.getValueType()));
368 Ops.push_back(InFlag);
370 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
371 InFlag = Chain.getValue(1);
373 // Create a stack location to hold GP when PIC is used. This stack
374 // location is used on function prologue to save GP and also after all
375 // emited CALL's to restore GP.
376 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
377 // Function can have an arbitrary number of calls, so
378 // hold the LastStackLoc with the biggest offset.
380 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
381 if (LastStackLoc >= MipsFI->getGPStackOffset()) {
382 LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4);
383 // Create the frame index only once. SPOffset here can be anything
384 // (this will be fixed on processFunctionBeforeFrameFinalized)
385 if (MipsFI->getGPStackOffset() == -1) {
386 FI = MFI->CreateFixedObject(4, 0);
389 MipsFI->setGPStackOffset(LastStackLoc);
393 FI = MipsFI->getGPFI();
394 SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
395 SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
396 Chain = GPLoad.getValue(1);
397 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
398 GPLoad, SDOperand(0,0));
401 // Create the CALLSEQ_END node.
402 Chain = DAG.getCALLSEQ_END(Chain,
403 DAG.getConstant(NumBytes, getPointerTy()),
404 DAG.getConstant(0, getPointerTy()),
406 InFlag = Chain.getValue(1);
408 // Handle result values, copying them out of physregs into vregs that we
410 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
413 /// LowerCallResult - Lower the result values of an ISD::CALL into the
414 /// appropriate copies out of appropriate physical registers. This assumes that
415 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
416 /// being lowered. Returns a SDNode with the same number of values as the
418 SDNode *MipsTargetLowering::
419 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
420 unsigned CallingConv, SelectionDAG &DAG) {
422 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
424 // Assign locations to each value returned by this call.
425 SmallVector<CCValAssign, 16> RVLocs;
426 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
428 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
429 SmallVector<SDOperand, 8> ResultVals;
431 // Copy all of the result registers out of their specified physreg.
432 for (unsigned i = 0; i != RVLocs.size(); ++i) {
433 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
434 RVLocs[i].getValVT(), InFlag).getValue(1);
435 InFlag = Chain.getValue(2);
436 ResultVals.push_back(Chain.getValue(0));
439 ResultVals.push_back(Chain);
441 // Merge everything together with a MERGE_VALUES node.
442 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
443 &ResultVals[0], ResultVals.size()).Val;
446 //===----------------------------------------------------------------------===//
447 // FORMAL_ARGUMENTS Calling Convention Implementation
448 //===----------------------------------------------------------------------===//
450 /// Mips custom FORMAL_ARGUMENTS implementation
451 SDOperand MipsTargetLowering::
452 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
454 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
458 assert(0 && "Unsupported calling convention");
460 return LowerCCCArguments(Op, DAG);
464 /// LowerCCCArguments - transform physical registers into
465 /// virtual registers and generate load operations for
466 /// arguments places on the stack.
467 /// TODO: isVarArg, sret
468 SDOperand MipsTargetLowering::
469 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
471 SDOperand Root = Op.getOperand(0);
472 MachineFunction &MF = DAG.getMachineFunction();
473 MachineFrameInfo *MFI = MF.getFrameInfo();
474 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
476 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
477 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
479 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
481 // GP holds the GOT address on PIC calls.
482 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
483 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
485 // Assign locations to all of the incoming arguments.
486 SmallVector<CCValAssign, 16> ArgLocs;
487 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
489 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
490 SmallVector<SDOperand, 8> ArgValues;
493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
495 CCValAssign &VA = ArgLocs[i];
497 // Arguments stored on registers
499 MVT::ValueType RegVT = VA.getLocVT();
500 TargetRegisterClass *RC;
502 if (RegVT == MVT::i32)
503 RC = Mips::CPURegsRegisterClass;
505 assert(0 && "support only Mips::CPURegsRegisterClass");
507 // Transform the arguments stored on
508 // physical registers into virtual ones
509 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
510 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
512 // If this is an 8 or 16-bit value, it is really passed promoted
513 // to 32 bits. Insert an assert[sz]ext to capture this, then
514 // truncate to the right size.
515 if (VA.getLocInfo() == CCValAssign::SExt)
516 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
517 DAG.getValueType(VA.getValVT()));
518 else if (VA.getLocInfo() == CCValAssign::ZExt)
519 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
520 DAG.getValueType(VA.getValVT()));
522 if (VA.getLocInfo() != CCValAssign::Full)
523 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
525 ArgValues.push_back(ArgValue);
527 // To meet ABI, when VARARGS are passed on registers, the registers
528 // must have their values written to the caller stack frame.
531 if (StackPtr.Val == 0)
532 StackPtr = DAG.getRegister(StackReg, getPointerTy());
534 // The stack pointer offset is relative to the caller stack frame.
535 // Since the real stack size is unknown here, a negative SPOffset
536 // is used so there's a way to adjust these offsets when the stack
537 // size get known (on EliminateFrameIndex). A dummy SPOffset is
538 // used instead of a direct negative address (which is recorded to
539 // be used on emitPrologue) to avoid mis-calc of the first stack
540 // offset on PEI::calculateFrameObjectOffsets.
541 // Arguments are always 32-bit.
542 int FI = MFI->CreateFixedObject(4, 0);
543 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
544 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
546 // emit ISD::STORE whichs stores the
547 // parameter value to a stack Location
548 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
553 assert(VA.isMemLoc());
555 // The stack pointer offset is relative to the caller stack frame.
556 // Since the real stack size is unknown here, a negative SPOffset
557 // is used so there's a way to adjust these offsets when the stack
558 // size get known (on EliminateFrameIndex). A dummy SPOffset is
559 // used instead of a direct negative address (which is recorded to
560 // be used on emitPrologue) to avoid mis-calc of the first stack
561 // offset on PEI::calculateFrameObjectOffsets.
562 // Arguments are always 32-bit.
563 int FI = MFI->CreateFixedObject(4, 0);
564 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset())));
566 // Create load nodes to retrieve arguments from the stack
567 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
568 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
571 ArgValues.push_back(Root);
573 // Return the new list of results.
574 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
575 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
578 //===----------------------------------------------------------------------===//
579 // Return Value Calling Convention Implementation
580 //===----------------------------------------------------------------------===//
582 SDOperand MipsTargetLowering::
583 LowerRET(SDOperand Op, SelectionDAG &DAG)
585 // CCValAssign - represent the assignment of
586 // the return value to a location
587 SmallVector<CCValAssign, 16> RVLocs;
588 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
589 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
591 // CCState - Info about the registers and stack slot.
592 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
594 // Analize return values of ISD::RET
595 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
597 // If this is the first return lowered for this function, add
598 // the regs to the liveout set for the function.
599 if (DAG.getMachineFunction().liveout_empty()) {
600 for (unsigned i = 0; i != RVLocs.size(); ++i)
601 if (RVLocs[i].isRegLoc())
602 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
605 // The chain is always operand #0
606 SDOperand Chain = Op.getOperand(0);
609 // Copy the result values into the output registers.
610 for (unsigned i = 0; i != RVLocs.size(); ++i) {
611 CCValAssign &VA = RVLocs[i];
612 assert(VA.isRegLoc() && "Can only return in registers!");
614 // ISD::RET => ret chain, (regnum1,val1), ...
615 // So i*2+1 index only the regnums
616 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
618 // guarantee that all emitted copies are
619 // stuck together, avoiding something bad
620 Flag = Chain.getValue(1);
623 // Return on Mips is always a "jr $ra"
625 return DAG.getNode(MipsISD::Ret, MVT::Other,
626 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
628 return DAG.getNode(MipsISD::Ret, MVT::Other,
629 Chain, DAG.getRegister(Mips::RA, MVT::i32));
632 //===----------------------------------------------------------------------===//
633 // Mips Inline Assembly Support
634 //===----------------------------------------------------------------------===//
636 /// getConstraintType - Given a constraint letter, return the type of
637 /// constraint it is for this target.
638 MipsTargetLowering::ConstraintType MipsTargetLowering::
639 getConstraintType(const std::string &Constraint) const
641 if (Constraint.size() == 1) {
642 // Mips specific constrainy
643 // GCC config/mips/constraints.md
645 // 'd' : An address register. Equivalent to r
646 // unless generating MIPS16 code.
647 // 'y' : Equivalent to r; retained for
648 // backwards compatibility.
650 switch (Constraint[0]) {
654 return C_RegisterClass;
658 return TargetLowering::getConstraintType(Constraint);
661 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
662 getRegForInlineAsmConstraint(const std::string &Constraint,
663 MVT::ValueType VT) const
665 if (Constraint.size() == 1) {
666 switch (Constraint[0]) {
668 return std::make_pair(0U, Mips::CPURegsRegisterClass);
672 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
675 std::vector<unsigned> MipsTargetLowering::
676 getRegClassForInlineAsmConstraint(const std::string &Constraint,
677 MVT::ValueType VT) const
679 if (Constraint.size() != 1)
680 return std::vector<unsigned>();
682 switch (Constraint[0]) {
685 // GCC Mips Constraint Letters
688 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0,
689 Mips::A1, Mips::A2, Mips::A3,
690 Mips::T0, Mips::T1, Mips::T2,
691 Mips::T3, Mips::T4, Mips::T5,
692 Mips::T6, Mips::T7, Mips::S0,
693 Mips::S1, Mips::S2, Mips::S3,
694 Mips::S4, Mips::S5, Mips::S6,
695 Mips::S7, Mips::T8, Mips::T9, 0);
698 return std::vector<unsigned>();