lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
  16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  17 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  18 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  19 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  20 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  21 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  22
  23 // Mips-specific dsp nodes
  24 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  25                                         SDTCisVT<2, untyped>]>;
  26 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  27                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  28 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  29                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  30 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  31                                              SDTCisVT<2, i32>]>;
  32
  33 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  34   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  35
  36 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  37   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  38
  39 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  40 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  41 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  42 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  43 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  44 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  45
  46 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  47 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  48
  49 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  51 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  53 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  54
  55 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  56 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  58 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  59 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  61 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  62 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  63
  64 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  65 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  68 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  71 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  72 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  73
  74 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  75 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  76 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  77 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  78 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  79 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  80 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  82 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  83 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  84 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  85
  86 // Flags.
  87 class Uses<list<Register> Regs> {
  88   list<Register> Uses = Regs;
  89 }
  90
  91 class Defs<list<Register> Regs> {
  92   list<Register> Defs = Regs;
  93 }
  94
  95 // Instruction encoding.
  96 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  97 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  98 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  99 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
 100 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 101 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 102 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 103 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 104 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 105 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 106 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 107 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 108 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 109 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 110 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 111 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 112 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 113 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 114 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 115 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 116 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 117 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 118 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 119 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 120 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 121 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 122 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 123 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 124 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 125 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 126 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 127 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 128 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 129 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 130 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 131 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 132 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 133 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 134 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 135 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 136 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 137 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 138 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 139 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 140 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 141 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 142 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 143 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 144 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 145 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 146 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 147 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 148 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 149 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 150 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 151 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 152 class MFHI_ENC : MFHI_FMT<0b010000>;
 153 class MFLO_ENC : MFHI_FMT<0b010010>;
 154 class MTHI_ENC : MTHI_FMT<0b010001>;
 155 class MTLO_ENC : MTHI_FMT<0b010011>;
 156 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 157 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 158 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 159 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 160 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 161 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 162 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 163 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 164 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 165 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 166 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 167 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 168 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 169 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 170 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 171 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 172 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 173 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 174 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 175 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 176 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 177 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 178 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 179 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 180 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 181 class REPL_QB_ENC : REPL_FMT<0b00010>;
 182 class REPL_PH_ENC : REPL_FMT<0b01010>;
 183 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 184 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 185 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 186 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 187 class LWX_ENC : LX_FMT<0b00000>;
 188 class LHX_ENC : LX_FMT<0b00100>;
 189 class LBUX_ENC : LX_FMT<0b00110>;
 190 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 191 class INSV_ENC : INSV_FMT<0b001100>;
 192
 193 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 194 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 195 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 196 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 197 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 198 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 199 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 200 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 201 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 202 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 203 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 204 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 205 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 206 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 207 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 208
 209 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 210 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 211 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 212 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 213 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 214 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 215 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 216 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 217 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 218 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 219 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 220 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 221 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 222 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 223 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 224 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 225 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 226 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 227 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 228 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 229 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 230 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 231 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 232 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 233 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 234 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 235 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 236 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 237 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 238 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 239 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 240 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 241 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 242 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 243 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 244 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 245 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 246 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 247 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 248 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 249 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 250 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 251 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 252 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 253 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 254 class APPEND_ENC : APPEND_FMT<0b00000>;
 255 class BALIGN_ENC : APPEND_FMT<0b10000>;
 256 class PREPEND_ENC : APPEND_FMT<0b00001>;
 257
 258 // Instruction desc.
 259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 260                         InstrItinClass itin, RegisterOperand ROD,
 261                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 262   dag OutOperandList = (outs ROD:$rd);
 263   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 264   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 265   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 266   InstrItinClass Itinerary = itin;
 267   string BaseOpcode = instr_asm;
 268 }
 269
 270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 271                            InstrItinClass itin, RegisterOperand ROD,
 272                            RegisterOperand ROS = ROD> {
 273   dag OutOperandList = (outs ROD:$rd);
 274   dag InOperandList = (ins ROS:$rs);
 275   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 276   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 277   InstrItinClass Itinerary = itin;
 278   string BaseOpcode = instr_asm;
 279 }
 280
 281 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 282                              InstrItinClass itin, RegisterOperand ROS,
 283                              RegisterOperand ROT = ROS> {
 284   dag OutOperandList = (outs);
 285   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 286   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 287   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 288   InstrItinClass Itinerary = itin;
 289 }
 290
 291 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 292                              InstrItinClass itin, RegisterOperand ROD,
 293                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 294   dag OutOperandList = (outs ROD:$rd);
 295   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 296   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 297   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 298   InstrItinClass Itinerary = itin;
 299   string BaseOpcode = instr_asm;
 300 }
 301
 302 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 303                                InstrItinClass itin, RegisterOperand ROT,
 304                                RegisterOperand ROS = ROT> {
 305   dag OutOperandList = (outs ROT:$rt);
 306   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 307   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 308   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
 309   InstrItinClass Itinerary = itin;
 310   string Constraints = "$src = $rt";
 311   string BaseOpcode = instr_asm;
 312 }
 313
 314 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 315                              InstrItinClass itin, RegisterOperand ROD,
 316                              RegisterOperand ROT = ROD> {
 317   dag OutOperandList = (outs ROD:$rd);
 318   dag InOperandList = (ins ROT:$rt);
 319   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 320   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 321   InstrItinClass Itinerary = itin;
 322   string BaseOpcode = instr_asm;
 323 }
 324
 325 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 326                      ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> {
 327   dag OutOperandList = (outs RO:$rd);
 328   dag InOperandList = (ins uimm16:$imm);
 329   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 330   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 331   InstrItinClass Itinerary = itin;
 332   string BaseOpcode = instr_asm;
 333 }
 334
 335 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 336                            InstrItinClass itin, RegisterOperand RO> {
 337   dag OutOperandList = (outs RO:$rd);
 338   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 339   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 340   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 341   InstrItinClass Itinerary = itin;
 342   string BaseOpcode = instr_asm;
 343 }
 344
 345 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 346                            SDPatternOperator ImmPat, InstrItinClass itin,
 347                            RegisterOperand RO, Operand ImmOpnd> {
 348   dag OutOperandList = (outs RO:$rd);
 349   dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
 350   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 351   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 352   InstrItinClass Itinerary = itin;
 353   bit hasSideEffects = 1;
 354   string BaseOpcode = instr_asm;
 355 }
 356
 357 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 358                    InstrItinClass itin> {
 359   dag OutOperandList = (outs GPR32Opnd:$rd);
 360   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 361   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 362   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 363   InstrItinClass Itinerary = itin;
 364   bit mayLoad = 1;
 365   string BaseOpcode = instr_asm;
 366 }
 367
 368 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 369                          InstrItinClass itin, RegisterOperand ROD,
 370                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
 371   dag OutOperandList = (outs ROD:$rd);
 372   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 373   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 374   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 375   InstrItinClass Itinerary = itin;
 376   string BaseOpcode = instr_asm;
 377 }
 378
 379 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 380                        Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> {
 381   dag OutOperandList = (outs GPR32Opnd:$rt);
 382   dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
 383   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 384   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 385                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];
 386   InstrItinClass Itinerary = itin;
 387   string Constraints = "$src = $rt";
 388   string BaseOpcode = instr_asm;
 389 }
 390
 391 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 392                               InstrItinClass itin> {
 393   dag OutOperandList = (outs GPR32Opnd:$rt);
 394   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 395   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 396   InstrItinClass Itinerary = itin;
 397   string BaseOpcode = instr_asm;
 398 }
 399
 400 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 401                               InstrItinClass itin> {
 402   dag OutOperandList = (outs GPR32Opnd:$rt);
 403   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs);
 404   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 405   InstrItinClass Itinerary = itin;
 406   string BaseOpcode = instr_asm;
 407 }
 408
 409 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 410   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 411   dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin);
 412   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 413   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 414                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 415   string Constraints = "$acin = $ac";
 416 }
 417
 418 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 419   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 420   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 421   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 422   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 423                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 424   string Constraints = "$acin = $ac";
 425 }
 426
 427 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 428   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 429   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 430   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 431   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 432                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 433   string Constraints = "$acin = $ac";
 434   string BaseOpcode = instr_asm;
 435 }
 436
 437 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 438                       InstrItinClass itin> {
 439   dag OutOperandList = (outs GPR32Opnd:$rd);
 440   dag InOperandList = (ins uimm16:$mask);
 441   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 442   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
 443   InstrItinClass Itinerary = itin;
 444   string BaseOpcode = instr_asm;
 445 }
 446
 447 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 448                       InstrItinClass itin> {
 449   dag OutOperandList = (outs);
 450   dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask);
 451   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 452   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
 453   InstrItinClass Itinerary = itin;
 454 }
 455
 456 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 457   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 458   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 459   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 460   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 461                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 462   string Constraints = "$acin = $ac";
 463   string BaseOpcode = instr_asm;
 464 }
 465
 466 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 467                      InstrItinClass itin> {
 468   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 469   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 470   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 471   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 472   InstrItinClass Itinerary = itin;
 473   bit isCommutable = 1;
 474   string BaseOpcode = instr_asm;
 475 }
 476
 477 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 478                      InstrItinClass itin> {
 479   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 480   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 481   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 482   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 483                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 484   InstrItinClass Itinerary = itin;
 485   string Constraints = "$acin = $ac";
 486   string BaseOpcode = instr_asm;
 487 }
 488
 489 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 490                      InstrItinClass itin> {
 491   dag OutOperandList = (outs GPR32Opnd:$rd);
 492   dag InOperandList = (ins RO:$ac);
 493   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 494   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 495   InstrItinClass Itinerary = itin;
 496   string BaseOpcode = instr_asm;
 497 }
 498
 499 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
 500   dag OutOperandList = (outs RO:$ac);
 501   dag InOperandList = (ins GPR32Opnd:$rs);
 502   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 503   InstrItinClass Itinerary = itin;
 504   string BaseOpcode = instr_asm;
 505 }
 506
 507 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 508   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 509   bit usesCustomInserter = 1;
 510 }
 511
 512 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 513   dag OutOperandList = (outs);
 514   dag InOperandList = (ins brtarget:$offset);
 515   string AsmString = !strconcat(instr_asm, "\t$offset");
 516   InstrItinClass Itinerary = itin;
 517   bit isBranch = 1;
 518   bit isTerminator = 1;
 519   bit hasDelaySlot = 1;
 520 }
 521
 522 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 523                      InstrItinClass itin> {
 524   dag OutOperandList = (outs GPR32Opnd:$rt);
 525   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 526   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 527   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 528   InstrItinClass Itinerary = itin;
 529   string Constraints = "$src = $rt";
 530   string BaseOpcode = instr_asm;
 531 }
 532
 533 //===----------------------------------------------------------------------===//
 534 // MIPS DSP Rev 1
 535 //===----------------------------------------------------------------------===//
 536
 537 // Addition/subtraction
 538 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 539                                        DSPROpnd, DSPROpnd>, IsCommutable,
 540                      Defs<[DSPOutFlag20]>;
 541
 542 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 543                                          NoItinerary, DSPROpnd, DSPROpnd>,
 544                        IsCommutable, Defs<[DSPOutFlag20]>;
 545
 546 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 547                                        DSPROpnd, DSPROpnd>,
 548                      Defs<[DSPOutFlag20]>;
 549
 550 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 551                                          NoItinerary, DSPROpnd, DSPROpnd>,
 552                        Defs<[DSPOutFlag20]>;
 553
 554 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 555                                        DSPROpnd, DSPROpnd>, IsCommutable,
 556                      Defs<[DSPOutFlag20]>;
 557
 558 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 559                                          NoItinerary, DSPROpnd, DSPROpnd>,
 560                        IsCommutable, Defs<[DSPOutFlag20]>;
 561
 562 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 563                                        DSPROpnd, DSPROpnd>,
 564                      Defs<[DSPOutFlag20]>;
 565
 566 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 567                                          NoItinerary, DSPROpnd, DSPROpnd>,
 568                        Defs<[DSPOutFlag20]>;
 569
 570 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 571                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 572                       IsCommutable, Defs<[DSPOutFlag20]>;
 573
 574 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 575                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 576                       Defs<[DSPOutFlag20]>;
 577
 578 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 579                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 580                    Defs<[DSPCarry]>;
 581
 582 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 583                                      GPR32Opnd, GPR32Opnd>,
 584                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 585
 586 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 587                                       GPR32Opnd, GPR32Opnd>;
 588
 589 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 590                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 591
 592 // Absolute value
 593 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 594                                               NoItinerary, DSPROpnd>,
 595                        Defs<[DSPOutFlag20]>;
 596
 597 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 598                                              NoItinerary, GPR32Opnd>,
 599                       Defs<[DSPOutFlag20]>;
 600
 601 // Precision reduce/expand
 602 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 603                                                  int_mips_precrq_qb_ph,
 604                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 605
 606 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 607                                                 int_mips_precrq_ph_w,
 608                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 609
 610 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 611                                                    int_mips_precrq_rs_ph_w,
 612                                                    NoItinerary, DSPROpnd,
 613                                                    GPR32Opnd>,
 614                             Defs<[DSPOutFlag22]>;
 615
 616 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 617                                                     int_mips_precrqu_s_qb_ph,
 618                                                     NoItinerary, DSPROpnd,
 619                                                     DSPROpnd>,
 620                              Defs<[DSPOutFlag22]>;
 621
 622 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 623                                                  int_mips_preceq_w_phl,
 624                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 625
 626 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 627                                                  int_mips_preceq_w_phr,
 628                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 629
 630 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 631                                                    int_mips_precequ_ph_qbl,
 632                                                    NoItinerary, DSPROpnd>;
 633
 634 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 635                                                    int_mips_precequ_ph_qbr,
 636                                                    NoItinerary, DSPROpnd>;
 637
 638 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 639                                                     int_mips_precequ_ph_qbla,
 640                                                     NoItinerary, DSPROpnd>;
 641
 642 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 643                                                     int_mips_precequ_ph_qbra,
 644                                                     NoItinerary, DSPROpnd>;
 645
 646 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 647                                                   int_mips_preceu_ph_qbl,
 648                                                   NoItinerary, DSPROpnd>;
 649
 650 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 651                                                   int_mips_preceu_ph_qbr,
 652                                                   NoItinerary, DSPROpnd>;
 653
 654 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 655                                                    int_mips_preceu_ph_qbla,
 656                                                    NoItinerary, DSPROpnd>;
 657
 658 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 659                                                    int_mips_preceu_ph_qbra,
 660                                                    NoItinerary, DSPROpnd>;
 661
 662 // Shift
 663 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 664                                           NoItinerary, DSPROpnd, uimm3>,
 665                      Defs<[DSPOutFlag22]>;
 666
 667 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 668                                            NoItinerary, DSPROpnd>,
 669                       Defs<[DSPOutFlag22]>;
 670
 671 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 672                                           NoItinerary, DSPROpnd, uimm3>;
 673
 674 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 675                                            NoItinerary, DSPROpnd>;
 676
 677 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 678                                           NoItinerary, DSPROpnd, uimm4>,
 679                      Defs<[DSPOutFlag22]>;
 680
 681 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 682                                            NoItinerary, DSPROpnd>,
 683                       Defs<[DSPOutFlag22]>;
 684
 685 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 686                                             immZExt4, NoItinerary, DSPROpnd,
 687                                             uimm4>,
 688                        Defs<[DSPOutFlag22]>;
 689
 690 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 691                                              NoItinerary, DSPROpnd>,
 692                         Defs<[DSPOutFlag22]>;
 693
 694 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 695                                           NoItinerary, DSPROpnd, uimm4>;
 696
 697 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 698                                            NoItinerary, DSPROpnd>;
 699
 700 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 701                                             immZExt4, NoItinerary, DSPROpnd,
 702                                             uimm4>;
 703
 704 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 705                                              NoItinerary, DSPROpnd>;
 706
 707 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 708                                            immZExt5, NoItinerary, GPR32Opnd,
 709                                            uimm5>,
 710                       Defs<[DSPOutFlag22]>;
 711
 712 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 713                                             NoItinerary, GPR32Opnd>,
 714                        Defs<[DSPOutFlag22]>;
 715
 716 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 717                                            immZExt5, NoItinerary, GPR32Opnd,
 718                                            uimm5>;
 719
 720 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 721                                             NoItinerary, GPR32Opnd>;
 722
 723 // Multiplication
 724 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 725                                               int_mips_muleu_s_ph_qbl,
 726                                               NoItinerary, DSPROpnd, DSPROpnd>,
 727                             Defs<[DSPOutFlag21]>;
 728
 729 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 730                                               int_mips_muleu_s_ph_qbr,
 731                                               NoItinerary, DSPROpnd, DSPROpnd>,
 732                             Defs<[DSPOutFlag21]>;
 733
 734 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 735                                              int_mips_muleq_s_w_phl,
 736                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 737                            IsCommutable, Defs<[DSPOutFlag21]>;
 738
 739 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 740                                              int_mips_muleq_s_w_phr,
 741                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 742                            IsCommutable, Defs<[DSPOutFlag21]>;
 743
 744 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 745                                           NoItinerary, DSPROpnd, DSPROpnd>,
 746                         IsCommutable, Defs<[DSPOutFlag21]>;
 747
 748 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 749                                               MipsMULSAQ_S_W_PH>,
 750                            Defs<[DSPOutFlag16_19]>;
 751
 752 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 753                          Defs<[DSPOutFlag16_19]>;
 754
 755 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 756                          Defs<[DSPOutFlag16_19]>;
 757
 758 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 759                           Defs<[DSPOutFlag16_19]>;
 760
 761 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 762                           Defs<[DSPOutFlag16_19]>;
 763
 764 // Move from/to hi/lo.
 765 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
 766 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
 767 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 768 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 769
 770 // Dot product with accumulate/subtract
 771 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 772
 773 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 774
 775 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 776
 777 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 778
 779 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 780                          Defs<[DSPOutFlag16_19]>;
 781
 782 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 783                          Defs<[DSPOutFlag16_19]>;
 784
 785 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 786                          Defs<[DSPOutFlag16_19]>;
 787
 788 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 789                          Defs<[DSPOutFlag16_19]>;
 790
 791 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 792 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 793 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 794 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 795 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 796 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 797
 798 // Comparison
 799 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 800                                                int_mips_cmpu_eq_qb, NoItinerary,
 801                                                DSPROpnd>,
 802                         IsCommutable, Defs<[DSPCCond]>;
 803
 804 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 805                                                int_mips_cmpu_lt_qb, NoItinerary,
 806                                                DSPROpnd>, Defs<[DSPCCond]>;
 807
 808 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 809                                                int_mips_cmpu_le_qb, NoItinerary,
 810                                                DSPROpnd>, Defs<[DSPCCond]>;
 811
 812 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 813                                                 int_mips_cmpgu_eq_qb,
 814                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 815                          IsCommutable;
 816
 817 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 818                                                 int_mips_cmpgu_lt_qb,
 819                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 820
 821 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 822                                                 int_mips_cmpgu_le_qb,
 823                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 824
 825 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 826                                               NoItinerary, DSPROpnd>,
 827                        IsCommutable, Defs<[DSPCCond]>;
 828
 829 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 830                                               NoItinerary, DSPROpnd>,
 831                        Defs<[DSPCCond]>;
 832
 833 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 834                                               NoItinerary, DSPROpnd>,
 835                        Defs<[DSPCCond]>;
 836
 837 // Misc
 838 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 839                                            NoItinerary, GPR32Opnd>;
 840
 841 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 842                                               NoItinerary, DSPROpnd, DSPROpnd>;
 843
 844 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 845                                     NoItinerary, DSPROpnd>;
 846
 847 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 848                                     NoItinerary, DSPROpnd>;
 849
 850 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 851                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 852
 853 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 854                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 855
 856 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 857                                             NoItinerary, DSPROpnd, DSPROpnd>,
 858                      Uses<[DSPCCond]>;
 859
 860 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 861                                             NoItinerary, DSPROpnd, DSPROpnd>,
 862                      Uses<[DSPCCond]>;
 863
 864 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 865
 866 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 867
 868 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 869
 870 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 871
 872 // Extr
 873 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 874                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 875
 876 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 877                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 878
 879 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 880                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 881
 882 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 883                                              NoItinerary>,
 884                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 885
 886 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 887                     Defs<[DSPOutFlag23]>;
 888
 889 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 890                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 891
 892 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 893                                               NoItinerary>,
 894                       Defs<[DSPOutFlag23]>;
 895
 896 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 897                                                NoItinerary>,
 898                        Defs<[DSPOutFlag23]>;
 899
 900 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 901                                                NoItinerary>,
 902                        Defs<[DSPOutFlag23]>;
 903
 904 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 905                                                 NoItinerary>,
 906                         Defs<[DSPOutFlag23]>;
 907
 908 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 909                                               NoItinerary>,
 910                       Defs<[DSPOutFlag23]>;
 911
 912 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 913                                                NoItinerary>,
 914                        Defs<[DSPOutFlag23]>;
 915
 916 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 917
 918 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 919
 920 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 921
 922 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 923
 924 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 925
 926 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 927                   Uses<[DSPPos, DSPSCount]>;
 928
 929 //===----------------------------------------------------------------------===//
 930 // MIPS DSP Rev 2
 931 // Addition/subtraction
 932 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 933                                        DSPROpnd, DSPROpnd>, IsCommutable,
 934                      Defs<[DSPOutFlag20]>;
 935
 936 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 937                                          NoItinerary, DSPROpnd, DSPROpnd>,
 938                        IsCommutable, Defs<[DSPOutFlag20]>;
 939
 940 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 941                                        DSPROpnd, DSPROpnd>,
 942                      Defs<[DSPOutFlag20]>;
 943
 944 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 945                                          NoItinerary, DSPROpnd, DSPROpnd>,
 946                        Defs<[DSPOutFlag20]>;
 947
 948 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 949                                          NoItinerary, DSPROpnd>, IsCommutable;
 950
 951 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 952                                            NoItinerary, DSPROpnd>, IsCommutable;
 953
 954 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 955                                          NoItinerary, DSPROpnd>;
 956
 957 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 958                                            NoItinerary, DSPROpnd>;
 959
 960 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 961                                          NoItinerary, DSPROpnd>, IsCommutable;
 962
 963 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 964                                            NoItinerary, DSPROpnd>, IsCommutable;
 965
 966 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 967                                          NoItinerary, DSPROpnd>;
 968
 969 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 970                                            NoItinerary, DSPROpnd>;
 971
 972 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 973                                         NoItinerary, GPR32Opnd>, IsCommutable;
 974
 975 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 976                                           NoItinerary, GPR32Opnd>, IsCommutable;
 977
 978 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 979                                         NoItinerary, GPR32Opnd>;
 980
 981 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 982                                           NoItinerary, GPR32Opnd>;
 983
 984 // Comparison
 985 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 986                                                  int_mips_cmpgdu_eq_qb,
 987                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 988                           IsCommutable, Defs<[DSPCCond]>;
 989
 990 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 991                                                  int_mips_cmpgdu_lt_qb,
 992                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 993                           Defs<[DSPCCond]>;
 994
 995 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 996                                                  int_mips_cmpgdu_le_qb,
 997                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 998                           Defs<[DSPCCond]>;
 999
1000 // Absolute
1001 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
1002                                               NoItinerary, DSPROpnd>,
1003                        Defs<[DSPOutFlag20]>;
1004
1005 // Multiplication
1006 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
1007                                        DSPROpnd>, IsCommutable,
1008                     Defs<[DSPOutFlag21]>;
1009
1010 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
1011                                          NoItinerary, DSPROpnd>, IsCommutable,
1012                       Defs<[DSPOutFlag21]>;
1013
1014 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
1015                                          NoItinerary, GPR32Opnd>, IsCommutable,
1016                       Defs<[DSPOutFlag21]>;
1017
1018 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1019                                           NoItinerary, GPR32Opnd>, IsCommutable,
1020                        Defs<[DSPOutFlag21]>;
1021
1022 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1023                                          NoItinerary, DSPROpnd, DSPROpnd>,
1024                        IsCommutable, Defs<[DSPOutFlag21]>;
1025
1026 // Dot product with accumulate/subtract
1027 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1028
1029 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1030
1031 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1032                           Defs<[DSPOutFlag16_19]>;
1033
1034 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1035                                               MipsDPAQX_SA_W_PH>,
1036                            Defs<[DSPOutFlag16_19]>;
1037
1038 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1039
1040 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1041
1042 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1043                           Defs<[DSPOutFlag16_19]>;
1044
1045 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1046                                               MipsDPSQX_SA_W_PH>,
1047                            Defs<[DSPOutFlag16_19]>;
1048
1049 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1050
1051 // Precision reduce/expand
1052 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1053                                                 int_mips_precr_qb_ph,
1054                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1055
1056 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1057                                                      int_mips_precr_sra_ph_w,
1058                                                      NoItinerary, DSPROpnd,
1059                                                      GPR32Opnd>;
1060
1061 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1062                                                       int_mips_precr_sra_r_ph_w,
1063                                                        NoItinerary, DSPROpnd,
1064                                                        GPR32Opnd>;
1065
1066 // Shift
1067 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1068                                           NoItinerary, DSPROpnd, uimm3>;
1069
1070 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1071                                            NoItinerary, DSPROpnd>;
1072
1073 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1074                                             immZExt3, NoItinerary, DSPROpnd,
1075                                             uimm3>;
1076
1077 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1078                                              NoItinerary, DSPROpnd>;
1079
1080 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1081                                           NoItinerary, DSPROpnd, uimm4>;
1082
1083 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1084                                            NoItinerary, DSPROpnd>;
1085
1086 // Misc
1087 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, immZExt5,
1088                                      NoItinerary>;
1089
1090 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, immZExt2,
1091                                      NoItinerary>;
1092
1093 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
1094                                       immZExt5, NoItinerary>;
1095
1096 // Pseudos.
1097 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1098                                                 NoItinerary>, Uses<[DSPPos]>;
1099
1100 // Instruction defs.
1101 // MIPS DSP Rev 1
1102 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1103 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1104 def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
1105 def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1106 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1107 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1108 def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
1109 def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1110 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1111 def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1112 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1113 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1114 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1115 def RADDU_W_QB : DspMMRel, RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1116 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1117 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1118 def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1119 def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1120 def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1121 def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1122 def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1123 def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1124 def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1125 def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1126 def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1127 def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1128 def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1129 def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1130 def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1131 def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1132 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1133 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1134 def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
1135 def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
1136 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1137 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1138 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1139 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1140 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
1141 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
1142 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1143 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1144 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1145 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1146 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
1147 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1148 def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1149 def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1150 def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1151 def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1152 def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1153 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1154 def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1155 def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1156 def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1157 def MAQ_SA_W_PHR : DspMMRel, MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1158 def MFHI_DSP : DspMMRel, MFHI_ENC, MFHI_DESC;
1159 def MFLO_DSP : DspMMRel, MFLO_ENC, MFLO_DESC;
1160 def MTHI_DSP : DspMMRel, MTHI_ENC, MTHI_DESC;
1161 def MTLO_DSP : DspMMRel, MTLO_ENC, MTLO_DESC;
1162 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1163 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1164 def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1165 def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1166 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1167 def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1168 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1169 def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1170 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1171 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1172 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1173 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1174 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1175 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1176 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1177 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1178 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1179 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1180 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1181 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1182 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1183 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1184 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1185 def BITREV : BITREV_ENC, BITREV_DESC;
1186 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1187 def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;
1188 def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;
1189 def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC;
1190 def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC;
1191 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1192 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1193 def LWX : DspMMRel, LWX_ENC, LWX_DESC;
1194 def LHX : DspMMRel, LHX_ENC, LHX_DESC;
1195 def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
1196 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1197 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1198 def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
1199 def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
1200 def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
1201 def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
1202 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1203 def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
1204 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1205 def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1206 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1207 def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1208 def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
1209 def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1210 def SHILO : SHILO_ENC, SHILO_DESC;
1211 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1212 def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC;
1213 def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC;
1214 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1215
1216 // MIPS DSP Rev 2
1217 let Predicates = [HasDSPR2] in {
1218
1219 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
1220 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1221 def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC;
1222 def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1223 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1224 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1225 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1226 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1227 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
1228 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1229 def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC;
1230 def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1231 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
1232 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1233 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC;
1234 def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1235 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
1236 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1237 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC;
1238 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1239 def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC;
1240 def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC;
1241 def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC;
1242 def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1243 def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1244 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
1245 def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC;
1246 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1247 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1248 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1249 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1250 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1251 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1252 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1253 def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1254 def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1255 def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1256 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
1257 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC;
1258 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1259 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1260 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC;
1261 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC;
1262 def APPEND : APPEND_ENC, APPEND_DESC;
1263 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1264 def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC;
1265
1266 }
1267
1268 // Pseudos.
1269 let isPseudo = 1, isCodeGenOnly = 1 in {
1270   // Pseudo instructions for loading and storing accumulator registers.
1271   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1272   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1273
1274   // Pseudos for loading and storing ccond field of DSP control register.
1275   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1276   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1277 }
1278
1279 // Pseudo CMP and PICK instructions.
1280 class PseudoCMP<Instruction RealInst> :
1281   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1282   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1283
1284 class PseudoPICK<Instruction RealInst> :
1285   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1286   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1287   NeverHasSideEffects;
1288
1289 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1290 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1291 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1292 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1293 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1294 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1295
1296 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1297 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1298
1299 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1300
1301 // Patterns.
1302 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1303   Pat<pattern, result>, Requires<[pred]>;
1304
1305 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1306                     RegisterClass SrcRC> :
1307    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1308           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1309
1310 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1311 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1312 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1313 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1314
1315 def : DSPPat<(v2i16 (load addr:$a)),
1316              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1317 def : DSPPat<(v4i8 (load addr:$a)),
1318              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1319 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1320              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1321 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1322              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1323
1324 // Binary operations.
1325 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1326                 Predicate Pred = HasDSP> :
1327   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1328
1329 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1330 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1331 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1332 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1333 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1334 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1335 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1336 def : DSPBinPat<ADDU_QB, v4i8, add>;
1337 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1338 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1339 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1340 def : DSPBinPat<ADDSC, i32, addc>;
1341 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1342 def : DSPBinPat<ADDWC, i32, adde>;
1343
1344 // Shift immediate patterns.
1345 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1346                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1347   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1348
1349 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1350 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1351 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1352 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1353 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1354 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1355 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1356 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1357 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1358 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1359 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1360 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1361
1362 // SETCC/SELECT_CC patterns.
1363 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1364                   CondCode CC> :
1365   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1366          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1367                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1368                       (ValTy ZERO)))>;
1369
1370 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1371                      CondCode CC> :
1372   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1373          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1374                       (ValTy ZERO),
1375                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1376
1377 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1378                      CondCode CC> :
1379   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1380          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1381
1382 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1383                         CondCode CC> :
1384   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1385          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1386
1387 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1388 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1389 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1390 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1391 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1392 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1393 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1394 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1395 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1396 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1397 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1398 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1399
1400 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1401 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1402 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1403 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1404 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1405 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1406 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1407 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1408 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1409 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1410 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1411 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1412
1413 // Extr patterns.
1414 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1415   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1416          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1417
1418 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1419   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1420          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1421
1422 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1423 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1424 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1425 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1426 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1427 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1428 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1429 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1430 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1431 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1432 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1433 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1434
1435 // Indexed load patterns.
1436 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1437   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1438          (Instr i32:$base, i32:$index)>;
1439
1440 let AddedComplexity = 20 in {
1441   def : IndexedLoadPat<zextloadi8, LBUX>;
1442   def : IndexedLoadPat<sextloadi16, LHX>;
1443   def : IndexedLoadPat<load, LWX>;
1444 }