lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
  16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  17 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  18 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  19 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  20 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  21 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  22
  23 // Mips-specific dsp nodes
  24 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  25                                         SDTCisVT<2, untyped>]>;
  26 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  27                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  28 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  29                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  30 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  31                                              SDTCisVT<2, i32>]>;
  32
  33 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  34   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  35
  36 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  37   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  38
  39 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  40 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  41 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  42 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  43 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  44 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  45
  46 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  47 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  48
  49 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  51 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  53 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  54
  55 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  56 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  58 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  59 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  61 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  62 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  63
  64 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  65 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  68 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  71 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  72 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  73
  74 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  75 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  76 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  77 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  78 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  79 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  80 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  82 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  83 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  84 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  85
  86 // Flags.
  87 class Uses<list<Register> Regs> {
  88   list<Register> Uses = Regs;
  89 }
  90
  91 class Defs<list<Register> Regs> {
  92   list<Register> Defs = Regs;
  93 }
  94
  95 // Instruction encoding.
  96 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  97 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  98 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  99 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
 100 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 101 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 102 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 103 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 104 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 105 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 106 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 107 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 108 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 109 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 110 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 111 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 112 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 113 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 114 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 115 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 116 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 117 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 118 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 119 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 120 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 121 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 122 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 123 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 124 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 125 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 126 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 127 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 128 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 129 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 130 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 131 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 132 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 133 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 134 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 135 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 136 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 137 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 138 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 139 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 140 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 141 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 142 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 143 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 144 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 145 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 146 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 147 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 148 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 149 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 150 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 151 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 152 class MFHI_ENC : MFHI_FMT<0b010000>;
 153 class MFLO_ENC : MFHI_FMT<0b010010>;
 154 class MTHI_ENC : MTHI_FMT<0b010001>;
 155 class MTLO_ENC : MTHI_FMT<0b010011>;
 156 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 157 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 158 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 159 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 160 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 161 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 162 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 163 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 164 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 165 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 166 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 167 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 168 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 169 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 170 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 171 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 172 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 173 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 174 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 175 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 176 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 177 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 178 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 179 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 180 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 181 class REPL_QB_ENC : REPL_FMT<0b00010>;
 182 class REPL_PH_ENC : REPL_FMT<0b01010>;
 183 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 184 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 185 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 186 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 187 class LWX_ENC : LX_FMT<0b00000>;
 188 class LHX_ENC : LX_FMT<0b00100>;
 189 class LBUX_ENC : LX_FMT<0b00110>;
 190 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 191 class INSV_ENC : INSV_FMT<0b001100>;
 192
 193 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 194 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 195 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 196 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 197 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 198 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 199 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 200 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 201 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 202 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 203 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 204 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 205 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 206 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 207 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 208
 209 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 210 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 211 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 212 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 213 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 214 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 215 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 216 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 217 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 218 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 219 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 220 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 221 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 222 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 223 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 224 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 225 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 226 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 227 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 228 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 229 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 230 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 231 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 232 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 233 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 234 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 235 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 236 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 237 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 238 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 239 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 240 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 241 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 242 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 243 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 244 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 245 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 246 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 247 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 248 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 249 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 250 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 251 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 252 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 253 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 254 class APPEND_ENC : APPEND_FMT<0b00000>;
 255 class BALIGN_ENC : APPEND_FMT<0b10000>;
 256 class PREPEND_ENC : APPEND_FMT<0b00001>;
 257
 258 // Instruction desc.
 259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 260                         InstrItinClass itin, RegisterOperand ROD,
 261                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 262   dag OutOperandList = (outs ROD:$rd);
 263   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 264   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 265   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 266   InstrItinClass Itinerary = itin;
 267   string BaseOpcode = instr_asm;
 268 }
 269
 270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 271                            InstrItinClass itin, RegisterOperand ROD,
 272                            RegisterOperand ROS = ROD> {
 273   dag OutOperandList = (outs ROD:$rd);
 274   dag InOperandList = (ins ROS:$rs);
 275   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 276   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 277   InstrItinClass Itinerary = itin;
 278 }
 279
 280 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 281                              InstrItinClass itin, RegisterOperand ROS,
 282                              RegisterOperand ROT = ROS> {
 283   dag OutOperandList = (outs);
 284   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 285   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 286   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 287   InstrItinClass Itinerary = itin;
 288 }
 289
 290 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 291                              InstrItinClass itin, RegisterOperand ROD,
 292                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 293   dag OutOperandList = (outs ROD:$rd);
 294   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 295   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 296   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 297   InstrItinClass Itinerary = itin;
 298 }
 299
 300 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 301                                InstrItinClass itin, RegisterOperand ROT,
 302                                RegisterOperand ROS = ROT> {
 303   dag OutOperandList = (outs ROT:$rt);
 304   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 305   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 306   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
 307   InstrItinClass Itinerary = itin;
 308   string Constraints = "$src = $rt";
 309 }
 310
 311 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 312                              InstrItinClass itin, RegisterOperand ROD,
 313                              RegisterOperand ROT = ROD> {
 314   dag OutOperandList = (outs ROD:$rd);
 315   dag InOperandList = (ins ROT:$rt);
 316   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 317   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 318   InstrItinClass Itinerary = itin;
 319   string BaseOpcode = instr_asm;
 320 }
 321
 322 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 323                      ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> {
 324   dag OutOperandList = (outs RO:$rd);
 325   dag InOperandList = (ins uimm16:$imm);
 326   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 327   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 328   InstrItinClass Itinerary = itin;
 329 }
 330
 331 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 332                            InstrItinClass itin, RegisterOperand RO> {
 333   dag OutOperandList = (outs RO:$rd);
 334   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 335   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 336   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 337   InstrItinClass Itinerary = itin;
 338   string BaseOpcode = instr_asm;
 339 }
 340
 341 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 342                            SDPatternOperator ImmPat, InstrItinClass itin,
 343                            RegisterOperand RO, Operand ImmOpnd> {
 344   dag OutOperandList = (outs RO:$rd);
 345   dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
 346   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 347   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 348   InstrItinClass Itinerary = itin;
 349   bit hasSideEffects = 1;
 350   string BaseOpcode = instr_asm;
 351 }
 352
 353 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 354                    InstrItinClass itin> {
 355   dag OutOperandList = (outs GPR32Opnd:$rd);
 356   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 357   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 358   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 359   InstrItinClass Itinerary = itin;
 360   bit mayLoad = 1;
 361 }
 362
 363 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 364                          InstrItinClass itin, RegisterOperand ROD,
 365                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
 366   dag OutOperandList = (outs ROD:$rd);
 367   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 368   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 369   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 370   InstrItinClass Itinerary = itin;
 371   string BaseOpcode = instr_asm;
 372 }
 373
 374 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 375                        SDPatternOperator ImmOp, InstrItinClass itin> {
 376   dag OutOperandList = (outs GPR32Opnd:$rt);
 377   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$sa, GPR32Opnd:$src);
 378   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 379   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 380                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, ImmOp:$sa))];
 381   InstrItinClass Itinerary = itin;
 382   string Constraints = "$src = $rt";
 383 }
 384
 385 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 386                               InstrItinClass itin> {
 387   dag OutOperandList = (outs GPR32Opnd:$rt);
 388   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 389   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 390   InstrItinClass Itinerary = itin;
 391   string BaseOpcode = instr_asm;
 392 }
 393
 394 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 395                               InstrItinClass itin> {
 396   dag OutOperandList = (outs GPR32Opnd:$rt);
 397   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs);
 398   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 399   InstrItinClass Itinerary = itin;
 400   string BaseOpcode = instr_asm;
 401 }
 402
 403 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 404   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 405   dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin);
 406   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 407   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 408                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 409   string Constraints = "$acin = $ac";
 410 }
 411
 412 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 413   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 414   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 415   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 416   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 417                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 418   string Constraints = "$acin = $ac";
 419 }
 420
 421 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 422   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 423   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 424   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 425   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 426                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 427   string Constraints = "$acin = $ac";
 428 }
 429
 430 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 431                       InstrItinClass itin> {
 432   dag OutOperandList = (outs GPR32Opnd:$rd);
 433   dag InOperandList = (ins uimm16:$mask);
 434   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 435   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
 436   InstrItinClass Itinerary = itin;
 437 }
 438
 439 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 440                       InstrItinClass itin> {
 441   dag OutOperandList = (outs);
 442   dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask);
 443   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 444   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
 445   InstrItinClass Itinerary = itin;
 446 }
 447
 448 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 449   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 450   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 451   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 452   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 453                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 454   string Constraints = "$acin = $ac";
 455   string BaseOpcode = instr_asm;
 456 }
 457
 458 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 459                      InstrItinClass itin> {
 460   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 461   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 462   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 463   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 464   InstrItinClass Itinerary = itin;
 465   bit isCommutable = 1;
 466   string BaseOpcode = instr_asm;
 467 }
 468
 469 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 470                      InstrItinClass itin> {
 471   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 472   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 473   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 474   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 475                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 476   InstrItinClass Itinerary = itin;
 477   string Constraints = "$acin = $ac";
 478   string BaseOpcode = instr_asm;
 479 }
 480
 481 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 482                      InstrItinClass itin> {
 483   dag OutOperandList = (outs GPR32Opnd:$rd);
 484   dag InOperandList = (ins RO:$ac);
 485   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 486   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 487   InstrItinClass Itinerary = itin;
 488 }
 489
 490 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
 491   dag OutOperandList = (outs RO:$ac);
 492   dag InOperandList = (ins GPR32Opnd:$rs);
 493   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 494   InstrItinClass Itinerary = itin;
 495 }
 496
 497 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 498   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 499   bit usesCustomInserter = 1;
 500 }
 501
 502 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 503   dag OutOperandList = (outs);
 504   dag InOperandList = (ins brtarget:$offset);
 505   string AsmString = !strconcat(instr_asm, "\t$offset");
 506   InstrItinClass Itinerary = itin;
 507   bit isBranch = 1;
 508   bit isTerminator = 1;
 509   bit hasDelaySlot = 1;
 510 }
 511
 512 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 513                      InstrItinClass itin> {
 514   dag OutOperandList = (outs GPR32Opnd:$rt);
 515   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 516   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 517   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 518   InstrItinClass Itinerary = itin;
 519   string Constraints = "$src = $rt";
 520   string BaseOpcode = instr_asm;
 521 }
 522
 523 //===----------------------------------------------------------------------===//
 524 // MIPS DSP Rev 1
 525 //===----------------------------------------------------------------------===//
 526
 527 // Addition/subtraction
 528 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 529                                        DSPROpnd, DSPROpnd>, IsCommutable,
 530                      Defs<[DSPOutFlag20]>;
 531
 532 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 533                                          NoItinerary, DSPROpnd, DSPROpnd>,
 534                        IsCommutable, Defs<[DSPOutFlag20]>;
 535
 536 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 537                                        DSPROpnd, DSPROpnd>,
 538                      Defs<[DSPOutFlag20]>;
 539
 540 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 541                                          NoItinerary, DSPROpnd, DSPROpnd>,
 542                        Defs<[DSPOutFlag20]>;
 543
 544 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 545                                        DSPROpnd, DSPROpnd>, IsCommutable,
 546                      Defs<[DSPOutFlag20]>;
 547
 548 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 549                                          NoItinerary, DSPROpnd, DSPROpnd>,
 550                        IsCommutable, Defs<[DSPOutFlag20]>;
 551
 552 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 553                                        DSPROpnd, DSPROpnd>,
 554                      Defs<[DSPOutFlag20]>;
 555
 556 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 557                                          NoItinerary, DSPROpnd, DSPROpnd>,
 558                        Defs<[DSPOutFlag20]>;
 559
 560 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 561                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 562                       IsCommutable, Defs<[DSPOutFlag20]>;
 563
 564 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 565                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 566                       Defs<[DSPOutFlag20]>;
 567
 568 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 569                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 570                    Defs<[DSPCarry]>;
 571
 572 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 573                                      GPR32Opnd, GPR32Opnd>,
 574                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 575
 576 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 577                                       GPR32Opnd, GPR32Opnd>;
 578
 579 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 580                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 581
 582 // Absolute value
 583 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 584                                               NoItinerary, DSPROpnd>,
 585                        Defs<[DSPOutFlag20]>;
 586
 587 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 588                                              NoItinerary, GPR32Opnd>,
 589                       Defs<[DSPOutFlag20]>;
 590
 591 // Precision reduce/expand
 592 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 593                                                  int_mips_precrq_qb_ph,
 594                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 595
 596 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 597                                                 int_mips_precrq_ph_w,
 598                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 599
 600 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 601                                                    int_mips_precrq_rs_ph_w,
 602                                                    NoItinerary, DSPROpnd,
 603                                                    GPR32Opnd>,
 604                             Defs<[DSPOutFlag22]>;
 605
 606 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 607                                                     int_mips_precrqu_s_qb_ph,
 608                                                     NoItinerary, DSPROpnd,
 609                                                     DSPROpnd>,
 610                              Defs<[DSPOutFlag22]>;
 611
 612 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 613                                                  int_mips_preceq_w_phl,
 614                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 615
 616 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 617                                                  int_mips_preceq_w_phr,
 618                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 619
 620 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 621                                                    int_mips_precequ_ph_qbl,
 622                                                    NoItinerary, DSPROpnd>;
 623
 624 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 625                                                    int_mips_precequ_ph_qbr,
 626                                                    NoItinerary, DSPROpnd>;
 627
 628 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 629                                                     int_mips_precequ_ph_qbla,
 630                                                     NoItinerary, DSPROpnd>;
 631
 632 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 633                                                     int_mips_precequ_ph_qbra,
 634                                                     NoItinerary, DSPROpnd>;
 635
 636 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 637                                                   int_mips_preceu_ph_qbl,
 638                                                   NoItinerary, DSPROpnd>;
 639
 640 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 641                                                   int_mips_preceu_ph_qbr,
 642                                                   NoItinerary, DSPROpnd>;
 643
 644 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 645                                                    int_mips_preceu_ph_qbla,
 646                                                    NoItinerary, DSPROpnd>;
 647
 648 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 649                                                    int_mips_preceu_ph_qbra,
 650                                                    NoItinerary, DSPROpnd>;
 651
 652 // Shift
 653 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 654                                           NoItinerary, DSPROpnd, uimm3>,
 655                      Defs<[DSPOutFlag22]>;
 656
 657 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 658                                            NoItinerary, DSPROpnd>,
 659                       Defs<[DSPOutFlag22]>;
 660
 661 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 662                                           NoItinerary, DSPROpnd, uimm3>;
 663
 664 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 665                                            NoItinerary, DSPROpnd>;
 666
 667 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 668                                           NoItinerary, DSPROpnd, uimm4>,
 669                      Defs<[DSPOutFlag22]>;
 670
 671 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 672                                            NoItinerary, DSPROpnd>,
 673                       Defs<[DSPOutFlag22]>;
 674
 675 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 676                                             immZExt4, NoItinerary, DSPROpnd,
 677                                             uimm4>,
 678                        Defs<[DSPOutFlag22]>;
 679
 680 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 681                                              NoItinerary, DSPROpnd>,
 682                         Defs<[DSPOutFlag22]>;
 683
 684 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 685                                           NoItinerary, DSPROpnd, uimm4>;
 686
 687 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 688                                            NoItinerary, DSPROpnd>;
 689
 690 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 691                                             immZExt4, NoItinerary, DSPROpnd,
 692                                             uimm4>;
 693
 694 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 695                                              NoItinerary, DSPROpnd>;
 696
 697 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 698                                            immZExt5, NoItinerary, GPR32Opnd,
 699                                            uimm5>,
 700                       Defs<[DSPOutFlag22]>;
 701
 702 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 703                                             NoItinerary, GPR32Opnd>,
 704                        Defs<[DSPOutFlag22]>;
 705
 706 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 707                                            immZExt5, NoItinerary, GPR32Opnd,
 708                                            uimm5>;
 709
 710 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 711                                             NoItinerary, GPR32Opnd>;
 712
 713 // Multiplication
 714 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 715                                               int_mips_muleu_s_ph_qbl,
 716                                               NoItinerary, DSPROpnd, DSPROpnd>,
 717                             Defs<[DSPOutFlag21]>;
 718
 719 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 720                                               int_mips_muleu_s_ph_qbr,
 721                                               NoItinerary, DSPROpnd, DSPROpnd>,
 722                             Defs<[DSPOutFlag21]>;
 723
 724 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 725                                              int_mips_muleq_s_w_phl,
 726                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 727                            IsCommutable, Defs<[DSPOutFlag21]>;
 728
 729 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 730                                              int_mips_muleq_s_w_phr,
 731                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 732                            IsCommutable, Defs<[DSPOutFlag21]>;
 733
 734 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 735                                           NoItinerary, DSPROpnd, DSPROpnd>,
 736                         IsCommutable, Defs<[DSPOutFlag21]>;
 737
 738 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 739                                               MipsMULSAQ_S_W_PH>,
 740                            Defs<[DSPOutFlag16_19]>;
 741
 742 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 743                          Defs<[DSPOutFlag16_19]>;
 744
 745 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 746                          Defs<[DSPOutFlag16_19]>;
 747
 748 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 749                           Defs<[DSPOutFlag16_19]>;
 750
 751 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 752                           Defs<[DSPOutFlag16_19]>;
 753
 754 // Move from/to hi/lo.
 755 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
 756 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
 757 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 758 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 759
 760 // Dot product with accumulate/subtract
 761 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 762
 763 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 764
 765 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 766
 767 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 768
 769 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 770                          Defs<[DSPOutFlag16_19]>;
 771
 772 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 773                          Defs<[DSPOutFlag16_19]>;
 774
 775 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 776                          Defs<[DSPOutFlag16_19]>;
 777
 778 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 779                          Defs<[DSPOutFlag16_19]>;
 780
 781 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 782 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 783 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 784 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 785 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 786 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 787
 788 // Comparison
 789 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 790                                                int_mips_cmpu_eq_qb, NoItinerary,
 791                                                DSPROpnd>,
 792                         IsCommutable, Defs<[DSPCCond]>;
 793
 794 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 795                                                int_mips_cmpu_lt_qb, NoItinerary,
 796                                                DSPROpnd>, Defs<[DSPCCond]>;
 797
 798 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 799                                                int_mips_cmpu_le_qb, NoItinerary,
 800                                                DSPROpnd>, Defs<[DSPCCond]>;
 801
 802 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 803                                                 int_mips_cmpgu_eq_qb,
 804                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 805                          IsCommutable;
 806
 807 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 808                                                 int_mips_cmpgu_lt_qb,
 809                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 810
 811 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 812                                                 int_mips_cmpgu_le_qb,
 813                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 814
 815 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 816                                               NoItinerary, DSPROpnd>,
 817                        IsCommutable, Defs<[DSPCCond]>;
 818
 819 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 820                                               NoItinerary, DSPROpnd>,
 821                        Defs<[DSPCCond]>;
 822
 823 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 824                                               NoItinerary, DSPROpnd>,
 825                        Defs<[DSPCCond]>;
 826
 827 // Misc
 828 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 829                                            NoItinerary, GPR32Opnd>;
 830
 831 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 832                                               NoItinerary, DSPROpnd, DSPROpnd>;
 833
 834 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 835                                     NoItinerary, DSPROpnd>;
 836
 837 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 838                                     NoItinerary, DSPROpnd>;
 839
 840 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 841                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 842
 843 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 844                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 845
 846 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 847                                             NoItinerary, DSPROpnd, DSPROpnd>,
 848                      Uses<[DSPCCond]>;
 849
 850 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 851                                             NoItinerary, DSPROpnd, DSPROpnd>,
 852                      Uses<[DSPCCond]>;
 853
 854 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 855
 856 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 857
 858 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 859
 860 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 861
 862 // Extr
 863 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 864                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 865
 866 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 867                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 868
 869 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 870                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 871
 872 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 873                                              NoItinerary>,
 874                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 875
 876 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 877                     Defs<[DSPOutFlag23]>;
 878
 879 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 880                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 881
 882 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 883                                               NoItinerary>,
 884                       Defs<[DSPOutFlag23]>;
 885
 886 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 887                                                NoItinerary>,
 888                        Defs<[DSPOutFlag23]>;
 889
 890 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 891                                                NoItinerary>,
 892                        Defs<[DSPOutFlag23]>;
 893
 894 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 895                                                 NoItinerary>,
 896                         Defs<[DSPOutFlag23]>;
 897
 898 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 899                                               NoItinerary>,
 900                       Defs<[DSPOutFlag23]>;
 901
 902 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 903                                                NoItinerary>,
 904                        Defs<[DSPOutFlag23]>;
 905
 906 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 907
 908 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 909
 910 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 911
 912 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 913
 914 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 915
 916 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 917                   Uses<[DSPPos, DSPSCount]>;
 918
 919 //===----------------------------------------------------------------------===//
 920 // MIPS DSP Rev 2
 921 // Addition/subtraction
 922 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 923                                        DSPROpnd, DSPROpnd>, IsCommutable,
 924                      Defs<[DSPOutFlag20]>;
 925
 926 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 927                                          NoItinerary, DSPROpnd, DSPROpnd>,
 928                        IsCommutable, Defs<[DSPOutFlag20]>;
 929
 930 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 931                                        DSPROpnd, DSPROpnd>,
 932                      Defs<[DSPOutFlag20]>;
 933
 934 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 935                                          NoItinerary, DSPROpnd, DSPROpnd>,
 936                        Defs<[DSPOutFlag20]>;
 937
 938 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 939                                          NoItinerary, DSPROpnd>, IsCommutable;
 940
 941 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 942                                            NoItinerary, DSPROpnd>, IsCommutable;
 943
 944 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 945                                          NoItinerary, DSPROpnd>;
 946
 947 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 948                                            NoItinerary, DSPROpnd>;
 949
 950 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 951                                          NoItinerary, DSPROpnd>, IsCommutable;
 952
 953 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 954                                            NoItinerary, DSPROpnd>, IsCommutable;
 955
 956 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 957                                          NoItinerary, DSPROpnd>;
 958
 959 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 960                                            NoItinerary, DSPROpnd>;
 961
 962 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 963                                         NoItinerary, GPR32Opnd>, IsCommutable;
 964
 965 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 966                                           NoItinerary, GPR32Opnd>, IsCommutable;
 967
 968 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 969                                         NoItinerary, GPR32Opnd>;
 970
 971 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 972                                           NoItinerary, GPR32Opnd>;
 973
 974 // Comparison
 975 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 976                                                  int_mips_cmpgdu_eq_qb,
 977                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 978                           IsCommutable, Defs<[DSPCCond]>;
 979
 980 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 981                                                  int_mips_cmpgdu_lt_qb,
 982                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 983                           Defs<[DSPCCond]>;
 984
 985 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 986                                                  int_mips_cmpgdu_le_qb,
 987                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 988                           Defs<[DSPCCond]>;
 989
 990 // Absolute
 991 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 992                                               NoItinerary, DSPROpnd>,
 993                        Defs<[DSPOutFlag20]>;
 994
 995 // Multiplication
 996 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
 997                                        DSPROpnd>, IsCommutable,
 998                     Defs<[DSPOutFlag21]>;
 999
1000 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
1001                                          NoItinerary, DSPROpnd>, IsCommutable,
1002                       Defs<[DSPOutFlag21]>;
1003
1004 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
1005                                          NoItinerary, GPR32Opnd>, IsCommutable,
1006                       Defs<[DSPOutFlag21]>;
1007
1008 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1009                                           NoItinerary, GPR32Opnd>, IsCommutable,
1010                        Defs<[DSPOutFlag21]>;
1011
1012 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1013                                          NoItinerary, DSPROpnd, DSPROpnd>,
1014                        IsCommutable, Defs<[DSPOutFlag21]>;
1015
1016 // Dot product with accumulate/subtract
1017 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1018
1019 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1020
1021 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1022                           Defs<[DSPOutFlag16_19]>;
1023
1024 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1025                                               MipsDPAQX_SA_W_PH>,
1026                            Defs<[DSPOutFlag16_19]>;
1027
1028 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1029
1030 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1031
1032 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1033                           Defs<[DSPOutFlag16_19]>;
1034
1035 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1036                                               MipsDPSQX_SA_W_PH>,
1037                            Defs<[DSPOutFlag16_19]>;
1038
1039 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1040
1041 // Precision reduce/expand
1042 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1043                                                 int_mips_precr_qb_ph,
1044                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1045
1046 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1047                                                      int_mips_precr_sra_ph_w,
1048                                                      NoItinerary, DSPROpnd,
1049                                                      GPR32Opnd>;
1050
1051 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1052                                                       int_mips_precr_sra_r_ph_w,
1053                                                        NoItinerary, DSPROpnd,
1054                                                        GPR32Opnd>;
1055
1056 // Shift
1057 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1058                                           NoItinerary, DSPROpnd, uimm3>;
1059
1060 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1061                                            NoItinerary, DSPROpnd>;
1062
1063 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1064                                             immZExt3, NoItinerary, DSPROpnd,
1065                                             uimm3>;
1066
1067 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1068                                              NoItinerary, DSPROpnd>;
1069
1070 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1071                                           NoItinerary, DSPROpnd, uimm4>;
1072
1073 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1074                                            NoItinerary, DSPROpnd>;
1075
1076 // Misc
1077 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1078                                      NoItinerary>;
1079
1080 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1081                                      NoItinerary>;
1082
1083 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1084                                       NoItinerary>;
1085
1086 // Pseudos.
1087 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1088                                                 NoItinerary>, Uses<[DSPPos]>;
1089
1090 // Instruction defs.
1091 // MIPS DSP Rev 1
1092 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1093 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1094 def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
1095 def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1096 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1097 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1098 def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
1099 def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1100 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1101 def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1102 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1103 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1104 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1105 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1106 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1107 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1108 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1109 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1110 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1111 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1112 def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1113 def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1114 def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1115 def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1116 def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1117 def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1118 def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1119 def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1120 def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1121 def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1122 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1123 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1124 def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
1125 def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
1126 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1127 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1128 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1129 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1130 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
1131 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
1132 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1133 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1134 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1135 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1136 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
1137 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1138 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1139 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1140 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1141 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1142 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1143 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1144 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1145 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1146 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1147 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1148 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
1149 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
1150 def MTHI_DSP : MTHI_ENC, MTHI_DESC;
1151 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
1152 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1153 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1154 def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1155 def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1156 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1157 def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1158 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1159 def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1160 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1161 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1162 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1163 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1164 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1165 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1166 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1167 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1168 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1169 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1170 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1171 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1172 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1173 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1174 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1175 def BITREV : BITREV_ENC, BITREV_DESC;
1176 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1177 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1178 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1179 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1180 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1181 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1182 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1183 def LWX : LWX_ENC, LWX_DESC;
1184 def LHX : LHX_ENC, LHX_DESC;
1185 def LBUX : LBUX_ENC, LBUX_DESC;
1186 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1187 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1188 def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
1189 def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
1190 def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
1191 def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
1192 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1193 def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
1194 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1195 def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1196 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1197 def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1198 def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
1199 def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1200 def SHILO : SHILO_ENC, SHILO_DESC;
1201 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1202 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1203 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1204 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1205
1206 // MIPS DSP Rev 2
1207 let Predicates = [HasDSPR2] in {
1208
1209 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
1210 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1211 def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC;
1212 def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1213 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1214 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1215 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1216 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1217 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
1218 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1219 def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC;
1220 def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1221 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
1222 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1223 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC;
1224 def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1225 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
1226 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1227 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC;
1228 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1229 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1230 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1231 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1232 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1233 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1234 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
1235 def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC;
1236 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1237 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1238 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1239 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1240 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1241 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1242 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1243 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1244 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1245 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1246 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
1247 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC;
1248 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1249 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1250 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC;
1251 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC;
1252 def APPEND : APPEND_ENC, APPEND_DESC;
1253 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1254 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1255
1256 }
1257
1258 // Pseudos.
1259 let isPseudo = 1, isCodeGenOnly = 1 in {
1260   // Pseudo instructions for loading and storing accumulator registers.
1261   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1262   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1263
1264   // Pseudos for loading and storing ccond field of DSP control register.
1265   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1266   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1267 }
1268
1269 // Pseudo CMP and PICK instructions.
1270 class PseudoCMP<Instruction RealInst> :
1271   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1272   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1273
1274 class PseudoPICK<Instruction RealInst> :
1275   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1276   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1277   NeverHasSideEffects;
1278
1279 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1280 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1281 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1282 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1283 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1284 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1285
1286 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1287 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1288
1289 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1290
1291 // Patterns.
1292 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1293   Pat<pattern, result>, Requires<[pred]>;
1294
1295 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1296                     RegisterClass SrcRC> :
1297    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1298           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1299
1300 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1301 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1302 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1303 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1304
1305 def : DSPPat<(v2i16 (load addr:$a)),
1306              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1307 def : DSPPat<(v4i8 (load addr:$a)),
1308              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1309 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1310              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1311 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1312              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1313
1314 // Binary operations.
1315 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1316                 Predicate Pred = HasDSP> :
1317   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1318
1319 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1320 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1321 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1322 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1323 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1324 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1325 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1326 def : DSPBinPat<ADDU_QB, v4i8, add>;
1327 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1328 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1329 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1330 def : DSPBinPat<ADDSC, i32, addc>;
1331 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1332 def : DSPBinPat<ADDWC, i32, adde>;
1333
1334 // Shift immediate patterns.
1335 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1336                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1337   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1338
1339 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1340 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1341 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1342 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1343 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1344 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1345 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1346 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1347 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1348 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1349 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1350 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1351
1352 // SETCC/SELECT_CC patterns.
1353 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1354                   CondCode CC> :
1355   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1356          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1357                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1358                       (ValTy ZERO)))>;
1359
1360 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1361                      CondCode CC> :
1362   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1363          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1364                       (ValTy ZERO),
1365                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1366
1367 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1368                      CondCode CC> :
1369   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1370          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1371
1372 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1373                         CondCode CC> :
1374   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1375          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1376
1377 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1378 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1379 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1380 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1381 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1382 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1383 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1384 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1385 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1386 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1387 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1388 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1389
1390 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1391 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1392 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1393 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1394 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1395 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1396 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1397 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1398 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1399 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1400 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1401 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1402
1403 // Extr patterns.
1404 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1405   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1406          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1407
1408 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1409   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1410          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1411
1412 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1413 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1414 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1415 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1416 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1417 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1418 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1419 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1420 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1421 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1422 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1423 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1424
1425 // Indexed load patterns.
1426 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1427   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1428          (Instr i32:$base, i32:$index)>;
1429
1430 let AddedComplexity = 20 in {
1431   def : IndexedLoadPat<zextloadi8, LBUX>;
1432   def : IndexedLoadPat<sextloadi16, LHX>;
1433   def : IndexedLoadPat<load, LWX>;
1434 }