1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 def Dsp2MicroMips : InstrMapping {
13 let FilterClass = "DspMMRel";
14 // Instructions with the same BaseOpcode and isNVStore values form a row.
15 let RowFields = ["BaseOpcode"];
16 // Instructions with the same predicate sense form a column.
17 let ColFields = ["Arch"];
18 // The key column is the unpredicated instructions.
20 // Value columns are PredSense=true and PredSense=false
21 let ValueCols = [["dsp"], ["mmdsp"]];
24 def HasDSP : Predicate<"Subtarget->hasDSP()">,
25 AssemblerPredicate<"FeatureDSP">;
26 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
27 AssemblerPredicate<"FeatureDSPR2">;
28 def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
29 AssemblerPredicate<"FeatureDSPR3">;
32 list<Predicate> InsnPredicates = [HasDSPR2];
36 class Field6<bits<6> val> {
40 def SPECIAL3_OPCODE : Field6<0b011111>;
41 def REGIMM_OPCODE : Field6<0b000001>;
43 class DSPInst<string opstr = "">
44 : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
45 let InsnPredicates = [HasDSP];
46 string BaseOpcode = opstr;
50 class PseudoDSP<dag outs, dag ins, list<dag> pattern,
51 InstrItinClass itin = IIPseudo>
52 : MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
53 let InsnPredicates = [HasDSP];
56 class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
57 : InstAlias<Asm, Result, Emit>, PredicateControl {
58 let InsnPredicates = [HasDSP];
61 // ADDU.QB sub-class format.
62 class ADDU_QB_FMT<bits<5> op> : DSPInst {
67 let Opcode = SPECIAL3_OPCODE.V;
73 let Inst{5-0} = 0b010000;
76 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
80 let Opcode = SPECIAL3_OPCODE.V;
86 let Inst{5-0} = 0b010000;
89 // CMPU.EQ.QB sub-class format.
90 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
94 let Opcode = SPECIAL3_OPCODE.V;
100 let Inst{5-0} = 0b010001;
103 class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
108 let Opcode = SPECIAL3_OPCODE.V;
110 let Inst{25-21} = rs;
111 let Inst{20-16} = rt;
112 let Inst{15-11} = rd;
114 let Inst{5-0} = 0b010001;
117 class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
122 let Opcode = SPECIAL3_OPCODE.V;
124 let Inst{25-21} = rs;
125 let Inst{20-16} = rt;
126 let Inst{15-11} = sa;
128 let Inst{5-0} = 0b010001;
131 // ABSQ_S.PH sub-class format.
132 class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
136 let Opcode = SPECIAL3_OPCODE.V;
139 let Inst{20-16} = rt;
140 let Inst{15-11} = rd;
142 let Inst{5-0} = 0b010010;
146 class REPL_FMT<bits<5> op> : DSPInst {
150 let Opcode = SPECIAL3_OPCODE.V;
152 let Inst{25-16} = imm;
153 let Inst{15-11} = rd;
155 let Inst{5-0} = 0b010010;
158 // SHLL.QB sub-class format.
159 class SHLL_QB_FMT<bits<5> op> : DSPInst {
164 let Opcode = SPECIAL3_OPCODE.V;
166 let Inst{25-21} = rs_sa;
167 let Inst{20-16} = rt;
168 let Inst{15-11} = rd;
170 let Inst{5-0} = 0b010011;
173 // LX sub-class format.
174 class LX_FMT<bits<5> op> : DSPInst {
179 let Opcode = SPECIAL3_OPCODE.V;
181 let Inst{25-21} = base;
182 let Inst{20-16} = index;
183 let Inst{15-11} = rd;
185 let Inst{5-0} = 0b001010;
188 // ADDUH.QB sub-class format.
189 class ADDUH_QB_FMT<bits<5> op> : DSPInst {
194 let Opcode = SPECIAL3_OPCODE.V;
196 let Inst{25-21} = rs;
197 let Inst{20-16} = rt;
198 let Inst{15-11} = rd;
200 let Inst{5-0} = 0b011000;
203 // APPEND sub-class format.
204 class APPEND_FMT<bits<5> op> : DSPInst {
209 let Opcode = SPECIAL3_OPCODE.V;
211 let Inst{25-21} = rs;
212 let Inst{20-16} = rt;
213 let Inst{15-11} = sa;
215 let Inst{5-0} = 0b110001;
218 // DPA.W.PH sub-class format.
219 class DPA_W_PH_FMT<bits<5> op> : DSPInst {
224 let Opcode = SPECIAL3_OPCODE.V;
226 let Inst{25-21} = rs;
227 let Inst{20-16} = rt;
229 let Inst{12-11} = ac;
231 let Inst{5-0} = 0b110000;
234 // MULT sub-class format.
235 class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
242 let Inst{25-21} = rs;
243 let Inst{20-16} = rt;
245 let Inst{12-11} = ac;
247 let Inst{5-0} = funct;
250 // MFHI sub-class format.
251 class MFHI_FMT<bits<6> funct> : DSPInst {
257 let Inst{22-21} = ac;
259 let Inst{15-11} = rd;
261 let Inst{5-0} = funct;
264 // MTHI sub-class format.
265 class MTHI_FMT<bits<6> funct> : DSPInst {
270 let Inst{25-21} = rs;
272 let Inst{12-11} = ac;
274 let Inst{5-0} = funct;
277 // EXTR.W sub-class format (type 1).
278 class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
283 let Opcode = SPECIAL3_OPCODE.V;
285 let Inst{25-21} = shift_rs;
286 let Inst{20-16} = rt;
288 let Inst{12-11} = ac;
290 let Inst{5-0} = 0b111000;
293 // SHILO sub-class format.
294 class SHILO_R1_FMT<bits<5> op> : DSPInst {
298 let Opcode = SPECIAL3_OPCODE.V;
300 let Inst{25-20} = shift;
302 let Inst{12-11} = ac;
304 let Inst{5-0} = 0b111000;
307 class SHILO_R2_FMT<bits<5> op> : DSPInst {
311 let Opcode = SPECIAL3_OPCODE.V;
313 let Inst{25-21} = rs;
315 let Inst{12-11} = ac;
317 let Inst{5-0} = 0b111000;
320 class RDDSP_FMT<bits<5> op> : DSPInst {
324 let Opcode = SPECIAL3_OPCODE.V;
326 let Inst{25-16} = mask;
327 let Inst{15-11} = rd;
329 let Inst{5-0} = 0b111000;
332 class WRDSP_FMT<bits<5> op> : DSPInst {
336 let Opcode = SPECIAL3_OPCODE.V;
338 let Inst{25-21} = rs;
339 let Inst{20-11} = mask;
341 let Inst{5-0} = 0b111000;
344 class BPOSGE32_FMT<bits<5> op> : DSPInst {
347 let Opcode = REGIMM_OPCODE.V;
350 let Inst{20-16} = op;
351 let Inst{15-0} = offset;
354 // INSV sub-class format.
355 class INSV_FMT<bits<6> op> : DSPInst {
359 let Opcode = SPECIAL3_OPCODE.V;
361 let Inst{25-21} = rs;
362 let Inst{20-16} = rt;