1 //===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
16 #include "MipsAsmPrinter.h"
18 #include "MipsInstrInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsMCInstLower.h"
21 #include "MipsMCSymbolRefExpr.h"
22 #include "InstPrinter/MipsInstPrinter.h"
23 #include "llvm/BasicBlock.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstr.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCInst.h"
33 #include "llvm/MC/MCSymbol.h"
34 #include "llvm/Target/Mangler.h"
35 #include "llvm/Target/TargetData.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegistry.h"
39 #include "llvm/ADT/SmallString.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/ADT/StringExtras.h"
42 #include "llvm/ADT/Twine.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Analysis/DebugInfo.h"
48 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
50 raw_svector_ostream OS(Str);
52 if (MI->isDebugValue()) {
53 PrintDebugValueComment(MI, OS);
57 MipsMCInstLower MCInstLowering(Mang, *MF, *this);
58 unsigned Opc = MI->getOpcode();
60 // If target is Mips1, expand double precision load/store to two single
61 // precision loads/stores (and delay slot if MI is a load).
62 if (Subtarget->isMips1() && (Opc == Mips::LDC1 || Opc == Mips::SDC1)) {
63 SmallVector<MCInst, 4> MCInsts;
64 const unsigned* SubReg =
65 TM.getRegisterInfo()->getSubRegisters(MI->getOperand(0).getReg());
66 MCInstLowering.LowerMips1F64LoadStore(MI, Opc, MCInsts,
67 Subtarget->isLittle(), SubReg);
69 for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
70 I != MCInsts.end(); ++I)
71 OutStreamer.EmitInstruction(*I);
77 MCInstLowering.Lower(MI, TmpInst0);
79 // Convert aligned loads/stores to their unaligned counterparts.
80 // FIXME: expand other unaligned memory accesses too.
81 if ((Opc == Mips::LW || Opc == Mips::SW) && !MI->memoperands_empty() &&
82 (*MI->memoperands_begin())->getAlignment() < 4) {
84 Directive.setOpcode(Mips::MACRO);
85 OutStreamer.EmitInstruction(Directive);
86 TmpInst0.setOpcode(Opc == Mips::LW ? Mips::ULW : Mips::USW);
87 OutStreamer.EmitInstruction(TmpInst0);
88 Directive.setOpcode(Mips::NOMACRO);
89 OutStreamer.EmitInstruction(Directive);
93 OutStreamer.EmitInstruction(TmpInst0);
96 //===----------------------------------------------------------------------===//
98 // Mips Asm Directives
100 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
101 // Describe the stack frame.
103 // -- Mask directives "(f)mask bitmask, offset"
104 // Tells the assembler which registers are saved and where.
105 // bitmask - contain a little endian bitset indicating which registers are
106 // saved on function prologue (e.g. with a 0x80000000 mask, the
107 // assembler knows the register 31 (RA) is saved at prologue.
108 // offset - the position before stack pointer subtraction indicating where
109 // the first saved register on prologue is located. (e.g. with a
111 // Consider the following function prologue:
114 // .mask 0xc0000000,-8
115 // addiu $sp, $sp, -48
119 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
120 // 30 (FP) are saved at prologue. As the save order on prologue is from
121 // left to right, RA is saved first. A -8 offset means that after the
122 // stack pointer subtration, the first register in the mask (RA) will be
123 // saved at address 48-8=40.
125 //===----------------------------------------------------------------------===//
127 //===----------------------------------------------------------------------===//
129 //===----------------------------------------------------------------------===//
131 // Create a bitmask with all callee saved registers for CPU or Floating Point
132 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
133 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
134 // CPU and FPU Saved Registers Bitmasks
135 unsigned CPUBitmask = 0, FPUBitmask = 0;
136 int CPUTopSavedRegOff, FPUTopSavedRegOff;
138 // Set the CPU and FPU Bitmasks
139 const MachineFrameInfo *MFI = MF->getFrameInfo();
140 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
141 // size of stack area to which FP callee-saved regs are saved.
142 unsigned CPURegSize = Mips::CPURegsRegisterClass->getSize();
143 unsigned FGR32RegSize = Mips::FGR32RegisterClass->getSize();
144 unsigned AFGR64RegSize = Mips::AFGR64RegisterClass->getSize();
145 bool HasAFGR64Reg = false;
146 unsigned CSFPRegsSize = 0;
147 unsigned i, e = CSI.size();
150 for (i = 0; i != e; ++i) {
151 unsigned Reg = CSI[i].getReg();
152 if (Mips::CPURegsRegisterClass->contains(Reg))
155 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
156 if (Mips::AFGR64RegisterClass->contains(Reg)) {
157 FPUBitmask |= (3 << RegNum);
158 CSFPRegsSize += AFGR64RegSize;
163 FPUBitmask |= (1 << RegNum);
164 CSFPRegsSize += FGR32RegSize;
168 for (; i != e; ++i) {
169 unsigned Reg = CSI[i].getReg();
170 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
171 CPUBitmask |= (1 << RegNum);
174 // FP Regs are saved right below where the virtual frame pointer points to.
175 FPUTopSavedRegOff = FPUBitmask ?
176 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
178 // CPU Regs are saved below FP Regs.
179 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
182 O << "\t.mask \t"; printHex32(CPUBitmask, O);
183 O << ',' << CPUTopSavedRegOff << '\n';
186 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
187 O << "," << FPUTopSavedRegOff << '\n';
190 // Print a 32 bit hex number with all numbers.
191 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
193 for (int i = 7; i >= 0; i--)
194 O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
197 //===----------------------------------------------------------------------===//
198 // Frame and Set directives
199 //===----------------------------------------------------------------------===//
202 void MipsAsmPrinter::emitFrameDirective() {
203 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
205 unsigned stackReg = RI.getFrameRegister(*MF);
206 unsigned returnReg = RI.getRARegister();
207 unsigned stackSize = MF->getFrameInfo()->getStackSize();
209 OutStreamer.EmitRawText("\t.frame\t$" +
210 Twine(LowercaseString(MipsInstPrinter::getRegisterName(stackReg))) +
211 "," + Twine(stackSize) + ",$" +
212 Twine(LowercaseString(MipsInstPrinter::getRegisterName(returnReg))));
215 /// Emit Set directives.
216 const char *MipsAsmPrinter::getCurrentABIString() const {
217 switch (Subtarget->getTargetABI()) {
218 case MipsSubtarget::O32: return "abi32";
219 case MipsSubtarget::O64: return "abiO64";
220 case MipsSubtarget::N32: return "abiN32";
221 case MipsSubtarget::N64: return "abi64";
222 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
226 llvm_unreachable("Unknown Mips ABI");
230 void MipsAsmPrinter::EmitFunctionEntryLabel() {
231 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
232 OutStreamer.EmitLabel(CurrentFnSym);
235 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
236 /// the first basic block in the function.
237 void MipsAsmPrinter::EmitFunctionBodyStart() {
238 emitFrameDirective();
240 SmallString<128> Str;
241 raw_svector_ostream OS(Str);
242 printSavedRegsBitmask(OS);
243 OutStreamer.EmitRawText(OS.str());
246 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
247 /// the last basic block in the function.
248 void MipsAsmPrinter::EmitFunctionBodyEnd() {
249 // There are instruction for this macros, but they must
250 // always be at the function end, and we can't emit and
251 // break with BB logic.
252 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
253 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
254 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
258 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
259 /// exactly one predecessor and the control transfer mechanism between
260 /// the predecessor and this block is a fall-through.
261 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
263 // The predecessor has to be immediately before this block.
264 const MachineBasicBlock *Pred = *MBB->pred_begin();
266 // If the predecessor is a switch statement, assume a jump table
267 // implementation, so it is not a fall through.
268 if (const BasicBlock *bb = Pred->getBasicBlock())
269 if (isa<SwitchInst>(bb->getTerminator()))
272 // If this is a landing pad, it isn't a fall through. If it has no preds,
273 // then nothing falls through to it.
274 if (MBB->isLandingPad() || MBB->pred_empty())
277 // If there isn't exactly one predecessor, it can't be a fall through.
278 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
281 if (PI2 != MBB->pred_end())
284 // The predecessor has to be immediately before this block.
285 if (!Pred->isLayoutSuccessor(MBB))
288 // If the block is completely empty, then it definitely does fall through.
292 // Otherwise, check the last instruction.
293 // Check if the last terminator is an unconditional branch.
294 MachineBasicBlock::const_iterator I = Pred->end();
295 while (I != Pred->begin() && !(--I)->getDesc().isTerminator()) ;
297 return !I->getDesc().isBarrier();
300 // Print out an operand for an inline asm expression.
301 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
302 unsigned AsmVariant,const char *ExtraCode,
304 // Does this asm operand have a single letter operand modifier?
305 if (ExtraCode && ExtraCode[0])
306 return true; // Unknown modifier.
308 printOperand(MI, OpNo, O);
312 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
313 unsigned OpNum, unsigned AsmVariant,
314 const char *ExtraCode,
316 if (ExtraCode && ExtraCode[0])
317 return true; // Unknown modifier.
319 const MachineOperand &MO = MI->getOperand(OpNum);
320 assert(MO.isReg() && "unexpected inline asm memory operand");
321 O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
325 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
327 const MachineOperand &MO = MI->getOperand(opNum);
330 if (MO.getTargetFlags())
333 switch(MO.getTargetFlags()) {
334 case MipsII::MO_GPREL: O << "%gp_rel("; break;
335 case MipsII::MO_GOT_CALL: O << "%call16("; break;
336 case MipsII::MO_GOT: O << "%got("; break;
337 case MipsII::MO_ABS_HI: O << "%hi("; break;
338 case MipsII::MO_ABS_LO: O << "%lo("; break;
339 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
340 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
341 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
342 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
345 switch (MO.getType()) {
346 case MachineOperand::MO_Register:
348 << LowercaseString(MipsInstPrinter::getRegisterName(MO.getReg()));
351 case MachineOperand::MO_Immediate:
355 case MachineOperand::MO_MachineBasicBlock:
356 O << *MO.getMBB()->getSymbol();
359 case MachineOperand::MO_GlobalAddress:
360 O << *Mang->getSymbol(MO.getGlobal());
363 case MachineOperand::MO_BlockAddress: {
364 MCSymbol* BA = GetBlockAddressSymbol(MO.getBlockAddress());
369 case MachineOperand::MO_ExternalSymbol:
370 O << *GetExternalSymbolSymbol(MO.getSymbolName());
373 case MachineOperand::MO_JumpTableIndex:
374 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
375 << '_' << MO.getIndex();
378 case MachineOperand::MO_ConstantPoolIndex:
379 O << MAI->getPrivateGlobalPrefix() << "CPI"
380 << getFunctionNumber() << "_" << MO.getIndex();
382 O << "+" << MO.getOffset();
386 llvm_unreachable("<unknown operand type>");
389 if (closeP) O << ")";
392 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
394 const MachineOperand &MO = MI->getOperand(opNum);
396 O << (unsigned short int)MO.getImm();
398 printOperand(MI, opNum, O);
401 void MipsAsmPrinter::
402 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
403 // Load/Store memory operands -- imm($reg)
404 // If PIC target the target is loaded as the
405 // pattern lw $25,%call16($28)
406 printOperand(MI, opNum+1, O);
408 printOperand(MI, opNum, O);
412 void MipsAsmPrinter::
413 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
414 // when using stack locations for not load/store instructions
415 // print the same way as all normal 3 operand instructions.
416 printOperand(MI, opNum, O);
418 printOperand(MI, opNum+1, O);
422 void MipsAsmPrinter::
423 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
424 const char *Modifier) {
425 const MachineOperand& MO = MI->getOperand(opNum);
426 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
429 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
430 // FIXME: Use SwitchSection.
432 // Tell the assembler which ABI we are using
433 OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
435 // TODO: handle O64 ABI
436 if (Subtarget->isABI_EABI()) {
437 if (Subtarget->isGP32bit())
438 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
440 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
443 // return to previous section
444 OutStreamer.EmitRawText(StringRef("\t.previous"));
448 MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
449 // Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
450 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
451 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
452 "Unexpected MachineOperand types");
453 return MachineLocation(MI->getOperand(0).getReg(),
454 MI->getOperand(1).getImm());
457 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
462 // Force static initialization.
463 extern "C" void LLVMInitializeMipsAsmPrinter() {
464 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
465 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);