1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: clo, clz
19 // Reencoded: jr -> jalr
20 // Reencoded: jr.hb -> jalr.hb
23 def brtarget21 : Operand<OtherVT> {
24 let EncoderMethod = "getBranchTarget21OpValue";
25 let OperandType = "OPERAND_PCREL";
26 let DecoderMethod = "DecodeBranchTarget21";
27 let ParserMatchClass = MipsJumpTargetAsmOperand;
30 def brtarget26 : Operand<OtherVT> {
31 let EncoderMethod = "getBranchTarget26OpValue";
32 let OperandType = "OPERAND_PCREL";
33 let DecoderMethod = "DecodeBranchTarget26";
34 let ParserMatchClass = MipsJumpTargetAsmOperand;
37 def jmpoffset16 : Operand<OtherVT> {
38 let EncoderMethod = "getJumpOffset16OpValue";
39 let ParserMatchClass = MipsJumpTargetAsmOperand;
42 def calloffset16 : Operand<iPTR> {
43 let EncoderMethod = "getJumpOffset16OpValue";
44 let ParserMatchClass = MipsJumpTargetAsmOperand;
47 //===----------------------------------------------------------------------===//
49 // Instruction Encodings
51 //===----------------------------------------------------------------------===//
53 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
54 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
55 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
56 class AUI_ENC : AUI_FM;
57 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
59 class BAL_ENC : BAL_FM;
60 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
61 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
62 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
63 DecodeDisambiguates<"AddiGroupBranch">;
64 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
65 DecodeDisambiguatedBy<"DaddiGroupBranch">;
66 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
67 DecodeDisambiguates<"DaddiGroupBranch">;
68 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
69 DecodeDisambiguatedBy<"DaddiGroupBranch">;
71 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
72 DecodeDisambiguates<"BgtzlGroupBranch">;
73 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
74 DecodeDisambiguatedBy<"BlezlGroupBranch">;
75 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
76 DecodeDisambiguatedBy<"BlezGroupBranch">;
77 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
78 DecodeDisambiguates<"BlezlGroupBranch">;
79 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
80 DecodeDisambiguatedBy<"BgtzGroupBranch">;
82 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
83 DecodeDisambiguatedBy<"BlezlGroupBranch">;
84 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
85 DecodeDisambiguates<"BgtzGroupBranch">;
86 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
87 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
89 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
90 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
91 DecodeDisambiguates<"BlezGroupBranch">;
92 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
94 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
95 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
96 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
97 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
99 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
100 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
101 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
102 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
103 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
104 DecodeDisambiguatedBy<"BlezGroupBranch">;
105 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
106 DecodeDisambiguatedBy<"DaddiGroupBranch">;
107 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
108 DecodeDisambiguatedBy<"AddiGroupBranch">;
109 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
110 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
111 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
112 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
113 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
114 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
115 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
116 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
118 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
119 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
120 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
121 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
123 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
124 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
126 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
127 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
129 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
130 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
132 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
133 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
134 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
135 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
137 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
138 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
139 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
140 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
142 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
143 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
144 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
145 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
147 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
148 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
149 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
150 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
152 class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>;
153 class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>;
155 class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>;
156 class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>;
157 class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>;
158 class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;
160 class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
161 class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
163 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
164 RegisterOperand FGROpnd,
165 SDPatternOperator Op = null_frag> {
166 dag OutOperandList = (outs FGRCCOpnd:$fd);
167 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
168 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
169 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
172 //===----------------------------------------------------------------------===//
174 // Instruction Multiclasses
176 //===----------------------------------------------------------------------===//
178 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
179 RegisterOperand FGROpnd>{
180 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
181 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
183 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
184 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
186 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
187 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
189 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
190 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
192 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
193 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd, setolt>,
195 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
196 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
198 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
199 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd, setole>,
201 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
202 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
204 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
205 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
207 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
208 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
210 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
211 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
213 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
214 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
216 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
217 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
219 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
220 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
222 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
223 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
225 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
226 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
230 //===----------------------------------------------------------------------===//
232 // Instruction Descriptions
234 //===----------------------------------------------------------------------===//
236 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
238 dag OutOperandList = (outs GPROpnd:$rs);
239 dag InOperandList = (ins ImmOpnd:$imm);
240 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
241 list<dag> Pattern = [];
244 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
245 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
246 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
248 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
250 dag OutOperandList = (outs GPROpnd:$rd);
251 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
252 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
253 list<dag> Pattern = [];
256 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
258 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
259 dag OutOperandList = (outs GPROpnd:$rs);
260 dag InOperandList = (ins simm16:$imm);
261 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
262 list<dag> Pattern = [];
265 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
266 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
268 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
269 dag OutOperandList = (outs GPROpnd:$rs);
270 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
271 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
272 list<dag> Pattern = [];
275 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
277 class BRANCH_DESC_BASE {
279 bit isTerminator = 1;
280 bit hasDelaySlot = 0;
283 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
284 dag InOperandList = (ins opnd:$offset);
285 dag OutOperandList = (outs);
286 string AsmString = !strconcat(instr_asm, "\t$offset");
290 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
291 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
292 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
293 dag OutOperandList = (outs);
294 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
295 list<Register> Defs = [AT];
298 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
299 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
300 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
301 dag OutOperandList = (outs);
302 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
303 list<Register> Defs = [AT];
306 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
307 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
308 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
309 dag OutOperandList = (outs);
310 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
311 list<Register> Defs = [AT];
314 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
316 bit hasDelaySlot = 1;
317 list<Register> Defs = [RA];
320 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
322 list<Register> Defs = [RA];
325 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
326 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
327 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
328 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
329 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
331 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
332 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
334 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
335 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
337 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
338 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
340 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
341 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
342 dag OutOperandList = (outs);
343 string AsmString = instr_asm;
344 bit hasDelaySlot = 1;
347 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
348 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
350 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
351 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
352 dag OutOperandList = (outs);
353 string AsmString = instr_asm;
354 bit hasDelaySlot = 1;
357 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
358 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
360 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
361 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
363 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
364 RegisterOperand GPROpnd> {
365 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
366 string AsmString = !strconcat(opstr, "\t$rt, $offset");
367 list<dag> Pattern = [];
368 bit isTerminator = 1;
369 bit hasDelaySlot = 0;
370 string DecoderMethod = "DecodeSimm16";
373 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
376 list<Register> Defs = [RA];
379 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
381 list<Register> Defs = [AT];
384 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
386 bit isIndirectBranch = 1;
387 bit hasDelaySlot = 1;
392 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
393 dag OutOperandList = (outs GPROpnd:$rd);
394 dag InOperandList = (ins GPROpnd:$rt);
395 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
396 list<dag> Pattern = [];
399 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
401 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
402 SDPatternOperator Op=null_frag> {
403 dag OutOperandList = (outs GPROpnd:$rd);
404 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
405 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
406 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
408 // This instruction doesn't trap division by zero itself. We must insert
409 // teq instructions as well.
410 bit usesCustomInserter = 1;
413 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
414 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
415 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
416 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
418 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
419 list<Register> Defs = [RA];
422 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
423 list<Register> Defs = [RA];
426 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
427 list<Register> Defs = [RA];
430 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
431 list<Register> Defs = [RA];
434 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
435 list<Register> Defs = [RA];
438 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
439 list<Register> Defs = [RA];
442 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
443 SDPatternOperator Op=null_frag> {
444 dag OutOperandList = (outs GPROpnd:$rd);
445 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
446 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
447 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
450 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
451 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
452 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
453 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
455 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
456 dag OutOperandList = (outs FGROpnd:$fd);
457 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
458 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
459 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
462 string Constraints = "$fd_in = $fd";
465 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
466 // We must insert a SUBREG_TO_REG around $fd_in
467 bit usesCustomInserter = 1;
469 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
471 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
472 dag OutOperandList = (outs GPROpnd:$rd);
473 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
474 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
475 list<dag> Pattern = [];
478 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
479 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
481 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
482 dag OutOperandList = (outs FGROpnd:$fd);
483 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
484 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
485 list<dag> Pattern = [];
486 string Constraints = "$fd_in = $fd";
489 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
490 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
491 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
492 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
494 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
495 dag OutOperandList = (outs FGROpnd:$fd);
496 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
497 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
498 list<dag> Pattern = [];
501 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
502 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
503 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
504 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
506 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
507 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
508 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
509 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
511 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
512 dag OutOperandList = (outs FGROpnd:$fd);
513 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
514 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
515 list<dag> Pattern = [];
518 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
519 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
520 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
521 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
523 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
524 dag OutOperandList = (outs FGROpnd:$fd);
525 dag InOperandList = (ins FGROpnd:$fs);
526 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
527 list<dag> Pattern = [];
530 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
531 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
532 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
533 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
535 class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
536 RegisterOperand GPROpnd> {
537 dag OutOperandList = (outs);
538 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
539 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
540 list<dag> Pattern = [];
543 class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>;
544 class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>;
546 class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
547 dag OutOperandList = (outs COPOpnd:$rt);
548 dag InOperandList = (ins mem_simm11:$addr);
549 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
550 list<dag> Pattern = [];
554 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>;
555 class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>;
557 class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
558 dag OutOperandList = (outs);
559 dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);
560 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
561 list<dag> Pattern = [];
565 class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>;
566 class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>;
568 class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
569 dag OutOperandList = (outs GPROpnd:$rt);
570 dag InOperandList = (ins mem_simm9:$addr);
571 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
572 list<dag> Pattern = [];
576 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd>;
578 class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
579 dag OutOperandList = (outs GPROpnd:$dst);
580 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
581 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
582 list<dag> Pattern = [];
584 string Constraints = "$rt = $dst";
587 class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
589 //===----------------------------------------------------------------------===//
591 // Instruction Definitions
593 //===----------------------------------------------------------------------===//
595 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
596 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
597 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
598 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
599 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
600 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
601 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
602 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
603 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
604 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
605 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
606 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
607 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
608 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
609 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
610 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
611 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
612 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
613 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
614 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
615 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
616 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
617 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
618 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
619 def BLTC; // Also aliased to bgtc with operands swapped
620 def BLTUC; // Also aliased to bgtuc with operands swapped
621 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
622 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
623 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
624 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
625 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
626 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
627 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
628 def CACHE_R6 : CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
629 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
630 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
631 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
632 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
633 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
634 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
635 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
636 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
637 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
638 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
639 def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
640 // def LSA; // See MSA
641 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
642 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
643 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
644 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
645 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
646 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
647 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
648 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
649 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
650 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
651 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
652 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
653 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
654 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
655 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
656 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
657 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
658 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
659 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
660 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
661 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
662 def NAL; // BAL with rd=0
663 def PREF_R6 : PREF_ENC, PREF_DESC, ISA_MIPS32R6;
664 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
665 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
666 def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
667 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
668 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
669 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
670 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
671 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
672 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
673 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
674 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
675 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
676 def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
678 //===----------------------------------------------------------------------===//
680 // Patterns and Pseudo Instructions
682 //===----------------------------------------------------------------------===//
684 // f32 comparisons supported via another comparison
685 def : MipsPat<(setone f32:$lhs, f32:$rhs),
686 (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
687 def : MipsPat<(seto f32:$lhs, f32:$rhs),
688 (NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
689 def : MipsPat<(setune f32:$lhs, f32:$rhs),
690 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
691 def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>,
693 def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>,
695 def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>,
697 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLT_S f32:$lhs, f32:$rhs)>,
699 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLE_S f32:$lhs, f32:$rhs)>,
701 def : MipsPat<(setne f32:$lhs, f32:$rhs),
702 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
704 // f64 comparisons supported via another comparison
705 def : MipsPat<(setone f64:$lhs, f64:$rhs),
706 (NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
707 def : MipsPat<(seto f64:$lhs, f64:$rhs),
708 (NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
709 def : MipsPat<(setune f64:$lhs, f64:$rhs),
710 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
711 def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>,
713 def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>,
715 def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
717 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLT_D f64:$lhs, f64:$rhs)>,
719 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLE_D f64:$lhs, f64:$rhs)>,
721 def : MipsPat<(setne f64:$lhs, f64:$rhs),
722 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
725 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
726 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
728 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
729 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
731 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
732 (OR (SELNEZ i32:$f, i32:$cond), (SELEQZ i32:$t, i32:$cond))>,
734 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
735 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
736 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
738 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
739 (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
740 (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
742 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
744 (OR (SELNEZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
745 (SELEQZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
747 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
749 (OR (SELNEZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
750 (SELEQZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
753 def : MipsPat<(select i32:$cond, i32:$t, immz),
754 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
755 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz),
756 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
757 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
758 (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
759 def : MipsPat<(select i32:$cond, immz, i32:$f),
760 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
761 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f),
762 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
763 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
764 (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;