1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPSr6 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 // Instruction Encodings
18 //===----------------------------------------------------------------------===//
19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
26 class AUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11110>;
27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
28 class AUI_MMR6_ENC : AUI_FM_MMR6;
29 class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
31 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
32 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
33 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
34 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
35 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
36 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
37 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
38 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
39 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
40 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
41 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
42 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
43 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
44 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
45 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
46 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
47 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
48 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
49 class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
50 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
51 class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
52 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
53 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
54 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
55 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
56 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
57 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
58 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
59 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
60 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
61 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
62 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
63 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
64 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
65 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
66 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
67 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
68 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
69 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
70 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
71 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
72 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
74 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
75 RegisterOperand GPROpnd>
76 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
77 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
78 dag OutOperandList = (outs);
79 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
80 list<Register> Defs = [AT];
83 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
85 list<Register> Defs = [RA];
88 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
90 list<Register> Defs = [RA];
93 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
95 list<Register> Defs = [RA];
98 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
100 list<Register> Defs = [RA];
103 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
105 list<Register> Defs = [RA];
108 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
110 list<Register> Defs = [RA];
113 /// Floating Point Instructions
114 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
115 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
116 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
117 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
118 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
119 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
120 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
121 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
122 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
123 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
124 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
125 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
126 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
127 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
128 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
129 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
131 //===----------------------------------------------------------------------===//
133 // Operand Definitions
135 //===----------------------------------------------------------------------===//
137 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
138 let Name = "MemOffsetSimm9GPR";
139 let SuperClasses = [MipsMemAsmOperand];
140 let RenderMethod = "addMemOperands";
141 let ParserMethod = "parseMemOperand";
142 let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
145 def mem_simm9gpr : mem_generic {
146 let MIOperandInfo = (ops ptr_rc, simm9);
147 let EncoderMethod = "getMemEncoding";
148 let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
151 //===----------------------------------------------------------------------===//
153 // Instruction Descriptions
155 //===----------------------------------------------------------------------===//
157 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
158 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
159 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
160 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
161 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
162 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
163 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
165 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
166 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
167 dag InOperandList = (ins opnd:$offset);
168 dag OutOperandList = (outs);
169 string AsmString = !strconcat(instr_asm, "\t$offset");
173 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
175 list<Register> Defs = [RA];
177 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
178 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
179 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
181 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
182 : MMR6Arch<instr_asm> {
183 dag OutOperandList = (outs GPROpnd:$rd);
184 dag InOperandList = (ins GPROpnd:$rt);
185 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
186 list<dag> Pattern = [];
189 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
191 class BRK_MMR6_DESC : BRK_FT<"break">;
193 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
194 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
195 dag OutOperandList = (outs);
196 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
197 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
198 list<dag> Pattern = [];
199 string DecoderMethod = "DecodeCacheOpMM";
202 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
203 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
205 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
206 : MMR6Arch<instr_asm> {
207 dag OutOperandList = (outs GPROpnd:$rt);
208 dag InOperandList = (ins GPROpnd:$rs);
209 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
212 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
213 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
215 class EHB_MMR6_DESC : Barrier<"ehb">;
216 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
218 class ERET_MMR6_DESC : ER_FT<"eret">;
219 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
221 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
222 RegisterOperand GPROpnd>
224 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
225 string AsmString = !strconcat(opstr, "\t$rt, $offset");
226 list<dag> Pattern = [];
227 bit isTerminator = 1;
228 bit hasDelaySlot = 0;
231 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
234 list<Register> Defs = [RA];
237 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
240 list<Register> Defs = [AT];
243 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
244 Operand ImmOpnd> : MMR6Arch<instr_asm> {
245 dag OutOperandList = (outs GPROpnd:$rd);
246 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
247 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
248 list<dag> Pattern = [];
251 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
253 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
254 : MMR6Arch<instr_asm> {
255 dag OutOperandList = (outs GPROpnd:$rt);
256 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
257 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
258 list<dag> Pattern = [];
261 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
263 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
264 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
265 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
266 : MMR6Arch<instr_asm> {
267 dag OutOperandList = (outs GPROpnd:$rt);
268 dag InOperandList = (ins simm16:$imm);
269 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
270 list<dag> Pattern = [];
273 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
274 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
276 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
277 Operand ImmOpnd> : MMR6Arch<instr_asm> {
278 dag OutOperandList = (outs GPROpnd:$rd);
279 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
280 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
281 list<dag> Pattern = [];
284 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
286 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
287 Operand ImmOpnd> : MMR6Arch<instr_asm> {
288 dag OutOperandList = (outs GPROpnd:$rt);
289 dag InOperandList = (ins ImmOpnd:$imm);
290 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
291 list<dag> Pattern = [];
294 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
295 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
297 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
298 : MMR6Arch<instr_asm> {
299 dag OutOperandList = (outs GPROpnd:$rd);
300 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
301 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
302 list<dag> Pattern = [];
305 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
306 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
307 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
308 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
309 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
310 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
311 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
312 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
313 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
314 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
315 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
316 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
317 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
318 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
320 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
321 SDPatternOperator OpNode = null_frag,
322 InstrItinClass Itin = NoItinerary,
323 ComplexPattern Addr = addr> :
324 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
325 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
326 let DecoderMethod = "DecodeMem";
329 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
330 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
332 /// Floating Point Instructions
333 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
334 InstrItinClass Itin, bit isComm,
335 SDPatternOperator OpNode = null_frag> : HARDFLOAT {
336 dag OutOperandList = (outs RC:$fd);
337 dag InOperandList = (ins RC:$ft, RC:$fs);
338 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
339 list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
340 InstrItinClass Itinerary = Itin;
341 bit isCommutable = isComm;
343 class FADD_S_MMR6_DESC
344 : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
345 class FADD_D_MMR6_DESC
346 : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
347 class FSUB_S_MMR6_DESC
348 : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
349 class FSUB_D_MMR6_DESC
350 : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
351 class FMUL_S_MMR6_DESC
352 : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
353 class FMUL_D_MMR6_DESC
354 : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
355 class FDIV_S_MMR6_DESC
356 : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
357 class FDIV_D_MMR6_DESC
358 : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
359 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
360 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
361 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
362 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
364 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
365 RegisterOperand SrcRC, InstrItinClass Itin,
366 SDPatternOperator OpNode = null_frag>
367 : HARDFLOAT, NeverHasSideEffects {
368 dag OutOperandList = (outs DstRC:$ft);
369 dag InOperandList = (ins SrcRC:$fs);
370 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
371 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
372 InstrItinClass Itinerary = Itin;
375 class FMOV_S_MMR6_DESC
376 : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
377 class FMOV_D_MMR6_DESC
378 : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
379 class FNEG_S_MMR6_DESC
380 : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
381 class FNEG_D_MMR6_DESC
382 : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
384 //===----------------------------------------------------------------------===//
386 // Instruction Definitions
388 //===----------------------------------------------------------------------===//
390 let DecoderNamespace = "MicroMipsR6" in {
391 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
392 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
393 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
394 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
396 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
398 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
399 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
400 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
401 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
402 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
403 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
404 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
405 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
407 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
409 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
411 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
413 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
415 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
417 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
419 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
420 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
421 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
422 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
423 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
424 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
425 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
426 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
427 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
428 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
430 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
431 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
432 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
433 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
434 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
435 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
436 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
437 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
438 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
439 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
440 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
441 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
442 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
443 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
444 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
445 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
446 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
448 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
450 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
451 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
452 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
453 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
454 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
455 let DecoderMethod = "DecodeMemMMImm16" in {
456 def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
458 let DecoderMethod = "DecodeMemMMImm9" in {
459 def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
461 /// Floating Point Instructions
462 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
464 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
466 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
468 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
470 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
472 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
474 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
476 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
478 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
480 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
482 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
484 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
486 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
488 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
490 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
492 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
496 //===----------------------------------------------------------------------===//
498 // MicroMips instruction aliases
500 //===----------------------------------------------------------------------===//
502 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
503 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;