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[oota-llvm.git] / lib / Target / Mips / MicroMips32r6InstrInfo.td
1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes microMIPSr6 instructions.
11 //
12 //===----------------------------------------------------------------------===//
13
14 //===----------------------------------------------------------------------===//
15 //
16 // Instruction Encodings
17 //
18 //===----------------------------------------------------------------------===//
19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
26 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
28 class AUI_MMR6_ENC : AUI_FM_MMR6;
29 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
31 class BC16_MMR6_ENC : BC16_FM_MM16R6;
32 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
33 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
34 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
35 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
36 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
37 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
38 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
39 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
40 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
41 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
42 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
43 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
44 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
45 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
46 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
47 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
48 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
49 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
50 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
51 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
52 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
53 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
54 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
55 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
56 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
57 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
58 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
59 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
60 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
61 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
62 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
63 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
64 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
65 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
66 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
67 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
68 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
69 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
70 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
71 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
72 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
73 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
74 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
75 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
76 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
77 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
78 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
79 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
80 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
81 class LB_MMR6_ENC : LB32_FM_MMR6;
82 class LBU_MMR6_ENC : LBU32_FM_MMR6;
83 class LBE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b100>;
84 class LBUE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b000>;
85 class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
86 class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
87 class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
88 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
89 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
90 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
91 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
92 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
93 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
94 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
95 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
96 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
97 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
98 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
99 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
100 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
101 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
102 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
103 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
104 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
105 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
106 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
107 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
108 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
109 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
110 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
111 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
112 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
113 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
114 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
115 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
116 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
117 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
118 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
119 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
120 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
121 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
122
123 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
124 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
125 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
126 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
127 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
128 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
129 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
130 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
131 class LI16_MMR6_ENC : LI_FM_MM16;
132 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
133 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
134 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
135 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
136
137 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
138                                   RegisterOperand GPROpnd>
139     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
140   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
141   dag OutOperandList = (outs);
142   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
143   list<Register> Defs = [AT];
144 }
145
146 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
147                                                       GPR32Opnd> {
148   list<Register> Defs = [RA];
149 }
150
151 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
152                                                       GPR32Opnd> {
153   list<Register> Defs = [RA];
154 }
155
156 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
157                                                       GPR32Opnd> {
158   list<Register> Defs = [RA];
159 }
160
161 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
162                                                       GPR32Opnd> {
163   list<Register> Defs = [RA];
164 }
165
166 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
167                                                       GPR32Opnd> {
168   list<Register> Defs = [RA];
169 }
170
171 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
172                                                       GPR32Opnd> {
173   list<Register> Defs = [RA];
174 }
175
176 /// Floating Point Instructions
177 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
178 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
179 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
180 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
181 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
182 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
183 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
184 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
185 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
186 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
187 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
188 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
189 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
190 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
191 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
192 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
193 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
194 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
195 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
196 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
197 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
198 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
199 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
200 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
201
202 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
203 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
204 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
205 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
206 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
207 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
208 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
209 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
210 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
211 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
212
213 //===----------------------------------------------------------------------===//
214 //
215 // Instruction Descriptions
216 //
217 //===----------------------------------------------------------------------===//
218
219 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
220 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
221 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
222 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
223 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
224 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
225 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
226
227 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
228     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
229   dag InOperandList = (ins opnd:$offset);
230   dag OutOperandList = (outs);
231   string AsmString = !strconcat(instr_asm, "\t$offset");
232   bit isBarrier = 1;
233 }
234
235 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
236   bit isCall = 1;
237   list<Register> Defs = [RA];
238 }
239 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
240
241 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
242                                        !strconcat("bc16", "\t$offset"), [],
243                                        II_BC, FrmI>,
244                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
245   let isBranch = 1;
246   let isTerminator = 1;
247   let isBarrier = 1;
248   let hasDelaySlot = 0;
249   let AdditionalPredicates = [RelocPIC];
250   let Defs = [AT];
251 }
252
253 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
254     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
255   let isBranch = 1;
256   let isTerminator = 1;
257   let hasDelaySlot = 0;
258   let Defs = [AT];
259 }
260 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
261 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
262
263 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
264 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
265
266 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
267     : MMR6Arch<instr_asm> {
268   dag OutOperandList = (outs GPROpnd:$rd);
269   dag InOperandList = (ins GPROpnd:$rt);
270   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
271   list<dag> Pattern = [];
272 }
273
274 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
275
276 class BRK_MMR6_DESC : BRK_FT<"break">;
277
278 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
279                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
280   dag OutOperandList = (outs);
281   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
282   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
283   list<dag> Pattern = [];
284   string DecoderMethod = "DecodeCacheOpMM";
285 }
286
287 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
288 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
289
290 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
291                                   RegisterOperand GPROpnd> :
292                                   CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
293                                   GPROpnd> {
294   string DecoderMethod = "DecodePrefeOpMM";
295 }
296
297 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
298 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
299
300 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
301                             RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
302   dag OutOperandList = (outs GPROpnd:$rt);
303   dag InOperandList = (ins MemOpnd:$addr);
304   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
305   string DecoderMethod = "DecodeLoadByte15";
306   bit mayLoad = 1;
307 }
308 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd>;
309 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd>;
310
311 class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
312                               RegisterOperand GPROpnd>
313     : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd> {
314   let DecoderMethod = "DecodeLoadByte9";
315 }
316 class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd>;
317 class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd>;
318
319 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
320     : MMR6Arch<instr_asm> {
321   dag OutOperandList = (outs GPROpnd:$rt);
322   dag InOperandList = (ins GPROpnd:$rs);
323   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
324 }
325
326 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
327 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
328
329 class EHB_MMR6_DESC : Barrier<"ehb">;
330 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
331
332 class ERET_MMR6_DESC : ER_FT<"eret">;
333 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
334
335 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
336     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
337                       [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
338       MMR6Arch<opstr>, MicroMipsR6Inst16 {
339   let isCall = 1;
340   let hasDelaySlot = 0;
341   let Defs = [RA];
342 }
343 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
344
345 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
346                                      RegisterOperand GPROpnd>
347     : MMR6Arch<opstr> {
348   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
349   string AsmString = !strconcat(opstr, "\t$rt, $offset");
350   list<dag> Pattern = [];
351   bit isTerminator = 1;
352   bit hasDelaySlot = 0;
353 }
354
355 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
356                                                        GPR32Opnd> {
357   bit isCall = 1;
358   list<Register> Defs = [RA];
359 }
360
361 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
362                                                      GPR32Opnd> {
363   bit isBarrier = 1;
364   list<Register> Defs = [AT];
365 }
366
367 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
368     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
369                       [], II_JR, FrmR>,
370       MMR6Arch<opstr>, MicroMipsR6Inst16 {
371   let hasDelaySlot = 0;
372   let isBranch = 1;
373   let isIndirectBranch = 1;
374 }
375 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
376
377 class JRCADDIUSP_MMR6_DESC
378     : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
379                       [], II_JRADDIUSP, FrmR>,
380       MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
381   let hasDelaySlot = 0;
382   let isTerminator = 1;
383   let isBarrier = 1;
384   let isBranch = 1;
385   let isIndirectBranch = 1;
386 }
387
388 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
389                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
390   dag OutOperandList = (outs GPROpnd:$rd);
391   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
392   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
393   list<dag> Pattern = [];
394 }
395
396 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
397
398 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
399     : MMR6Arch<instr_asm> {
400   dag OutOperandList = (outs GPROpnd:$rt);
401   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
402   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
403   list<dag> Pattern = [];
404 }
405
406 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
407
408 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
409 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
410 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
411     : MMR6Arch<instr_asm> {
412   dag OutOperandList = (outs GPROpnd:$rt);
413   dag InOperandList = (ins simm16:$imm);
414   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
415   list<dag> Pattern = [];
416 }
417
418 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
419 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
420
421 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
422                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
423   dag OutOperandList = (outs GPROpnd:$rd);
424   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
425   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
426   list<dag> Pattern = [];
427 }
428
429 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
430
431 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
432                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
433   dag OutOperandList = (outs GPROpnd:$rt);
434   dag InOperandList = (ins ImmOpnd:$imm);
435   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
436   list<dag> Pattern = [];
437 }
438
439 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
440 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
441
442 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
443     : MMR6Arch<instr_asm> {
444   dag OutOperandList = (outs GPROpnd:$rd);
445   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
446   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
447   list<dag> Pattern = [];
448 }
449
450 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
451 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
452 class PAUSE_MMR6_DESC : Barrier<"pause">;
453 class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
454   dag OutOperandList = (outs GPR32Opnd:$rt);
455   dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
456   string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
457   list<dag> Pattern = [];
458   InstrItinClass Itinerary = II_RDHWR;
459   Format Form = FrmR;
460 }
461
462 class WAIT_MMR6_DESC : WaitMM<"wait">;
463 class SSNOP_MMR6_DESC : Barrier<"ssnop">;
464 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
465 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
466 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
467 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
468 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
469 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
470 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
471 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
472 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
473 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
474 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
475 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
476
477 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
478                   SDPatternOperator OpNode = null_frag,
479                   InstrItinClass Itin = NoItinerary,
480                   ComplexPattern Addr = addr> :
481   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
482          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
483   let DecoderMethod = "DecodeMem";
484   let mayStore = 1;
485 }
486 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
487 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
488
489 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
490     : MMR6Arch<instr_asm> {
491   dag InOperandList = (ins RO:$rs);
492   dag OutOperandList = (outs RO:$rt);
493   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
494   list<dag> Pattern = [];
495   Format f = FrmR;
496   string BaseOpcode = instr_asm;
497   bit hasSideEffects = 0;
498 }
499 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
500 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
501
502 /// Floating Point Instructions
503 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
504                             InstrItinClass Itin, bit isComm,
505                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
506   dag OutOperandList = (outs RC:$fd);
507   dag InOperandList = (ins RC:$ft, RC:$fs);
508   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
509   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
510   InstrItinClass Itinerary = Itin;
511   bit isCommutable = isComm;
512 }
513 class FADD_S_MMR6_DESC
514   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
515 class FADD_D_MMR6_DESC
516   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
517 class FSUB_S_MMR6_DESC
518   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
519 class FSUB_D_MMR6_DESC
520   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
521 class FMUL_S_MMR6_DESC
522   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
523 class FMUL_D_MMR6_DESC
524   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
525 class FDIV_S_MMR6_DESC
526   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
527 class FDIV_D_MMR6_DESC
528   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
529 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
530 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
531 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
532 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
533
534 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
535                                RegisterOperand SrcRC, InstrItinClass Itin,
536                                SDPatternOperator OpNode = null_frag>
537                                : HARDFLOAT, NeverHasSideEffects {
538   dag OutOperandList = (outs DstRC:$ft);
539   dag InOperandList = (ins SrcRC:$fs);
540   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
541   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
542   InstrItinClass Itinerary = Itin;
543   Format Form = FrmFR;
544 }
545 class FMOV_S_MMR6_DESC
546   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
547 class FMOV_D_MMR6_DESC
548   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
549 class FNEG_S_MMR6_DESC
550   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
551 class FNEG_D_MMR6_DESC
552   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
553
554 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
555 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
556 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
557 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
558
559 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
560 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
561 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
562 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
563
564 class CVT_MMR6_DESC_BASE<
565     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
566     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
567     : HARDFLOAT, NeverHasSideEffects {
568   dag OutOperandList = (outs DstRC:$ft);
569   dag InOperandList = (ins SrcRC:$fs);
570   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
571   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
572   InstrItinClass Itinerary = Itin;
573   Format Form = FrmFR;
574 }
575
576 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
577                                              II_CVT>;
578 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
579                                              II_CVT>;
580 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
581                                              II_CVT>;
582 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
583                                              II_CVT>;
584 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
585                                              II_CVT>;
586 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
587                                              II_CVT>;
588 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
589                                              II_CVT>, FGR_64;
590 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
591                                              II_CVT>;
592 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
593                                              II_CVT>;
594 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
595                                              II_CVT>, FGR_64;
596
597 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
598                        RegisterOperand FGROpnd> {
599   def CMP_AF_#NAME : POOL32F_CMP_FM<
600       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
601       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
602       ISA_MICROMIPS32R6;
603   def CMP_UN_#NAME : POOL32F_CMP_FM<
604       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
605       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
606       ISA_MICROMIPS32R6;
607   def CMP_EQ_#NAME : POOL32F_CMP_FM<
608       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
609       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
610       ISA_MICROMIPS32R6;
611   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
612       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
613       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
614       ISA_MICROMIPS32R6;
615   def CMP_LT_#NAME : POOL32F_CMP_FM<
616       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
617       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
618       ISA_MICROMIPS32R6;
619   def CMP_ULT_#NAME : POOL32F_CMP_FM<
620       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
621       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
622       ISA_MICROMIPS32R6;
623   def CMP_LE_#NAME : POOL32F_CMP_FM<
624       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
625       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
626       ISA_MICROMIPS32R6;
627   def CMP_ULE_#NAME : POOL32F_CMP_FM<
628       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
629       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
630       ISA_MICROMIPS32R6;
631   def CMP_SAF_#NAME : POOL32F_CMP_FM<
632       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
633       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
634       ISA_MICROMIPS32R6;
635   def CMP_SUN_#NAME : POOL32F_CMP_FM<
636       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
637       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
638       ISA_MICROMIPS32R6;
639   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
640       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
641       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
642       ISA_MICROMIPS32R6;
643   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
644       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
645       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
646       ISA_MICROMIPS32R6;
647   def CMP_SLT_#NAME : POOL32F_CMP_FM<
648       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
649       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
650       ISA_MICROMIPS32R6;
651   def CMP_SULT_#NAME : POOL32F_CMP_FM<
652       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
653       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
654       ISA_MICROMIPS32R6;
655   def CMP_SLE_#NAME : POOL32F_CMP_FM<
656       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
657       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
658       ISA_MICROMIPS32R6;
659   def CMP_SULE_#NAME : POOL32F_CMP_FM<
660       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
661       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
662       ISA_MICROMIPS32R6;
663 }
664
665 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
666                              RegisterOperand SrcRC, InstrItinClass Itin,
667                              SDPatternOperator OpNode = null_frag>
668     : HARDFLOAT, NeverHasSideEffects {
669   dag OutOperandList = (outs DstRC:$ft);
670   dag InOperandList  = (ins SrcRC:$fs);
671   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
672   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
673   InstrItinClass Itinerary = Itin;
674   Format Form = FrmFR;
675   list<Predicate> EncodingPredicates = [HasStdEnc];
676 }
677
678 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
679                                                 II_ABS, fabs>;
680 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
681                                                 II_ABS, fabs>;
682 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
683                                                     FGR32Opnd, II_FLOOR>;
684 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
685                                                     FGR64Opnd, II_FLOOR>;
686 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
687                                                     FGR32Opnd, II_FLOOR>;
688 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
689                                                     AFGR64Opnd, II_FLOOR>;
690 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
691                                                    FGR32Opnd, II_CEIL>;
692 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
693                                                    FGR64Opnd, II_CEIL>;
694 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
695                                                    FGR32Opnd, II_CEIL>;
696 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
697                                                    AFGR64Opnd, II_CEIL>;
698 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
699                                                     FGR32Opnd, II_TRUNC>;
700 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
701                                                     FGR64Opnd, II_TRUNC>;
702 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
703                                                     FGR32Opnd, II_TRUNC>;
704 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
705                                                     AFGR64Opnd, II_TRUNC>;
706 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
707                                                  II_SQRT_S, fsqrt>;
708 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
709                                                  II_SQRT_D, fsqrt>;
710 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
711                                                   FGR32Opnd, II_TRUNC>;
712 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
713                                                   AFGR64Opnd, II_TRUNC>;
714
715 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
716     : Store<opstr, RO>, MMR6Arch<opstr> {
717   let DecoderMethod = "DecodeMemMMImm16";
718 }
719 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
720
721 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
722     : MMR6Arch<instr_asm>, MipsR6Inst {
723   dag OutOperandList = (outs);
724   dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
725   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
726   string DecoderMethod = "DecodeStoreEvaOpMM";
727   bit mayStore = 1;
728 }
729 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
730 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
731 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
732 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
733 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
734             MMR6Arch<instr_asm>, MipsR6Inst {
735   dag OutOperandList = (outs RO:$rt);
736   dag InOperandList = (ins mem_mm_12:$addr);
737   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
738   string DecoderMethod = "DecodeMemMMImm9";
739   bit mayLoad = 1;
740 }
741 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
742 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
743 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
744       MMR6Arch<"addu16">;
745 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
746       MMR6Arch<"and16">;
747 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
748       MMR6Arch<"andi16">;
749 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
750 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
751       MMR6Arch<"or16">;
752 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
753       MMR6Arch<"sll16">;
754 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
755       MMR6Arch<"srl16">;
756 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
757       MicroMipsR6Inst16;
758 class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
759       MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
760 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
761       MicroMipsR6Inst16;
762 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
763       MicroMipsR6Inst16;
764 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
765       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
766 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
767       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
768
769 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
770   dag OutOperandList = (outs GPR32Opnd:$rt);
771   dag InOperandList = (ins mem:$addr);
772   string AsmString = "lw\t$rt, $addr";
773   let DecoderMethod = "DecodeMemMMImm16";
774   let canFoldAsLoad = 1;
775   let mayLoad = 1;
776   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
777   InstrItinClass Itinerary = II_LW;
778 }
779
780 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
781   dag OutOperandList = (outs GPR32Opnd:$rt);
782   dag InOperandList = (ins uimm16:$imm16);
783   string AsmString = "lui\t$rt, $imm16";
784   list<dag> Pattern = [];
785   bit hasSideEffects = 0;
786   bit isReMaterializable = 1;
787   InstrItinClass Itinerary = II_LUI;
788   Format Form = FrmI;
789 }
790
791 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
792   dag OutOperandList = (outs);
793   dag InOperandList = (ins i32imm:$stype);
794   string AsmString = !strconcat("sync", "\t$stype");
795   list<dag> Pattern = [(MipsSync imm:$stype)];
796   InstrItinClass Itinerary = NoItinerary;
797   bit HasSideEffects = 1;
798 }
799
800 class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
801   let DecoderMethod = "DecodeSynciR6";
802 }
803
804 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
805   dag OutOperandList = (outs GPR32Opnd:$rt);
806   dag InOperandList = (ins GPR32Opnd:$rd);
807   string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
808 }
809
810 class SDBBP_MMR6_DESC : MipsR6Inst {
811   dag OutOperandList = (outs);
812   dag InOperandList = (ins uimm20:$code_);
813   string AsmString = !strconcat("sdbbp", "\t$code_");
814   list<dag> Pattern = [];
815 }
816
817 //===----------------------------------------------------------------------===//
818 //
819 // Instruction Definitions
820 //
821 //===----------------------------------------------------------------------===//
822
823 let DecoderNamespace = "MicroMipsR6" in {
824 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
825 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
826 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
827 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
828                    ISA_MICROMIPS32R6;
829 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
830                   ISA_MICROMIPS32R6;
831 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
832 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
833 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
834 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
835 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
836 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
837 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
838 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
839 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
840                    ISA_MICROMIPS32R6;
841 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
842                    ISA_MICROMIPS32R6;
843 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
844                    ISA_MICROMIPS32R6;
845 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
846                    ISA_MICROMIPS32R6;
847 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
848                    ISA_MICROMIPS32R6;
849 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
850                    ISA_MICROMIPS32R6;
851 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
852                    ISA_MICROMIPS32R6;
853 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
854                    ISA_MICROMIPS32R6;
855 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
856                    ISA_MICROMIPS32R6;
857 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
858 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
859 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
860 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
861 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
862 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
863 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
864 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
865 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
866 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
867                   ISA_MICROMIPS32R6;
868 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
869                    ISA_MICROMIPS32R6;
870 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
871 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
872 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
873 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
874                       ISA_MICROMIPS32R6;
875 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
876 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
877 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
878 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
879 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
880 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
881 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
882 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
883 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
884 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
885 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
886 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
887 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
888 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
889 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
890                   ISA_MICROMIPS32R6;
891 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
892                   ISA_MICROMIPS32R6;
893 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
894 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
895 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
896 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
897 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
898                   ISA_MICROMIPS32R6;
899 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
900                   ISA_MICROMIPS32R6;
901 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
902 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
903 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
904 def LBE_MMR6 : R6MMR6Rel, LBE_MMR6_ENC, LBE_MMR6_DESC, ISA_MICROMIPS32R6;
905 def LBUE_MMR6 : R6MMR6Rel, LBUE_MMR6_ENC, LBUE_MMR6_DESC, ISA_MICROMIPS32R6;
906 def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
907 def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
908 def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
909 def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
910 def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
911 def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
912 def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
913                   ISA_MICROMIPS32R6;
914 def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
915 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
916 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
917 let DecoderMethod = "DecodeMemMMImm16" in {
918   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
919 }
920 let DecoderMethod = "DecodeMemMMImm9" in {
921   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
922 }
923 /// Floating Point Instructions
924 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
925                   ISA_MICROMIPS32R6;
926 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
927                   ISA_MICROMIPS32R6;
928 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
929                   ISA_MICROMIPS32R6;
930 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
931                   ISA_MICROMIPS32R6;
932 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
933                   ISA_MICROMIPS32R6;
934 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
935                   ISA_MICROMIPS32R6;
936 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
937                   ISA_MICROMIPS32R6;
938 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
939                   ISA_MICROMIPS32R6;
940 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
941                    ISA_MICROMIPS32R6;
942 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
943                    ISA_MICROMIPS32R6;
944 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
945                    ISA_MICROMIPS32R6;
946 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
947                    ISA_MICROMIPS32R6;
948 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
949                   ISA_MICROMIPS32R6;
950 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
951                   ISA_MICROMIPS32R6;
952 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
953                   ISA_MICROMIPS32R6;
954 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
955                   ISA_MICROMIPS32R6;
956 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
957 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
958 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
959 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
960 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
961                   ISA_MICROMIPS32R6;
962 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
963                   ISA_MICROMIPS32R6;
964 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
965                   ISA_MICROMIPS32R6;
966 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
967                   ISA_MICROMIPS32R6;
968 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
969                    ISA_MICROMIPS32R6;
970 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
971                    ISA_MICROMIPS32R6;
972 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
973                    ISA_MICROMIPS32R6;
974 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
975                    ISA_MICROMIPS32R6;
976 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
977                    ISA_MICROMIPS32R6;
978 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
979                    ISA_MICROMIPS32R6;
980 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
981                    ISA_MICROMIPS32R6;
982 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
983                    ISA_MICROMIPS32R6;
984 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
985                    ISA_MICROMIPS32R6;
986 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
987                    ISA_MICROMIPS32R6;
988 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
989 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
990 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
991 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
992 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
993                      ISA_MICROMIPS32R6;
994 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
995                      ISA_MICROMIPS32R6;
996 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
997                      ISA_MICROMIPS32R6;
998 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
999                      ISA_MICROMIPS32R6;
1000 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1001                     ISA_MICROMIPS32R6;
1002 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1003                     ISA_MICROMIPS32R6;
1004 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1005                     ISA_MICROMIPS32R6;
1006 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1007                     ISA_MICROMIPS32R6;
1008 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1009                      ISA_MICROMIPS32R6;
1010 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1011                      ISA_MICROMIPS32R6;
1012 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1013                      ISA_MICROMIPS32R6;
1014 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1015                      ISA_MICROMIPS32R6;
1016 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
1017                   ISA_MICROMIPS32R6;
1018 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
1019                   ISA_MICROMIPS32R6;
1020 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
1021                    ISA_MICROMIPS32R6;
1022 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
1023                    ISA_MICROMIPS32R6;
1024 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1025 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
1026 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
1027 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1028 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
1029 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
1030 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
1031 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1032 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1033 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1034                   ISA_MICROMIPS32R6;
1035 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1036                   ISA_MICROMIPS32R6;
1037 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1038                   ISA_MICROMIPS32R6;
1039 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1040                   ISA_MICROMIPS32R6;
1041 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1042                   ISA_MICROMIPS32R6;
1043 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1044                   ISA_MICROMIPS32R6;
1045 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1046                   ISA_MICROMIPS32R6;
1047 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1048                    ISA_MICROMIPS32R6;
1049 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1050                 ISA_MICROMIPS32R6;
1051 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1052                   ISA_MICROMIPS32R6;
1053 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1054                    ISA_MICROMIPS32R6;
1055 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1056                   ISA_MICROMIPS32R6;
1057 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1058                  ISA_MICROMIPS32R6;
1059 }
1060
1061 //===----------------------------------------------------------------------===//
1062 //
1063 // MicroMips instruction aliases
1064 //
1065 //===----------------------------------------------------------------------===//
1066
1067 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1068 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1069 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1070                                       !strconcat("b", "\t$offset")> {
1071   string DecoderNamespace = "MicroMipsR6";
1072 }
1073 def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1074 def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1075 def : MipsInstAlias<"rdhwr $rt, $rs",
1076                     (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1077                     ISA_MICROMIPS32R6;
C/C++ LLVM-based compilers that forbids OOTA behaviors