lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def mem_mm_9 : Operand<i32> {
  15   let PrintMethod = "printMemOperand";
  16   let MIOperandInfo = (ops GPR32, simm9);
  17   let EncoderMethod = "getMemEncodingMMImm9";
  18   let ParserMatchClass = MipsMemAsmOperand;
  19   let OperandType = "OPERAND_MEMORY";
  20 }
  21
  22 //===----------------------------------------------------------------------===//
  23 //
  24 // Instruction Encodings
  25 //
  26 //===----------------------------------------------------------------------===//
  27 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  28 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  29 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  30 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  31 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  32 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  33 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  34 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  35 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  36 class AUI_MMR6_ENC : AUI_FM_MMR6;
  37 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  38 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  39 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  40 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  41 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  42 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  43 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  44 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
  45 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
  46 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
  47 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
  48 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
  49 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
  50 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  51 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  52 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
  53 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
  54 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
  55 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
  56 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
  57 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
  58 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
  59 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
  60 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
  61 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
  62 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
  63 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
  64 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
  65 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
  66 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
  67 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
  68 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
  69 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
  70 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
  71 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
  72 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
  73 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
  74 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
  75 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
  76 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
  77 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
  78 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
  79 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
  80 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
  81 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
  82 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
  83 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
  84 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
  85 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
  86 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
  87 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
  88 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
  89 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
  90 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
  91 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
  92 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
  93 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
  94 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
  95 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
  96 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
  97 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
  98 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
  99 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
 100 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
 101 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
 102 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 103 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
 104 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
 105 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 106 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
 107 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
 108 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 109 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 110 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 111
 112 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 113                                   RegisterOperand GPROpnd>
 114     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 115   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 116   dag OutOperandList = (outs);
 117   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 118   list<Register> Defs = [AT];
 119 }
 120
 121 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 122                                                       GPR32Opnd> {
 123   list<Register> Defs = [RA];
 124 }
 125
 126 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 127                                                       GPR32Opnd> {
 128   list<Register> Defs = [RA];
 129 }
 130
 131 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 132                                                       GPR32Opnd> {
 133   list<Register> Defs = [RA];
 134 }
 135
 136 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 137                                                       GPR32Opnd> {
 138   list<Register> Defs = [RA];
 139 }
 140
 141 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 142                                                       GPR32Opnd> {
 143   list<Register> Defs = [RA];
 144 }
 145
 146 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 147                                                       GPR32Opnd> {
 148   list<Register> Defs = [RA];
 149 }
 150
 151 /// Floating Point Instructions
 152 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 153 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
 154 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 155 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
 156 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 157 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
 158 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 159 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
 160 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 161 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 162 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 163 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 164 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 165 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 166 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 167 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
 168 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 169 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 170 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 171 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 172 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 173 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 174 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 175 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 176
 177 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 178 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 179 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 180 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
 181 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
 182 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
 183 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 184 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
 185 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 186 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 187
 188 //===----------------------------------------------------------------------===//
 189 //
 190 // Operand Definitions
 191 //
 192 //===----------------------------------------------------------------------===//
 193
 194 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
 195   let Name = "MemOffsetSimm9GPR";
 196   let SuperClasses = [MipsMemAsmOperand];
 197   let RenderMethod = "addMemOperands";
 198   let ParserMethod = "parseMemOperand";
 199   let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
 200 }
 201
 202 def mem_simm9gpr : mem_generic {
 203   let MIOperandInfo = (ops ptr_rc, simm9);
 204   let EncoderMethod = "getMemEncoding";
 205   let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
 206 }
 207
 208 //===----------------------------------------------------------------------===//
 209 //
 210 // Instruction Descriptions
 211 //
 212 //===----------------------------------------------------------------------===//
 213
 214 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 215 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
 216 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
 217 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
 218 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
 219 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
 220 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
 221
 222 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
 223     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 224   dag InOperandList = (ins opnd:$offset);
 225   dag OutOperandList = (outs);
 226   string AsmString = !strconcat(instr_asm, "\t$offset");
 227   bit isBarrier = 1;
 228 }
 229
 230 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
 231   bit isCall = 1;
 232   list<Register> Defs = [RA];
 233 }
 234 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
 235
 236 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 237                                        !strconcat("bc16", "\t$offset"), [],
 238                                        IIBranch, FrmI>,
 239                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
 240   let isBranch = 1;
 241   let isTerminator = 1;
 242   let isBarrier = 1;
 243   let hasDelaySlot = 0;
 244   let AdditionalPredicates = [RelocPIC];
 245   let Defs = [AT];
 246 }
 247
 248 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 249     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
 250   let isBranch = 1;
 251   let isTerminator = 1;
 252   let hasDelaySlot = 0;
 253   let Defs = [AT];
 254 }
 255 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 256 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 257
 258 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
 259 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
 260
 261 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 262     : MMR6Arch<instr_asm> {
 263   dag OutOperandList = (outs GPROpnd:$rd);
 264   dag InOperandList = (ins GPROpnd:$rt);
 265   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 266   list<dag> Pattern = [];
 267 }
 268
 269 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 270
 271 class BRK_MMR6_DESC : BRK_FT<"break">;
 272
 273 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 274                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 275   dag OutOperandList = (outs);
 276   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 277   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 278   list<dag> Pattern = [];
 279   string DecoderMethod = "DecodeCacheOpMM";
 280 }
 281
 282 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
 283 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
 284
 285 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 286     : MMR6Arch<instr_asm> {
 287   dag OutOperandList = (outs GPROpnd:$rt);
 288   dag InOperandList = (ins GPROpnd:$rs);
 289   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 290 }
 291
 292 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
 293 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
 294
 295 class EHB_MMR6_DESC : Barrier<"ehb">;
 296 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
 297
 298 class ERET_MMR6_DESC : ER_FT<"eret">;
 299 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
 300
 301 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 302                                      RegisterOperand GPROpnd>
 303     : MMR6Arch<opstr> {
 304   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 305   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 306   list<dag> Pattern = [];
 307   bit isTerminator = 1;
 308   bit hasDelaySlot = 0;
 309 }
 310
 311 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 312                                                        GPR32Opnd> {
 313   bit isCall = 1;
 314   list<Register> Defs = [RA];
 315 }
 316
 317 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 318                                                      GPR32Opnd> {
 319   bit isBarrier = 1;
 320   list<Register> Defs = [AT];
 321 }
 322
 323 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 324                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
 325   dag OutOperandList = (outs GPROpnd:$rd);
 326   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 327   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 328   list<dag> Pattern = [];
 329 }
 330
 331 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
 332
 333 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 334     : MMR6Arch<instr_asm> {
 335   dag OutOperandList = (outs GPROpnd:$rt);
 336   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
 337   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 338   list<dag> Pattern = [];
 339 }
 340
 341 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
 342
 343 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 344 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
 345 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 346     : MMR6Arch<instr_asm> {
 347   dag OutOperandList = (outs GPROpnd:$rt);
 348   dag InOperandList = (ins simm16:$imm);
 349   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 350   list<dag> Pattern = [];
 351 }
 352
 353 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
 354 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
 355
 356 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 357                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
 358   dag OutOperandList = (outs GPROpnd:$rd);
 359   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 360   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 361   list<dag> Pattern = [];
 362 }
 363
 364 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
 365
 366 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 367                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
 368   dag OutOperandList = (outs GPROpnd:$rt);
 369   dag InOperandList = (ins ImmOpnd:$imm);
 370   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 371   list<dag> Pattern = [];
 372 }
 373
 374 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
 375 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
 376
 377 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 378     : MMR6Arch<instr_asm> {
 379   dag OutOperandList = (outs GPROpnd:$rd);
 380   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 381   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 382   list<dag> Pattern = [];
 383 }
 384
 385 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
 386 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
 387 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 388 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
 389 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
 390 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
 391 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
 392 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 393 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 394 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 395 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 396 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
 397 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 398 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 399
 400 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
 401                   SDPatternOperator OpNode = null_frag,
 402                   InstrItinClass Itin = NoItinerary,
 403                   ComplexPattern Addr = addr> :
 404   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 405          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 406   let DecoderMethod = "DecodeMem";
 407   let mayStore = 1;
 408 }
 409 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
 410 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
 411
 412 /// Floating Point Instructions
 413 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 414                             InstrItinClass Itin, bit isComm,
 415                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 416   dag OutOperandList = (outs RC:$fd);
 417   dag InOperandList = (ins RC:$ft, RC:$fs);
 418   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 419   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 420   InstrItinClass Itinerary = Itin;
 421   bit isCommutable = isComm;
 422 }
 423 class FADD_S_MMR6_DESC
 424   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 425 class FADD_D_MMR6_DESC
 426   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
 427 class FSUB_S_MMR6_DESC
 428   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 429 class FSUB_D_MMR6_DESC
 430   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
 431 class FMUL_S_MMR6_DESC
 432   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 433 class FMUL_D_MMR6_DESC
 434   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
 435 class FDIV_S_MMR6_DESC
 436   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 437 class FDIV_D_MMR6_DESC
 438   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
 439 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
 440 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
 441 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
 442 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
 443
 444 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 445                                RegisterOperand SrcRC, InstrItinClass Itin,
 446                                SDPatternOperator OpNode = null_frag>
 447                                : HARDFLOAT, NeverHasSideEffects {
 448   dag OutOperandList = (outs DstRC:$ft);
 449   dag InOperandList = (ins SrcRC:$fs);
 450   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 451   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 452   InstrItinClass Itinerary = Itin;
 453   Format Form = FrmFR;
 454 }
 455 class FMOV_S_MMR6_DESC
 456   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 457 class FMOV_D_MMR6_DESC
 458   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
 459 class FNEG_S_MMR6_DESC
 460   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 461 class FNEG_D_MMR6_DESC
 462   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
 463
 464 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
 465 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
 466 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
 467 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
 468
 469 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
 470 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
 471 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
 472 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
 473
 474 class CVT_MMR6_DESC_BASE<
 475     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 476     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 477     : HARDFLOAT, NeverHasSideEffects {
 478   dag OutOperandList = (outs DstRC:$ft);
 479   dag InOperandList = (ins SrcRC:$fs);
 480   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 481   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 482   InstrItinClass Itinerary = Itin;
 483   Format Form = FrmFR;
 484 }
 485
 486 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 487                                              II_CVT>;
 488 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 489                                              II_CVT>;
 490 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 491                                              II_CVT>;
 492 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
 493                                              II_CVT>;
 494 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
 495                                              II_CVT>;
 496 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
 497                                              II_CVT>;
 498 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 499                                              II_CVT>, FGR_64;
 500 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
 501                                              II_CVT>;
 502 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 503                                              II_CVT>;
 504 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 505                                              II_CVT>, FGR_64;
 506
 507 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 508                        RegisterOperand FGROpnd> {
 509   def CMP_AF_#NAME : POOL32F_CMP_FM<
 510       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 511       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 512       ISA_MICROMIPS32R6;
 513   def CMP_UN_#NAME : POOL32F_CMP_FM<
 514       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 515       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 516       ISA_MICROMIPS32R6;
 517   def CMP_EQ_#NAME : POOL32F_CMP_FM<
 518       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 519       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 520       ISA_MICROMIPS32R6;
 521   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
 522       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 523       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 524       ISA_MICROMIPS32R6;
 525   def CMP_LT_#NAME : POOL32F_CMP_FM<
 526       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 527       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 528       ISA_MICROMIPS32R6;
 529   def CMP_ULT_#NAME : POOL32F_CMP_FM<
 530       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 531       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 532       ISA_MICROMIPS32R6;
 533   def CMP_LE_#NAME : POOL32F_CMP_FM<
 534       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 535       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 536       ISA_MICROMIPS32R6;
 537   def CMP_ULE_#NAME : POOL32F_CMP_FM<
 538       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 539       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 540       ISA_MICROMIPS32R6;
 541   def CMP_SAF_#NAME : POOL32F_CMP_FM<
 542       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 543       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 544       ISA_MICROMIPS32R6;
 545   def CMP_SUN_#NAME : POOL32F_CMP_FM<
 546       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 547       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 548       ISA_MICROMIPS32R6;
 549   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
 550       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 551       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 552       ISA_MICROMIPS32R6;
 553   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
 554       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 555       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 556       ISA_MICROMIPS32R6;
 557   def CMP_SLT_#NAME : POOL32F_CMP_FM<
 558       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 559       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 560       ISA_MICROMIPS32R6;
 561   def CMP_SULT_#NAME : POOL32F_CMP_FM<
 562       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 563       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 564       ISA_MICROMIPS32R6;
 565   def CMP_SLE_#NAME : POOL32F_CMP_FM<
 566       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 567       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 568       ISA_MICROMIPS32R6;
 569   def CMP_SULE_#NAME : POOL32F_CMP_FM<
 570       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
 571       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 572       ISA_MICROMIPS32R6;
 573 }
 574
 575 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 576                              RegisterOperand SrcRC, InstrItinClass Itin,
 577                              SDPatternOperator OpNode = null_frag>
 578     : HARDFLOAT, NeverHasSideEffects {
 579   dag OutOperandList = (outs DstRC:$ft);
 580   dag InOperandList  = (ins SrcRC:$fs);
 581   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
 582   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 583   InstrItinClass Itinerary = Itin;
 584   Format Form = FrmFR;
 585   list<Predicate> EncodingPredicates = [HasStdEnc];
 586 }
 587
 588 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
 589                                                 II_ABS, fabs>;
 590 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
 591                                                 II_ABS, fabs>;
 592 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
 593                                                     FGR32Opnd, II_FLOOR>;
 594 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
 595                                                     FGR64Opnd, II_FLOOR>;
 596 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
 597                                                     FGR32Opnd, II_FLOOR>;
 598 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
 599                                                     AFGR64Opnd, II_FLOOR>;
 600 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
 601                                                    FGR32Opnd, II_CEIL>;
 602 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
 603                                                    FGR64Opnd, II_CEIL>;
 604 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
 605                                                    FGR32Opnd, II_CEIL>;
 606 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
 607                                                    AFGR64Opnd, II_CEIL>;
 608 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
 609                                                     FGR32Opnd, II_TRUNC>;
 610 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
 611                                                     FGR64Opnd, II_TRUNC>;
 612 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
 613                                                     FGR32Opnd, II_TRUNC>;
 614 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
 615                                                     AFGR64Opnd, II_TRUNC>;
 616 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
 617                                                  II_SQRT_S, fsqrt>;
 618 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
 619                                                  II_SQRT_D, fsqrt>;
 620 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
 621                                                   FGR32Opnd, II_TRUNC>;
 622 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
 623                                                   AFGR64Opnd, II_TRUNC>;
 624
 625 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
 626     : Store<opstr, RO>, MMR6Arch<opstr> {
 627   let DecoderMethod = "DecodeMemMMImm16";
 628 }
 629 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
 630
 631 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 632     : MMR6Arch<instr_asm>, MipsR6Inst {
 633   dag OutOperandList = (outs);
 634   dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
 635   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 636   string DecoderMethod = "DecodeStoreEvaOpMM";
 637   bit mayStore = 1;
 638 }
 639 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
 640 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
 641 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
 642 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
 643
 644 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
 645             MMR6Arch<instr_asm>, MipsR6Inst {
 646   dag OutOperandList = (outs RO:$rt);
 647   dag InOperandList = (ins mem_mm_12:$addr);
 648   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 649   string DecoderMethod = "DecodeMemMMImm9";
 650   bit mayLoad = 1;
 651 }
 652 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 653 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 654
 655 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
 656   dag OutOperandList = (outs GPR32Opnd:$rt);
 657   dag InOperandList = (ins mem:$addr);
 658   string AsmString = "lw\t$rt, $addr";
 659   let DecoderMethod = "DecodeMemMMImm16";
 660   let canFoldAsLoad = 1;
 661   let mayLoad = 1;
 662   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
 663   InstrItinClass Itinerary = II_LW;
 664 }
 665
 666 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
 667   dag OutOperandList = (outs GPR32Opnd:$rt);
 668   dag InOperandList = (ins uimm16:$imm16);
 669   string AsmString = "lui\t$rt, $imm16";
 670   list<dag> Pattern = [];
 671   bit hasSideEffects = 0;
 672   bit isReMaterializable = 1;
 673   InstrItinClass Itinerary = II_LUI;
 674   Format Form = FrmI;
 675 }
 676
 677 //===----------------------------------------------------------------------===//
 678 //
 679 // Instruction Definitions
 680 //
 681 //===----------------------------------------------------------------------===//
 682
 683 let DecoderNamespace = "MicroMipsR6" in {
 684 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
 685 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
 686 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
 687 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
 688                    ISA_MICROMIPS32R6;
 689 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
 690                   ISA_MICROMIPS32R6;
 691 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
 692 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
 693 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
 694 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
 695 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
 696 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
 697 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
 698 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
 699 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
 700                    ISA_MICROMIPS32R6;
 701 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
 702                    ISA_MICROMIPS32R6;
 703 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
 704                    ISA_MICROMIPS32R6;
 705 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
 706                    ISA_MICROMIPS32R6;
 707 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
 708                    ISA_MICROMIPS32R6;
 709 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
 710                    ISA_MICROMIPS32R6;
 711 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
 712                    ISA_MICROMIPS32R6;
 713 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
 714                    ISA_MICROMIPS32R6;
 715 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
 716                    ISA_MICROMIPS32R6;
 717 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 718 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
 719 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 720 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 721 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
 722 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
 723 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
 724 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
 725 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
 726 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
 727                   ISA_MICROMIPS32R6;
 728 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
 729 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 730 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 731 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 732 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 733 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 734 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
 735 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
 736 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
 737 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
 738 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
 739 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
 740 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
 741 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
 742 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
 743 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
 744 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
 745                   ISA_MICROMIPS32R6;
 746 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
 747                   ISA_MICROMIPS32R6;
 748 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
 749 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
 750 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
 751 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
 752 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
 753 let DecoderMethod = "DecodeMemMMImm16" in {
 754   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
 755 }
 756 let DecoderMethod = "DecodeMemMMImm9" in {
 757   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
 758 }
 759 /// Floating Point Instructions
 760 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
 761                   ISA_MICROMIPS32R6;
 762 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
 763                   ISA_MICROMIPS32R6;
 764 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
 765                   ISA_MICROMIPS32R6;
 766 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
 767                   ISA_MICROMIPS32R6;
 768 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
 769                   ISA_MICROMIPS32R6;
 770 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
 771                   ISA_MICROMIPS32R6;
 772 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
 773                   ISA_MICROMIPS32R6;
 774 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
 775                   ISA_MICROMIPS32R6;
 776 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
 777                    ISA_MICROMIPS32R6;
 778 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
 779                    ISA_MICROMIPS32R6;
 780 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
 781                    ISA_MICROMIPS32R6;
 782 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
 783                    ISA_MICROMIPS32R6;
 784 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
 785                   ISA_MICROMIPS32R6;
 786 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
 787                   ISA_MICROMIPS32R6;
 788 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
 789                   ISA_MICROMIPS32R6;
 790 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
 791                   ISA_MICROMIPS32R6;
 792 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
 793 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
 794 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
 795 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
 796 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
 797                   ISA_MICROMIPS32R6;
 798 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
 799                   ISA_MICROMIPS32R6;
 800 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
 801                   ISA_MICROMIPS32R6;
 802 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
 803                   ISA_MICROMIPS32R6;
 804 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
 805                    ISA_MICROMIPS32R6;
 806 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
 807                    ISA_MICROMIPS32R6;
 808 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
 809                    ISA_MICROMIPS32R6;
 810 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
 811                    ISA_MICROMIPS32R6;
 812 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
 813                    ISA_MICROMIPS32R6;
 814 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
 815                    ISA_MICROMIPS32R6;
 816 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
 817                    ISA_MICROMIPS32R6;
 818 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
 819                    ISA_MICROMIPS32R6;
 820 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
 821                    ISA_MICROMIPS32R6;
 822 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
 823                    ISA_MICROMIPS32R6;
 824 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
 825 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
 826 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
 827 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
 828 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
 829                      ISA_MICROMIPS32R6;
 830 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
 831                      ISA_MICROMIPS32R6;
 832 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
 833                      ISA_MICROMIPS32R6;
 834 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
 835                      ISA_MICROMIPS32R6;
 836 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
 837                     ISA_MICROMIPS32R6;
 838 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
 839                     ISA_MICROMIPS32R6;
 840 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
 841                     ISA_MICROMIPS32R6;
 842 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
 843                     ISA_MICROMIPS32R6;
 844 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
 845                      ISA_MICROMIPS32R6;
 846 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
 847                      ISA_MICROMIPS32R6;
 848 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
 849                      ISA_MICROMIPS32R6;
 850 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
 851                      ISA_MICROMIPS32R6;
 852 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
 853                   ISA_MICROMIPS32R6;
 854 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
 855                   ISA_MICROMIPS32R6;
 856 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
 857                    ISA_MICROMIPS32R6;
 858 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
 859                    ISA_MICROMIPS32R6;
 860 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
 861 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
 862 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
 863 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
 864 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
 865 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
 866 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
 867 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
 868 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
 869 }
 870
 871 //===----------------------------------------------------------------------===//
 872 //
 873 // MicroMips instruction aliases
 874 //
 875 //===----------------------------------------------------------------------===//
 876
 877 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
 878 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
 879 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
 880                                       !strconcat("b", "\t$offset")>,
 881                     MicroMipsR6Inst16;