1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides Mips specific target streamer methods.
12 //===----------------------------------------------------------------------===//
14 #include "InstPrinter/MipsInstPrinter.h"
15 #include "MipsELFStreamer.h"
16 #include "MipsMCTargetDesc.h"
17 #include "MipsTargetObjectFile.h"
18 #include "MipsTargetStreamer.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCELF.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/ELF.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/FormattedStream.h"
31 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
32 : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
33 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
35 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
36 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
37 void MipsTargetStreamer::emitDirectiveSetMips16() {}
38 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
39 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
40 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
41 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
42 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
43 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
44 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
45 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
46 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
47 forbidModuleDirective();
49 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
50 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
51 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
52 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
53 void MipsTargetStreamer::emitDirectiveNaN2008() {}
54 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
55 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
56 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
57 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
58 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
59 unsigned ReturnReg) {}
60 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
61 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
63 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
64 forbidModuleDirective();
66 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
67 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
68 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
69 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
70 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
71 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
72 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
73 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
74 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
75 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
76 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
77 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
78 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
79 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
80 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
81 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
82 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
83 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
84 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
85 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
86 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
87 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
88 const MCSymbol &Sym, bool IsReg) {
90 void MipsTargetStreamer::emitDirectiveModuleOddSPReg(bool Enabled,
92 if (!Enabled && !IsO32ABI)
93 report_fatal_error("+nooddspreg is only valid for O32");
95 void MipsTargetStreamer::emitDirectiveSetFp(
96 MipsABIFlagsSection::FpABIKind Value) {
97 forbidModuleDirective();
100 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
101 formatted_raw_ostream &OS)
102 : MipsTargetStreamer(S), OS(OS) {}
104 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
105 OS << "\t.set\tmicromips\n";
106 forbidModuleDirective();
109 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
110 OS << "\t.set\tnomicromips\n";
111 forbidModuleDirective();
114 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
115 OS << "\t.set\tmips16\n";
116 forbidModuleDirective();
119 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
120 OS << "\t.set\tnomips16\n";
121 MipsTargetStreamer::emitDirectiveSetNoMips16();
124 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
125 OS << "\t.set\treorder\n";
126 MipsTargetStreamer::emitDirectiveSetReorder();
129 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
130 OS << "\t.set\tnoreorder\n";
131 forbidModuleDirective();
134 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
135 OS << "\t.set\tmacro\n";
136 MipsTargetStreamer::emitDirectiveSetMacro();
139 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
140 OS << "\t.set\tnomacro\n";
141 MipsTargetStreamer::emitDirectiveSetNoMacro();
144 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
145 OS << "\t.set\tmsa\n";
146 MipsTargetStreamer::emitDirectiveSetMsa();
149 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
150 OS << "\t.set\tnomsa\n";
151 MipsTargetStreamer::emitDirectiveSetNoMsa();
154 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
155 OS << "\t.set\tat\n";
156 MipsTargetStreamer::emitDirectiveSetAt();
159 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
160 OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
161 MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
164 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
165 OS << "\t.set\tnoat\n";
166 MipsTargetStreamer::emitDirectiveSetNoAt();
169 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
170 OS << "\t.end\t" << Name << '\n';
173 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
174 OS << "\t.ent\t" << Symbol.getName() << '\n';
177 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
179 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
181 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
182 OS << "\t.nan\tlegacy\n";
185 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
186 OS << "\t.option\tpic0\n";
189 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
190 OS << "\t.option\tpic2\n";
193 void MipsTargetAsmStreamer::emitDirectiveInsn() {
194 MipsTargetStreamer::emitDirectiveInsn();
198 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
199 unsigned ReturnReg) {
201 << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
203 << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
206 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
207 OS << "\t.set arch=" << Arch << "\n";
208 MipsTargetStreamer::emitDirectiveSetArch(Arch);
211 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
212 OS << "\t.set\tmips0\n";
213 MipsTargetStreamer::emitDirectiveSetMips0();
216 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
217 OS << "\t.set\tmips1\n";
218 MipsTargetStreamer::emitDirectiveSetMips1();
221 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
222 OS << "\t.set\tmips2\n";
223 MipsTargetStreamer::emitDirectiveSetMips2();
226 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
227 OS << "\t.set\tmips3\n";
228 MipsTargetStreamer::emitDirectiveSetMips3();
231 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
232 OS << "\t.set\tmips4\n";
233 MipsTargetStreamer::emitDirectiveSetMips4();
236 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
237 OS << "\t.set\tmips5\n";
238 MipsTargetStreamer::emitDirectiveSetMips5();
241 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
242 OS << "\t.set\tmips32\n";
243 MipsTargetStreamer::emitDirectiveSetMips32();
246 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
247 OS << "\t.set\tmips32r2\n";
248 MipsTargetStreamer::emitDirectiveSetMips32R2();
251 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
252 OS << "\t.set\tmips32r3\n";
253 MipsTargetStreamer::emitDirectiveSetMips32R3();
256 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
257 OS << "\t.set\tmips32r5\n";
258 MipsTargetStreamer::emitDirectiveSetMips32R5();
261 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
262 OS << "\t.set\tmips32r6\n";
263 MipsTargetStreamer::emitDirectiveSetMips32R6();
266 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
267 OS << "\t.set\tmips64\n";
268 MipsTargetStreamer::emitDirectiveSetMips64();
271 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
272 OS << "\t.set\tmips64r2\n";
273 MipsTargetStreamer::emitDirectiveSetMips64R2();
276 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
277 OS << "\t.set\tmips64r3\n";
278 MipsTargetStreamer::emitDirectiveSetMips64R3();
281 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
282 OS << "\t.set\tmips64r5\n";
283 MipsTargetStreamer::emitDirectiveSetMips64R5();
286 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
287 OS << "\t.set\tmips64r6\n";
288 MipsTargetStreamer::emitDirectiveSetMips64R6();
291 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
292 OS << "\t.set\tdsp\n";
293 MipsTargetStreamer::emitDirectiveSetDsp();
296 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
297 OS << "\t.set\tnodsp\n";
298 MipsTargetStreamer::emitDirectiveSetNoDsp();
301 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
302 OS << "\t.set\tpop\n";
303 MipsTargetStreamer::emitDirectiveSetPop();
306 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
307 OS << "\t.set\tpush\n";
308 MipsTargetStreamer::emitDirectiveSetPush();
311 // Print a 32 bit hex number with all numbers.
312 static void printHex32(unsigned Value, raw_ostream &OS) {
314 for (int i = 7; i >= 0; i--)
315 OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
318 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
319 int CPUTopSavedRegOff) {
321 printHex32(CPUBitmask, OS);
322 OS << ',' << CPUTopSavedRegOff << '\n';
325 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
326 int FPUTopSavedRegOff) {
328 printHex32(FPUBitmask, OS);
329 OS << "," << FPUTopSavedRegOff << '\n';
332 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
334 << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
335 forbidModuleDirective();
338 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
342 OS << "\t.cpsetup\t$"
343 << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
347 << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
353 OS << Sym.getName() << "\n";
354 forbidModuleDirective();
357 void MipsTargetAsmStreamer::emitDirectiveModuleFP(
358 MipsABIFlagsSection::FpABIKind Value, bool Is32BitABI) {
359 MipsTargetStreamer::emitDirectiveModuleFP(Value, Is32BitABI);
361 OS << "\t.module\tfp=";
362 OS << ABIFlagsSection.getFpABIString(Value) << "\n";
365 void MipsTargetAsmStreamer::emitDirectiveSetFp(
366 MipsABIFlagsSection::FpABIKind Value) {
367 MipsTargetStreamer::emitDirectiveSetFp(Value);
370 OS << ABIFlagsSection.getFpABIString(Value) << "\n";
373 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg(bool Enabled,
375 MipsTargetStreamer::emitDirectiveModuleOddSPReg(Enabled, IsO32ABI);
377 OS << "\t.module\t" << (Enabled ? "" : "no") << "oddspreg\n";
380 // This part is for ELF object output.
381 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
382 const MCSubtargetInfo &STI)
383 : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
384 MCAssembler &MCA = getStreamer().getAssembler();
385 Pic = MCA.getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
387 const FeatureBitset &Features = STI.getFeatureBits();
389 // Set the header flags that we can in the constructor.
390 // FIXME: This is a fairly terrible hack. We set the rest
391 // of these in the destructor. The problem here is two-fold:
393 // a: Some of the eflags can be set/reset by directives.
394 // b: There aren't any usage paths that initialize the ABI
395 // pointer until after we initialize either an assembler
396 // or the target machine.
397 // We can fix this by making the target streamer construct
398 // the ABI, but this is fraught with wide ranging dependency
400 unsigned EFlags = MCA.getELFHeaderEFlags();
403 if (Features[Mips::FeatureMips64r6])
404 EFlags |= ELF::EF_MIPS_ARCH_64R6;
405 else if (Features[Mips::FeatureMips64r2] ||
406 Features[Mips::FeatureMips64r3] ||
407 Features[Mips::FeatureMips64r5])
408 EFlags |= ELF::EF_MIPS_ARCH_64R2;
409 else if (Features[Mips::FeatureMips64])
410 EFlags |= ELF::EF_MIPS_ARCH_64;
411 else if (Features[Mips::FeatureMips5])
412 EFlags |= ELF::EF_MIPS_ARCH_5;
413 else if (Features[Mips::FeatureMips4])
414 EFlags |= ELF::EF_MIPS_ARCH_4;
415 else if (Features[Mips::FeatureMips3])
416 EFlags |= ELF::EF_MIPS_ARCH_3;
417 else if (Features[Mips::FeatureMips32r6])
418 EFlags |= ELF::EF_MIPS_ARCH_32R6;
419 else if (Features[Mips::FeatureMips32r2] ||
420 Features[Mips::FeatureMips32r3] ||
421 Features[Mips::FeatureMips32r5])
422 EFlags |= ELF::EF_MIPS_ARCH_32R2;
423 else if (Features[Mips::FeatureMips32])
424 EFlags |= ELF::EF_MIPS_ARCH_32;
425 else if (Features[Mips::FeatureMips2])
426 EFlags |= ELF::EF_MIPS_ARCH_2;
428 EFlags |= ELF::EF_MIPS_ARCH_1;
431 if (Features[Mips::FeatureNaN2008])
432 EFlags |= ELF::EF_MIPS_NAN2008;
434 // -mabicalls and -mplt are not implemented but we should act as if they were
436 EFlags |= ELF::EF_MIPS_CPIC;
438 MCA.setELFHeaderEFlags(EFlags);
441 void MipsTargetELFStreamer::emitLabel(MCSymbol *Symbol) {
442 if (!isMicroMipsEnabled())
444 getStreamer().getOrCreateSymbolData(Symbol);
445 uint8_t Type = MCELF::GetType(*Symbol);
446 if (Type != ELF::STT_FUNC)
449 // The "other" values are stored in the last 6 bits of the second byte
450 // The traditional defines for STO values assume the full byte and thus
451 // the shift to pack it.
452 MCELF::setOther(*Symbol, ELF::STO_MIPS_MICROMIPS >> 2);
455 void MipsTargetELFStreamer::finish() {
456 MCAssembler &MCA = getStreamer().getAssembler();
457 const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
459 // .bss, .text and .data are always at least 16-byte aligned.
460 MCSection &TextSection = *OFI.getTextSection();
461 MCA.registerSection(TextSection);
462 MCSection &DataSection = *OFI.getDataSection();
463 MCA.registerSection(DataSection);
464 MCSection &BSSSection = *OFI.getBSSSection();
465 MCA.registerSection(BSSSection);
467 TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
468 DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
469 BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
471 const FeatureBitset &Features = STI.getFeatureBits();
473 // Update e_header flags. See the FIXME and comment above in
474 // the constructor for a full rundown on this.
475 unsigned EFlags = MCA.getELFHeaderEFlags();
478 // N64 does not require any ABI bits.
479 if (getABI().IsO32())
480 EFlags |= ELF::EF_MIPS_ABI_O32;
481 else if (getABI().IsN32())
482 EFlags |= ELF::EF_MIPS_ABI2;
484 if (Features[Mips::FeatureGP64Bit]) {
485 if (getABI().IsO32())
486 EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
487 } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
488 EFlags |= ELF::EF_MIPS_32BITMODE;
490 // If we've set the cpic eflag and we're n64, go ahead and set the pic
492 if (EFlags & ELF::EF_MIPS_CPIC && getABI().IsN64())
493 EFlags |= ELF::EF_MIPS_PIC;
495 MCA.setELFHeaderEFlags(EFlags);
497 // Emit all the option records.
498 // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
500 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
501 MEF.EmitMipsOptionRecords();
506 void MipsTargetELFStreamer::emitAssignment(MCSymbol *Symbol,
507 const MCExpr *Value) {
508 // If on rhs is micromips symbol then mark Symbol as microMips.
509 if (Value->getKind() != MCExpr::SymbolRef)
511 const MCSymbol &RhsSym =
512 static_cast<const MCSymbolRefExpr *>(Value)->getSymbol();
514 if (!(MCELF::getOther(RhsSym) & (ELF::STO_MIPS_MICROMIPS >> 2)))
517 // The "other" values are stored in the last 6 bits of the second byte.
518 // The traditional defines for STO values assume the full byte and thus
519 // the shift to pack it.
520 MCELF::setOther(*Symbol, ELF::STO_MIPS_MICROMIPS >> 2);
523 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
524 return static_cast<MCELFStreamer &>(Streamer);
527 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
528 MicroMipsEnabled = true;
530 MCAssembler &MCA = getStreamer().getAssembler();
531 unsigned Flags = MCA.getELFHeaderEFlags();
532 Flags |= ELF::EF_MIPS_MICROMIPS;
533 MCA.setELFHeaderEFlags(Flags);
534 forbidModuleDirective();
537 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
538 MicroMipsEnabled = false;
539 forbidModuleDirective();
542 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
543 MCAssembler &MCA = getStreamer().getAssembler();
544 unsigned Flags = MCA.getELFHeaderEFlags();
545 Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
546 MCA.setELFHeaderEFlags(Flags);
547 forbidModuleDirective();
550 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
551 MCAssembler &MCA = getStreamer().getAssembler();
552 unsigned Flags = MCA.getELFHeaderEFlags();
553 Flags |= ELF::EF_MIPS_NOREORDER;
554 MCA.setELFHeaderEFlags(Flags);
555 forbidModuleDirective();
558 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
559 MCAssembler &MCA = getStreamer().getAssembler();
560 MCContext &Context = MCA.getContext();
561 MCStreamer &OS = getStreamer();
563 MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS,
564 ELF::SHF_ALLOC | ELF::SHT_REL);
566 const MCSymbolRefExpr *ExprRef =
567 MCSymbolRefExpr::Create(Name, MCSymbolRefExpr::VK_None, Context);
569 MCA.registerSection(*Sec);
570 Sec->setAlignment(4);
574 OS.SwitchSection(Sec);
576 OS.EmitValueImpl(ExprRef, 4);
578 OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
579 OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset
581 OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
582 OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset
584 OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
585 OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg
586 OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg
588 // The .end directive marks the end of a procedure. Invalidate
589 // the information gathered up until this point.
590 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
595 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
596 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
599 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
600 MCAssembler &MCA = getStreamer().getAssembler();
601 unsigned Flags = MCA.getELFHeaderEFlags();
602 Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
603 MCA.setELFHeaderEFlags(Flags);
606 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
607 MCAssembler &MCA = getStreamer().getAssembler();
608 unsigned Flags = MCA.getELFHeaderEFlags();
609 Flags |= ELF::EF_MIPS_NAN2008;
610 MCA.setELFHeaderEFlags(Flags);
613 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
614 MCAssembler &MCA = getStreamer().getAssembler();
615 unsigned Flags = MCA.getELFHeaderEFlags();
616 Flags &= ~ELF::EF_MIPS_NAN2008;
617 MCA.setELFHeaderEFlags(Flags);
620 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
621 MCAssembler &MCA = getStreamer().getAssembler();
622 unsigned Flags = MCA.getELFHeaderEFlags();
623 // This option overrides other PIC options like -KPIC.
625 Flags &= ~ELF::EF_MIPS_PIC;
626 MCA.setELFHeaderEFlags(Flags);
629 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
630 MCAssembler &MCA = getStreamer().getAssembler();
631 unsigned Flags = MCA.getELFHeaderEFlags();
633 // NOTE: We are following the GAS behaviour here which means the directive
634 // 'pic2' also sets the CPIC bit in the ELF header. This is different from
635 // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
636 // EF_MIPS_CPIC to be mutually exclusive.
637 Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
638 MCA.setELFHeaderEFlags(Flags);
641 void MipsTargetELFStreamer::emitDirectiveInsn() {
642 MipsTargetStreamer::emitDirectiveInsn();
643 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
644 MEF.createPendingLabelRelocs();
647 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
648 unsigned ReturnReg_) {
649 MCContext &Context = getStreamer().getAssembler().getContext();
650 const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
653 FrameReg = RegInfo->getEncodingValue(StackReg);
654 FrameOffset = StackSize;
655 ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
658 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
659 int CPUTopSavedRegOff) {
661 GPRBitMask = CPUBitmask;
662 GPROffset = CPUTopSavedRegOff;
665 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
666 int FPUTopSavedRegOff) {
668 FPRBitMask = FPUBitmask;
669 FPROffset = FPUTopSavedRegOff;
672 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
674 // This directive expands to:
675 // lui $gp, %hi(_gp_disp)
676 // addui $gp, $gp, %lo(_gp_disp)
677 // addu $gp, $gp, $reg
678 // when support for position independent code is enabled.
679 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
682 // There's a GNU extension controlled by -mno-shared that allows
683 // locally-binding symbols to be accessed using absolute addresses.
684 // This is currently not supported. When supported -mno-shared makes
685 // .cpload expand to:
686 // lui $gp, %hi(__gnu_local_gp)
687 // addiu $gp, $gp, %lo(__gnu_local_gp)
689 StringRef SymName("_gp_disp");
690 MCAssembler &MCA = getStreamer().getAssembler();
691 MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
692 MCA.registerSymbol(*GP_Disp);
695 TmpInst.setOpcode(Mips::LUi);
696 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
697 const MCSymbolRefExpr *HiSym = MCSymbolRefExpr::Create(
698 "_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_HI, MCA.getContext());
699 TmpInst.addOperand(MCOperand::createExpr(HiSym));
700 getStreamer().EmitInstruction(TmpInst, STI);
704 TmpInst.setOpcode(Mips::ADDiu);
705 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
706 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
707 const MCSymbolRefExpr *LoSym = MCSymbolRefExpr::Create(
708 "_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_LO, MCA.getContext());
709 TmpInst.addOperand(MCOperand::createExpr(LoSym));
710 getStreamer().EmitInstruction(TmpInst, STI);
714 TmpInst.setOpcode(Mips::ADDu);
715 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
716 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
717 TmpInst.addOperand(MCOperand::createReg(RegNo));
718 getStreamer().EmitInstruction(TmpInst, STI);
720 forbidModuleDirective();
723 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
727 // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
728 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
731 MCAssembler &MCA = getStreamer().getAssembler();
734 // Either store the old $gp in a register or on the stack
736 // move $save, $gpreg
737 Inst.setOpcode(Mips::DADDu);
738 Inst.addOperand(MCOperand::createReg(RegOrOffset));
739 Inst.addOperand(MCOperand::createReg(Mips::GP));
740 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
742 // sd $gpreg, offset($sp)
743 Inst.setOpcode(Mips::SD);
744 Inst.addOperand(MCOperand::createReg(Mips::GP));
745 Inst.addOperand(MCOperand::createReg(Mips::SP));
746 Inst.addOperand(MCOperand::createImm(RegOrOffset));
748 getStreamer().EmitInstruction(Inst, STI);
751 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
752 &Sym, MCSymbolRefExpr::VK_Mips_GPOFF_HI, MCA.getContext());
753 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
754 &Sym, MCSymbolRefExpr::VK_Mips_GPOFF_LO, MCA.getContext());
756 // lui $gp, %hi(%neg(%gp_rel(funcSym)))
757 Inst.setOpcode(Mips::LUi);
758 Inst.addOperand(MCOperand::createReg(Mips::GP));
759 Inst.addOperand(MCOperand::createExpr(HiExpr));
760 getStreamer().EmitInstruction(Inst, STI);
763 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
764 Inst.setOpcode(Mips::ADDiu);
765 Inst.addOperand(MCOperand::createReg(Mips::GP));
766 Inst.addOperand(MCOperand::createReg(Mips::GP));
767 Inst.addOperand(MCOperand::createExpr(LoExpr));
768 getStreamer().EmitInstruction(Inst, STI);
771 // daddu $gp, $gp, $funcreg
772 Inst.setOpcode(Mips::DADDu);
773 Inst.addOperand(MCOperand::createReg(Mips::GP));
774 Inst.addOperand(MCOperand::createReg(Mips::GP));
775 Inst.addOperand(MCOperand::createReg(RegNo));
776 getStreamer().EmitInstruction(Inst, STI);
778 forbidModuleDirective();
781 void MipsTargetELFStreamer::emitMipsAbiFlags() {
782 MCAssembler &MCA = getStreamer().getAssembler();
783 MCContext &Context = MCA.getContext();
784 MCStreamer &OS = getStreamer();
785 MCSectionELF *Sec = Context.getELFSection(
786 ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
787 MCA.registerSection(*Sec);
788 Sec->setAlignment(8);
789 OS.SwitchSection(Sec);
791 OS << ABIFlagsSection;
794 void MipsTargetELFStreamer::emitDirectiveModuleOddSPReg(bool Enabled,
796 MipsTargetStreamer::emitDirectiveModuleOddSPReg(Enabled, IsO32ABI);
798 ABIFlagsSection.OddSPReg = Enabled;