lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

   1 //===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides Mips specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
  15 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
  16
  17 #include "llvm/Support/DataTypes.h"
  18
  19 namespace llvm {
  20 class MCAsmBackend;
  21 class MCCodeEmitter;
  22 class MCContext;
  23 class MCInstrInfo;
  24 class MCObjectWriter;
  25 class MCRegisterInfo;
  26 class MCSubtargetInfo;
  27 class StringRef;
  28 class Target;
  29 class raw_ostream;
  30
  31 extern Target TheMipsTarget;
  32 extern Target TheMipselTarget;
  33 extern Target TheMips64Target;
  34 extern Target TheMips64elTarget;
  35
  36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
  37                                          const MCRegisterInfo &MRI,
  38                                          MCContext &Ctx);
  39 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
  40                                          const MCRegisterInfo &MRI,
  41                                          MCContext &Ctx);
  42
  43 MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
  44                                        const MCRegisterInfo &MRI, StringRef TT,
  45                                        StringRef CPU);
  46 MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
  47                                        const MCRegisterInfo &MRI, StringRef TT,
  48                                        StringRef CPU);
  49 MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
  50                                        const MCRegisterInfo &MRI, StringRef TT,
  51                                        StringRef CPU);
  52 MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
  53                                        const MCRegisterInfo &MRI, StringRef TT,
  54                                        StringRef CPU);
  55
  56 MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI,
  57                                           bool IsLittleEndian, bool Is64Bit);
  58
  59 namespace MIPS_MC {
  60 StringRef selectMipsCPU(StringRef TT, StringRef CPU);
  61 }
  62
  63 } // End llvm namespace
  64
  65 // Defines symbolic names for Mips registers.  This defines a mapping from
  66 // register name to register number.
  67 #define GET_REGINFO_ENUM
  68 #include "MipsGenRegisterInfo.inc"
  69
  70 // Defines symbolic names for the Mips instructions.
  71 #define GET_INSTRINFO_ENUM
  72 #include "MipsGenInstrInfo.inc"
  73
  74 #define GET_SUBTARGETINFO_ENUM
  75 #include "MipsGenSubtargetInfo.inc"
  76
  77 #endif