lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

   1 //===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides Mips specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
  15 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
  16
  17 #include "llvm/Support/DataTypes.h"
  18
  19 namespace llvm {
  20 class MCAsmBackend;
  21 class MCCodeEmitter;
  22 class MCContext;
  23 class MCInstrInfo;
  24 class MCObjectWriter;
  25 class MCRegisterInfo;
  26 class MCSubtargetInfo;
  27 class StringRef;
  28 class Target;
  29 class TargetTuple;
  30 class raw_ostream;
  31 class raw_pwrite_stream;
  32
  33 extern Target TheMipsTarget;
  34 extern Target TheMipselTarget;
  35 extern Target TheMips64Target;
  36 extern Target TheMips64elTarget;
  37
  38 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
  39                                          const MCRegisterInfo &MRI,
  40                                          MCContext &Ctx);
  41 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
  42                                          const MCRegisterInfo &MRI,
  43                                          MCContext &Ctx);
  44
  45 MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
  46                                        const MCRegisterInfo &MRI,
  47                                        const TargetTuple &TT, StringRef CPU);
  48 MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
  49                                        const MCRegisterInfo &MRI,
  50                                        const TargetTuple &TT, StringRef CPU);
  51 MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
  52                                        const MCRegisterInfo &MRI,
  53                                        const TargetTuple &TT, StringRef CPU);
  54 MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
  55                                        const MCRegisterInfo &MRI,
  56                                        const TargetTuple &TT, StringRef CPU);
  57
  58 MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
  59                                           bool IsLittleEndian, bool Is64Bit);
  60
  61 namespace MIPS_MC {
  62 StringRef selectMipsCPU(const TargetTuple &TT, StringRef CPU);
  63 }
  64
  65 } // End llvm namespace
  66
  67 // Defines symbolic names for Mips registers.  This defines a mapping from
  68 // register name to register number.
  69 #define GET_REGINFO_ENUM
  70 #include "MipsGenRegisterInfo.inc"
  71
  72 // Defines symbolic names for the Mips instructions.
  73 #define GET_INSTRINFO_ENUM
  74 #include "MipsGenInstrInfo.inc"
  75
  76 #define GET_SUBTARGETINFO_ENUM
  77 #include "MipsGenSubtargetInfo.inc"
  78
  79 #endif