1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides Mips specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "InstPrinter/MipsInstPrinter.h"
15 #include "MipsELFStreamer.h"
16 #include "MipsMCAsmInfo.h"
17 #include "MipsMCNaCl.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetStreamer.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCCodeGenInfo.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MachineLocation.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/FormattedStream.h"
31 #include "llvm/Support/TargetRegistry.h"
35 #define GET_INSTRINFO_MC_DESC
36 #include "MipsGenInstrInfo.inc"
38 #define GET_SUBTARGETINFO_MC_DESC
39 #include "MipsGenSubtargetInfo.inc"
41 #define GET_REGINFO_MC_DESC
42 #include "MipsGenRegisterInfo.inc"
44 /// Select the Mips CPU for the given triple and cpu name.
45 /// FIXME: Merge with the copy in MipsSubtarget.cpp
46 StringRef MIPS_MC::selectMipsCPU(StringRef TT, StringRef CPU) {
47 if (CPU.empty() || CPU == "generic") {
49 if (TheTriple.getArch() == Triple::mips ||
50 TheTriple.getArch() == Triple::mipsel)
58 static MCInstrInfo *createMipsMCInstrInfo() {
59 MCInstrInfo *X = new MCInstrInfo();
60 InitMipsMCInstrInfo(X);
64 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
65 MCRegisterInfo *X = new MCRegisterInfo();
66 InitMipsMCRegisterInfo(X, Mips::RA);
70 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
72 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
73 MCSubtargetInfo *X = new MCSubtargetInfo();
74 InitMipsMCSubtargetInfo(X, TT, CPU, FS);
78 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
79 MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
81 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
82 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
83 MAI->addInitialFrameState(Inst);
88 static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
90 CodeGenOpt::Level OL) {
91 MCCodeGenInfo *X = new MCCodeGenInfo();
92 if (CM == CodeModel::JITDefault)
94 else if (RM == Reloc::Default)
96 X->InitMCCodeGenInfo(RM, CM, OL);
100 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
101 unsigned SyntaxVariant,
102 const MCAsmInfo &MAI,
103 const MCInstrInfo &MII,
104 const MCRegisterInfo &MRI) {
105 return new MipsInstPrinter(MAI, MII, MRI);
108 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
109 MCAsmBackend &MAB, raw_ostream &OS,
110 MCCodeEmitter *Emitter, bool RelaxAll) {
113 S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
115 S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
119 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
120 formatted_raw_ostream &OS,
121 MCInstPrinter *InstPrint,
123 return new MipsTargetAsmStreamer(S, OS);
126 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
127 return new MipsTargetStreamer(S);
130 static MCTargetStreamer *
131 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
132 return new MipsTargetELFStreamer(S, STI);
135 extern "C" void LLVMInitializeMipsTargetMC() {
136 for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
137 &TheMips64elTarget}) {
138 // Register the MC asm info.
139 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
141 // Register the MC codegen info.
142 TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
144 // Register the MC instruction info.
145 TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
147 // Register the MC register info.
148 TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
150 // Register the elf streamer.
151 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
153 // Register the asm target streamer.
154 TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
156 TargetRegistry::RegisterNullTargetStreamer(*T,
157 createMipsNullTargetStreamer);
159 // Register the MC subtarget info.
160 TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
162 // Register the MCInstPrinter.
163 TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
165 TargetRegistry::RegisterObjectTargetStreamer(
166 *T, createMipsObjectTargetStreamer);
169 // Register the MC Code Emitter
170 for (Target *T : {&TheMipsTarget, &TheMips64Target})
171 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
173 for (Target *T : {&TheMipselTarget, &TheMips64elTarget})
174 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
176 // Register the asm backend.
177 TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
178 createMipsAsmBackendEB32);
179 TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
180 createMipsAsmBackendEL32);
181 TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
182 createMipsAsmBackendEB64);
183 TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
184 createMipsAsmBackendEL64);