1 //===-- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H
16 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/Support/DataTypes.h"
30 class MCSubtargetInfo;
33 class MipsMCCodeEmitter : public MCCodeEmitter {
34 MipsMCCodeEmitter(const MipsMCCodeEmitter &) = delete;
35 void operator=(const MipsMCCodeEmitter &) = delete;
36 const MCInstrInfo &MCII;
40 bool isMicroMips(const MCSubtargetInfo &STI) const;
41 bool isMips32r6(const MCSubtargetInfo &STI) const;
44 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle)
45 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {}
47 ~MipsMCCodeEmitter() override {}
49 void EmitByte(unsigned char C, raw_ostream &OS) const;
51 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
52 raw_ostream &OS) const;
54 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
55 SmallVectorImpl<MCFixup> &Fixups,
56 const MCSubtargetInfo &STI) const override;
58 // getBinaryCodeForInstr - TableGen'erated function for getting the
59 // binary encoding for an instruction.
60 uint64_t getBinaryCodeForInstr(const MCInst &MI,
61 SmallVectorImpl<MCFixup> &Fixups,
62 const MCSubtargetInfo &STI) const;
64 // getJumpTargetOpValue - Return binary encoding of the jump
65 // target operand. If the machine operand requires relocation,
66 // record the relocation and return zero.
67 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
68 SmallVectorImpl<MCFixup> &Fixups,
69 const MCSubtargetInfo &STI) const;
71 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump
72 // target operand. If the machine operand requires relocation,
73 // record the relocation and return zero.
74 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &STI) const;
78 // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump
80 unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
81 SmallVectorImpl<MCFixup> &Fixups,
82 const MCSubtargetInfo &STI) const;
84 unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
85 SmallVectorImpl<MCFixup> &Fixups,
86 const MCSubtargetInfo &STI) const;
88 unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
89 SmallVectorImpl<MCFixup> &Fixups,
90 const MCSubtargetInfo &STI) const;
92 // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp
93 // instruction immediate operand.
94 unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
95 SmallVectorImpl<MCFixup> &Fixups,
96 const MCSubtargetInfo &STI) const;
98 // getBranchTargetOpValue - Return binary encoding of the branch
99 // target operand. If the machine operand requires relocation,
100 // record the relocation and return zero.
101 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
102 SmallVectorImpl<MCFixup> &Fixups,
103 const MCSubtargetInfo &STI) const;
105 // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch
106 // target operand. If the machine operand requires relocation,
107 // record the relocation and return zero.
108 unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
109 SmallVectorImpl<MCFixup> &Fixups,
110 const MCSubtargetInfo &STI) const;
112 // getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
113 // 10-bit branch target operand. If the machine operand requires relocation,
114 // record the relocation and return zero.
115 unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
116 SmallVectorImpl<MCFixup> &Fixups,
117 const MCSubtargetInfo &STI) const;
119 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
120 // target operand. If the machine operand requires relocation,
121 // record the relocation and return zero.
122 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
123 SmallVectorImpl<MCFixup> &Fixups,
124 const MCSubtargetInfo &STI) const;
126 // getBranchTarget21OpValue - Return binary encoding of the branch
127 // offset operand. If the machine operand requires relocation,
128 // record the relocation and return zero.
129 unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
130 SmallVectorImpl<MCFixup> &Fixups,
131 const MCSubtargetInfo &STI) const;
133 // getBranchTarget26OpValue - Return binary encoding of the branch
134 // offset operand. If the machine operand requires relocation,
135 // record the relocation and return zero.
136 unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
137 SmallVectorImpl<MCFixup> &Fixups,
138 const MCSubtargetInfo &STI) const;
140 // getBranchTarget26OpValueMM - Return binary encoding of the branch
141 // offset operand. If the machine operand requires relocation,
142 // record the relocation and return zero.
143 unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI) const;
147 // getJumpOffset16OpValue - Return binary encoding of the jump
148 // offset operand. If the machine operand requires relocation,
149 // record the relocation and return zero.
150 unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
151 SmallVectorImpl<MCFixup> &Fixups,
152 const MCSubtargetInfo &STI) const;
154 // getMachineOpValue - Return binary encoding of operand. If the machin
155 // operand requires relocation, record the relocation and return zero.
156 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
157 SmallVectorImpl<MCFixup> &Fixups,
158 const MCSubtargetInfo &STI) const;
160 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
161 SmallVectorImpl<MCFixup> &Fixups,
162 const MCSubtargetInfo &STI) const;
164 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
165 SmallVectorImpl<MCFixup> &Fixups,
166 const MCSubtargetInfo &STI) const;
167 unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
168 SmallVectorImpl<MCFixup> &Fixups,
169 const MCSubtargetInfo &STI) const;
170 unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
171 SmallVectorImpl<MCFixup> &Fixups,
172 const MCSubtargetInfo &STI) const;
173 unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
174 SmallVectorImpl<MCFixup> &Fixups,
175 const MCSubtargetInfo &STI) const;
176 unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
177 SmallVectorImpl<MCFixup> &Fixups,
178 const MCSubtargetInfo &STI) const;
179 unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
180 SmallVectorImpl<MCFixup> &Fixups,
181 const MCSubtargetInfo &STI) const;
182 unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
183 SmallVectorImpl<MCFixup> &Fixups,
184 const MCSubtargetInfo &STI) const;
185 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
186 SmallVectorImpl<MCFixup> &Fixups,
187 const MCSubtargetInfo &STI) const;
188 unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
189 SmallVectorImpl<MCFixup> &Fixups,
190 const MCSubtargetInfo &STI) const;
191 unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
192 SmallVectorImpl<MCFixup> &Fixups,
193 const MCSubtargetInfo &STI) const;
194 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
195 SmallVectorImpl<MCFixup> &Fixups,
196 const MCSubtargetInfo &STI) const;
198 /// Subtract Offset then encode as a N-bit unsigned integer.
199 template <unsigned Bits, int Offset>
200 unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
201 SmallVectorImpl<MCFixup> &Fixups,
202 const MCSubtargetInfo &STI) const;
204 unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
205 SmallVectorImpl<MCFixup> &Fixups,
206 const MCSubtargetInfo &STI) const;
208 unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
209 SmallVectorImpl<MCFixup> &Fixups,
210 const MCSubtargetInfo &STI) const;
212 unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
213 SmallVectorImpl<MCFixup> &Fixups,
214 const MCSubtargetInfo &STI) const;
215 unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo,
216 SmallVectorImpl<MCFixup> &Fixups,
217 const MCSubtargetInfo &STI) const;
219 unsigned getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
220 SmallVectorImpl<MCFixup> &Fixups,
221 const MCSubtargetInfo &STI) const;
223 unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
224 SmallVectorImpl<MCFixup> &Fixups,
225 const MCSubtargetInfo &STI) const;
227 unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
228 SmallVectorImpl<MCFixup> &Fixups,
229 const MCSubtargetInfo &STI) const;
231 unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
232 const MCSubtargetInfo &STI) const;
234 unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
235 SmallVectorImpl<MCFixup> &Fixups,
236 const MCSubtargetInfo &STI) const;
238 unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
239 SmallVectorImpl<MCFixup> &Fixups,
240 const MCSubtargetInfo &STI) const;
241 }; // class MipsMCCodeEmitter